www.ijird.com
October, 2013
Vol 2 Issue 10
ISSN: 2278 – 0211 (Online)
Investigation And Design Of An Integrated Buck-Buck-Boost
Converter For Power Factor Correction
Hannah Monica Anoop
Student, M.Tech Power Electronics And Drives
School Of Electrical Sciences, Karunya University, Coimbatore, Tamilnadu, India
Abstract:
This paper presents the detailed analysis of an integrated buck-buck-boost (IBuBuBo) converter used for power factor correction.
It is a one-stage one-switch AC/DC converter which steps down the voltage without a transformer. It combines a buck type PFC
cell with a buck-boost type DC/DC cell. Two capacitors are sharing the voltage. Part of the input power is directly coupled to the
output. With the above features it is able to achieve a high power factor, efficient power conversion and low output voltage without
a transformer. This reduces the cost and size. The main switch handles the peak inductor current of DC/DC cell rather than the
superposition of both inductor currents.
Key words: Direct power transfer (DPT), integrated buck-buck-boost converter (IBuBuBo), power factor correction (PFC), single
stage(SS), transformerless.
1.Introduction
Because of the compact size, simple control and low cost, Single Stage converters are gaining importance. The average current of CB
(15) and critical inductance L1(40) in [1] have been corrected. Most of them used boost PFC followed by a dc/dc cell for output
voltage regulation [3],[4]. Because of boost type PFC cell, the intermediate bus voltage is higher than the line voltage [5]. A small
step-down dc/dc cell (buck or buck-boost) has very poor efficiency. So a transformer is used which causes high spike on switch in
addition to the leakage inductance. A snubber circuit is therefore needed to control the spike [2]. In [6], buck-boost PFC is used which
gives negative polarity at the output terminal. The power is processed twice which reduces the efficiency.
Figure 1: Ibububo AC/DC Converter
The proposed integrated buck-buck-boost converter keeps the intermediate bus voltage less than that of the line voltage. The
transformer is not required. The polarity of the voltage at the output terminal is positive. The input power is processed only once.
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2.Principle Of Operation
The IBuBuBo converter integrates a buck PFC cell with a buck-boost DC/DC cell. The PFC cell constitutes CB, CO, L1, D1 and S1. The
DC/DC cell constitutes CB, CO, L2, D2, D3 and S1. The initial current of both the inductors are zero as they operate in discontinuous
conduction mode (DCM). There are two modes of operation.
Mode 1(Vin (θ) ≤VB+VO): In this mode the buck PFC cell becomes inactive as the rectifier bridge is reverse biased because the sum of
the intermediate bus voltage and the output voltage is greater than the input voltage. Only the buck-boost cell sustains power to the
load. No input current is drawn. It can be divided into three periods.

Period 1: S1 is turned ON; the bus voltage VB charges the inductor L2. The load is supplied by the output capacitor CO.

Period 2: S1 is turned OFF; L2 is discharged through D3 and supplied to Co and load.
Figure 2
1) Period 3: L2 is completely discharged. The load is supplied by the output capacitor CO.
Mode 2(Vin (θ) >VB+VO): the input voltage is greater than the sum of the intermediate bus voltage and the output voltage.
Figure 3




Period 1: S1 is turned ON; L1 and L2 are charged by the difference of voltage across them.
Period 2: S1 is turned OFF; the energy of L2 is released to Co and current is supplied to the load through D3. Part of the input
power is supplied to the load directly. L1 is discharging to charge CO and CB. this period lasts as long as L2 has current.
Period 3: This period lasts as long as L1 has current and it supplies to Co and load.
Period 4: Only Co delivers power to the load.
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Vol 2 Issue 10
3.Converter Design
Following assumptions are made to do the analysis:
 all components are ideal;
 line input source is pure sinusoidal;
 the capacitors can be treated as constant DC voltage sources due to high capacitances;
 the input voltage is constant within a switching period.
A. Circuit characteristics
VT  VO  VB
(1)
The phase angles of dead-time
V
  sin 1  T
 V pk

 and 



are given as
(2)
V
        sin 1  T
 V pk




(3)
The conduction angle of the converter is
V
        2sin 1  T
 V pk




(4)
Peak currents of the inductors
iL1 _ pk
 Vin ( )  VT

L1

 
 d1TS
0
iL 2 _ pk 


    


VB
d1TS
L2
Where TS (
(5)
(6)
1
) is the switching period of the converter
fs
By considering the volt-second balance of the L1 and L2 ,the duty relations can be expressed as
(d 2  d3 )VT  d1 (Vin ( )  VT )
 Vin ( )  VT

VT

d 2  d 3  
 d1
0





     (7)
d 2 V0  d1VB
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d2 
VB
d1
V0
October, 2013
Vol 2 Issue 10
(8)
By applying charge balance of CB over a half-line period, the bus voltage can be determined
iCB
iCB
iCB
iCB
iCB
iCB
sw
sw
sw
sw
sw


1  iL1 _ pk  iL 2 _ pk  d1  


2  d 2iL1 _ pk  d 3iL1 _ pk 


(9)
1 iL1 _ pk  d1  d 2  d 3  


2  iL 2 _ pk d1

(10)
Vin ( )  VT

d1TS (d1  d 2  d3 ) 

L1
1

 

2  VB
  L d1TS d1

 2

V ( )  VT 
 Vin ( )  VT 2
d1 TS  in


L1
L1
1


2
 Vin ( )  VT  VB 2 
d1   d1 TS 
 d1TS 
VT



 L2
 Vin ( )  VT



2
L1
d1 TS 



2  Vin ( )  VT  VB 
1 
 
VT
 L2 

 Vin ( )  VT

Vin ( ) 

d T  LV
1 T



2  VB
 L

 2

2
1 S
sw
(11)
and
iCB


1
iCB
 0
sw
d
(12)
From (11)
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iCB
iCB
iCB
iCB
iCB
iCB







October, 2013
Vol 2 Issue 10
1  d12TS Vin ( )  VT
V 
Vin ( )  B 


 0 2  L1VT
L2 
 Vin 2 ( ) Vin ( ) 



L1 
d12TS   L1VT

d

2 0  VB

 (13)
 L2

 V pk 2 (sin 2  )


L1VT
d12TS  

2 0  V pk sin   VB



L1
L2



d




  Vpk  V pk (sin 2  )


sin





 

VT
d12TS   L1 





2
2
 d  d1 TS VB d




2
L
2
0


 Vpk   V pk  1  cos 2



2
d12TS  L1   VT 



2
 d  VB d
0 L2



  sin    





(14)
 V pk  V pk   A 



B





d12TS  L1  VT  2 4 



2   VB

 (15)
 L2

Where the constants A and B are
A  sin 2  sin 2
B  cos   cos 
Equating to zero

VB V pk  V pk   A 

  B


L2
L1  VT  2 4 

VB 
V pk L2 V pk    A  BVT

 
 L1 VT   2 4  V pk
(16)



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VB 
V pk 2 M
2 VT
Where

A 2 BVT 
  

2
V pk 

October, 2013
Vol 2 Issue 10
(17)
L2
M
L1
A sin 2  sin 2 

2
2
A
 sin  cos   sin  cos 
2
From equation (2)
V
sin    T
 V pk




(18)
and
cos  
V pk 2  VT 2
V pk
(19)
From equation (3)
sin   sin  
sin   
VT
V pk
VT
V pk
(20)
And
cos  
A  VT

2  V pk

V pk 2  VT 2
V pk
V pk 2  VT 2   VT

  Vpk
V pk
 
(21)
Vpk 2  VT 2  A 2VT
 
Vpk 2  VT 2
2
 2 Vpk
Vpk

2
2
V pk 2  VT 2
2 BVT 2VT
2 BVT 2VT  V pk  VT

cos   cos 


Vpk
Vpk
V pk
V pk 
V pk
V pk

(22)

0


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(23)
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October, 2013


 2 VB  VO  
1 VB  VO


2
sin



 
V pk M
 V
V pk 2


pk
VB 


2 VT 

 V pk  VB  VO V pk  VB  VO  


Vol 2 Issue 10
2
(24)
The instantaneous input current is given by
iin
iin
sw
sw

iL1 _ pk
2
d1
 Vin ( )  VT

L1

  2
 d1 TS
0



    
(25)


The average input current is given by

1
I in   iin

sw
d
From (25)
1 d12TS
I in 
 2 L1

 V
sin    VT d
pk

I in 
1 d12TS  V pk  cos   cos   



 2 L1  VT     

I in 
1 d12TS
Vpk B  VT  
 2 L1
(27)
The rms value of input current is given by

I in _ rms
I in _ rms
I in _ rms
1

iin
 
1 d12TS

 2 L1
1 d12TS

 2 L1
2
sw
d
(28)
2

 V
pk
sin    VT  d

 Vpk 2 (sin 2  )  VT 2 
d
 

  2V pk sin   VT 

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October, 2013
Vol 2 Issue 10
From (13) and (15)
I in _ rms
 2 A 
 2 A

2
d12TS V pk     VT      
1 d12TS V pk     

2 4 
2 4
 I in _ rms   2 L 
2 L1  
1
VT 2  2 BV pkVT  (29)
 2V pk  cos   cos   VT 


The average input power is given by

1
Pin   Vin ( ) iin


sw
d
(30)
Pin 

Vin    VT 2 
1 
d1 TS d
 Vin ( )

 
2 L1

Pin 
1 d12TS
 2 L1
1 d12TS
Pin 
 2 L1

 V
in
2

( )  Vin  VT d
 V pk 2 (sin 2  )  
d
 

  V pk sin  VT 

From (13) and (15)
  A

1 d12TS
Pin 
V pk V pk     BVT 
 2 L1
 2 4
 (31)
The power factor is given by

1
V ( ) iin sw d
  in
PF 
V pk
I in _ rms
2


(32)
1 d12TS
V
 2 L1 pk
  A

V pk  2  4   BVT 

 

PF 
 2  A 
V pk 1 d12TS V pk     
2 4 
2  2 L1  2
VT   2 BV pkVT 


From (29) and (31)
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  A

V pk     BVT 

2
 2 4

PF 
  2  A

2
V pk  2  4   VT   2 BV pkVT 




Vol 2 Issue 10
(33)
B. Condition for DCM
For the cells to work in DCM the critical inductance must be determined. To allow L1 working in discontinuous mode
Inequalities:
d1_PFC  d 2  d3  1
d 2  d3  1  d1_PFC
d1_PFC
 VT
  
 Vin
0

(34)
   
(35)
Where d1_PFC is the maximum d1 of PFC cell
For DC/DC cell to work in DCM, the following inequality must be held
d1_DC/ DC  d 2  1
d 2  1  d1_DC/ DC
(36)
VB
d1_DC/ DC  1  d1_DC/ DC
V0
(37)
d1_DC/ DC 
V0
V
 0
VO  VB VT
As the switch is shared in both cells of the converter, the maximum duty cycle d1_max is given by
d1_max

 d1_PFC , 
min 

d

1_DC/DC

    

d1_DC/DC
(38)
The output power is given by
Pout 
V0 2
RL _ min
(39)
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Vol 2 Issue 10
By applying input-output power balance
From (31) and (39)
   A 
2
V

V0 2
1 d1_ max TS

V pk  pk  2 4  


RL _ min  2 L1_ crit
  BVT

L1_ crit 
RL _ min

 d1_ max 2TS

V


pk
2
 2V0



 A
 V pk     BVT   (40)



  2 4 
WhereRL_min is the minimum load resistance
And L1_crit is the critical value of the inductance
The critical inductanceL2_crit is calculated from the input power to the DC/DC cell and is given by
V
 B

Pin _ DC / DC
iDC / DC
sw



iDC / DC
sw
d
0
(41)
iL 2 _ pk
2
d1
From (6)
iDC / DC
sw
Pin _ DC / DC

VB 2
d1 TS
2 L2
VB   VB 2 

d1 TS d

 0  2 L2

Pin _ DC / DC 
VB VB 2
d1 TS
 2 L2
Pin _ DC / DC 
VB 2 2
d1 TS
2 L2
(42)
(43)
(44)
From (39) and (44)
V0 2
VB 2

d1_ max 2TS
RL _ min 2 L2 _ crit
L2 _ crit 
RL _ minVB 2
2V0 2
d1_ max 2TS
(45)
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Vol 2 Issue 10
C.Capacitors optimization
E
1
CV 2
2
(46)
E  P*t
(47)
From (46) and (47)
CB 
CB 
2 Pt
V2
2 PO thold _ up
VB @ 90Vrms 
2
Where thold_up is the hold-up time
D. Distribution of Direct Power Transfer
po    po _ PFC    po _ DC / DC  
po _ PFC    VO iL1  
iL1  
sw

sw
(48)
(49)
1
iL1 _ pk  d1  d 2  d 3  
2
From (9) and (11)
iL1  
sw

2
1 S

d T  Vin ( )  VT
Vin ( ) 

2  L1VT

 2
 d1 TS

po _PF C     2

0
 Vin ( )  VT
 LV
1 T

 V ( )
 in


    


po _ DC / DC    pin_ DC / DC  
po _ DC / DC    VB iDC / DC
iDC / DC
sw

1
iL 2 _ pk d1
2

1 VB
d1TS d1
2 L2

VB 2
d1 TS
2 L2
sw
(50)
From (6)
iDC / DC
sw
iDC / DC
sw
(51)
INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH & DEVELOPMENT
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po _ DC / DC    VB iDC / DC
October, 2013
sw
Vol 2 Issue 10
(52)
From (42)
po _ DC / DC   
VBTS 2
d1  
2 L2
 iL1    
sw



I O   iD 3   sw 

 iD 3   sw
iD 3  
sw

Pin _ DC / DC
VO
   

VB 2
d12TS
2 L2VO
 d12TS  Vin ( )  VT  


 
 2  L1VT
 


2

V
I O   Vin ( )  B d12TS      
2 L2VO



2
 VB d12TS
 2 L2VO

 V ( )  VT   
 2  in
 
 d1 TS  LV
1 T
 
 2 
2 

V
Vin ( )  B       
I O  

L2VO  



2
 VB d 2T
 2 L2VO 1 S
IO 
PO
VO

 Vin ( )  VT   

2

 
  d1    TS  L1VT
 


2

2
VB  
PO 


V
(

)


in
L2VO  
VO 

2
 2
VB  d1    T
S
 2L V
2 O

INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH & DEVELOPMENT
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October, 2013
Vol 2 Issue 10

2 PO

2
 V T  Vin ( )  VT V ( )   VB 


in
 O S  L V
d1    
1 T
 L2VO 


 2 L2 PO
 VB 2TS

4.Conclusion
The proposed IBuBuBo converter, from (24), achieves a very low bus voltage. From (2) decrease of VB extends the conduction angle
giving better power factor. The power handled by both PFC cell and dc/dc cell is changed oppositely to maintain the load power under
different input conditions. At low-line condition, there is more input power coupled directly to the output. At high-line condition,
more power is delivered to the output by the dc/dc cell.
5.References
1. S. K. Ki and D. D. C. Lu, “A high step-down transformerless single-stage single-switch AC/DC converter,” IEEE
Transaction Power Electronics., vol. 28, no. 1, pp. 36-45
2. S. K. Ki and D. D. C. Lu, “Implementation of an efficient transformerless single-stage single-switchac/dc converter,” IEEE
Transaction on Industrial Electronics.., vol. 57, no. 12, pp. 4095-4105, Dec. 2010.
3. Q.Zhao, F. C. Lee, and F. –S. Tsai, “Voltage and current stress reduction in single-stage power factor correction AC/DC
converters with bulk capacirot voltage feedback,” IEEE Transaction on Power Electronics., vol 17, no. 4,pp. 749-755, May
2003.
4. O. Garcia, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, “Single phase power factor correction : A Survey,” IEEE
Transaction on Power Electronics., vol 18, no. 3,pp. 749-755,May 2003.
5. R. Redl and L. Balogh, “Design considerations for single-stage isolated power-factor-corrected power supplies with fast
regulation of output voltage,” in Proc. IEEE Application of Power Electronics Conference., 1995, vol. 1, pp. 454-458
6. M. A. Al-Saffar, E. H. Ismail, and A. J. Sabzali, “Integrated buck-boost quadratic buck PFC rectifier for universal input
applications,” IEEE Transaction on Power Electronics.,vol. 26,no. 12, pp. 2886-2896, Dec 2009.
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