Buried Contact Solar Cells using Low Temperature Epitaxial Growth
Processes
A.W. Y. Ho, S. R. Wenham, A. B. Sproul, and T. Puzzer
Key Center for Photovoltaic Engineering
Electrical Engineering Building, University of New South Wales
Sydney NSW 2052
AUSTRALIA
Telephone:
+61 02 9385 5471
Facsimile:
+61 02 9385 5412
E-mail:
anitah@student.unsw.edu.au
Abstract
High temperature processes contribute significantly to the cost and contamination risk in solar cells.
A reasonable quality aluminium doped p+ layer can be formed at the rear of an n-type silicon
substrate by aluminium induced epitaxial growth. This combination alleviates the need for junction
formation by diffusion and the boron/oxygen related defects that degrade conventional p-type
substrates. Junction and rear surface recombination can be controlled via a rear surface passivating
oxide through which the junction is formed in localised regions where the overlying aluminium
reduces the oxide. The subsequent sputtering of silicon and the low temperature annealing facilitate
the epitaxial growth of the aluminium doped layer while the displaced aluminium to the surface forms
the rear metal contact for the solar cell. High front and rear surface recombination currently limit the
performance of these devices to quite low efficiencies with the need to improve the quality of the front
and rear surface passivating oxides. At present, such oxides are quite thin (less than 100 angstroms)
and formed at relatively low temperatures with no hydrogen passivation of the interface. Modelling
of the devices gives close agreement between experimental results and theory, indicating the surface
recombination velocities to be greater than 106 cm/second.
1
BACKGROUND
Present commercial photovoltaic markets are dominated by screen printed solar cell technologies utilising conventional
Boron doped p-type monocrystalline or multicrystalline silicon wafers. Unfortunately, the performance of such devices
has remained stagnant with little performance improvement over the last 20 years (Godfrey, 1982). The best
performing production lines around the world achieve efficiencies in the vicinity of 15% using screen printed solar cell
technology. This compares with efficiencies in the 14-15% range achieved in the early 1980’s using very similar
technology (Godfrey, 1982).
In recent years, new insight has been gained regarding the recombination processes limiting the minority carrier
diffusion lengths in conventional boron doped p-type silicon substrates (Schmidt et al, 1997). Such substrates, with
high concentrations of oxygen and boron, suffer from the formation of boron/oxygen defects that significantly reduce
minority carrier lifetimes to the vicinity of 20 microseconds. In comparison, float zone wafers with similar
crystallographic quality but with much lower oxygen concentration are able to achieve minority carrier lifetimes more
than an order of magnitude higher for the same substrate resistivity. These findings have led to new research and
technology development efforts aimed at adapting fabrication techniques for the use of substrates without boron such as
phosphorus doped n-type substrates or else p-type substrates using alternative dopants such as gallium (Saitoh et al,
2000), (Zhao et al, 2000), (Wenham, 2000).
In this work, techniques to facilitate the use of phosphorus doped n-type substrates are being developed. In preliminary
work, the minority carrier lifetimes for phosphorus doped Czochralski wafers have been compared to those of boron
doped Czochralski wafers. Both substrates have been exposed to various high temperature thermal processes typical of
Buried Contact Solar Cells using Low Temperature Epitaxial Growth Processes
A.W.Y. Ho et al
those used in device fabrication. At the end of such treatments, the measurement of the respective minority carrier
lifetimes has indicated that those in the p-type Czochralski material have degraded to values in the vicinity of 20
microseconds compared with 200 microseconds for the n-type substrates of similar doping concentration. These
preliminary results provide the motivation for developing new device structures that utilise such n-type substrates.
Another aim in the present work is to develop low temperature processes that minimise the risk of wafer contamination
while potentially reducing the fabrication costs.
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NEW DEVICE STRUCTURE
The expectation of achieving long minority carrier diffusion lengths in n-type substrates opens the opportunity for
innovative device structures. For example, provided the diffusion lengths are much greater than the wafer thickness, the
opportunity exists for using rear junctions in a similar manner as has been demonstrated previously at Stanford
University (Sinton et al, 1990). To suit commercial application, however, the use of photolithographic processes must
be avoided.
Front metal contacts – grooves not shown
The proposed structure for this work is
shown in Figure 1 where the n-type wafer
shown has all surfaces passivated with a
thin, high quality thermal silicon dioxide
layer. The aim in developing this structure
Thin
is to use techniques for localised junction
n - type Si wafer
passivating
formation at the rear so as to keep the
oxide
junction and rear contact area small. This
helps minimise junction recombination and
also the impact of a high surface
p
p
Al doped
recombination velocity at the interface
epitaxial grown
between the p+ and the rear metal contact.
layer
The aim is to keep the junction area to only
a few percent of the wafer area with the
Rear metal contact
remainder of the rear surface of the n-type
Figure 1: Structure using Low Temperature Processing
wafer being passivated with a thermally
grown silicon dioxide layer. To achieve
good collection probabilities for carriers generated throughout the wafer, it is essential that adjacent localised junction
regions be located within about 10% of the minority carrier diffusion length of each other. This necessitates juxtaposed
junction regions being located within about 40 microns of each other. This can be quite challenging to achieve in nonphotolithographic processes although has been successfully demonstrated through the use of laser scribing techniques.
The most successful approach (shown in Figure 2), however, has been to rely on the use of aluminium to reduce the
underlying silicon dioxide layer in localised regions where pinholes or lower density regions exist within the silicon
dioxide layer. These can be reliably formed approximately every 15-20 microns, therefore providing a simple but
effective approach for opening small holes in the oxide layer through to the substrate surface. The subsequent
deposition of amorphous silicon onto the surface of the aluminium layer facilitates solid phase epitaxial growth of the
silicon onto the exposed localised regions of the wafer surface when exposed to temperatures in the vicinity of 500°C.
This aluminium induced solid phase epitaxial growth process (shown in Figure 3) is well documented in the literature
(Koschier et al, 2000), (Majni et al, 2000) with the grown layer being heavily doped with aluminium. The highly
reactive aluminium layer is able to reduce interfacial oxides and therefore provide an excellent interface at the wafer
surface for the nucleation of the epitaxial growth process. The quality of the grown junction however is relatively poor
due to the low minority carrier lifetimes for the heavily aluminium doped p+ grown region. Junction recombination
can, however, be reduced to acceptable levels by firstly keeping the junction area to well below the rear surface area of
the wafer and secondly by ensuring the epitaxially grown material is significantly more heavily doped than the
substrate. This latter requirement ensures that the electronic junction lies within the good crystallographic quality
material of the substrate rather than within the poor quality epitaxially grown material.
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Buried Contact Solar Cells using Low Temperature Epitaxial Growth Processes
A.W.Y. Ho et al
Thin interfacial
oxide
Heat treatment at
~500°C
n – type Si wafer
n – type Si wafer
Thin interfacial
oxide
Al
Al reduces oxide and penetrates
through the pinholes in the oxide
Figure 2: Heat Treatment for Aluminium to Reduce the Interfacial Oxide
Figure 3a, 3b: FIB Images of the Overhang of a Groove Before and After Low Temperature Annealing
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RESULTS
Current (A)
Current (A)
Light IV Curves for Batch B1
4.5E-02
B1-1
4.0E-02
3.5E-02
B1-2
B1-3
B1-4
3.0E-02
2.5E-02
2.0E-02
2.0E-02
1.5E-02
1.5E-02
1.0E-02
1.0E-02
5.0E-03
5.0E-03
1.0E-01
1.5E-01
2.0E-01
2.5E-01
3.0E-01
b8-2
3.5E-01
b8-3
3.5E-02
2.5E-02
5.0E-02
b8-1
4.0E-02
* 0.6 um p++ and Al layers
* 3 hours preheat treatment
* ~ 100A oxide
3.0E-02
0.0E+00
0.0E+00
Light IV Curve for Batch B8
4.5E-02
0.0E+00
0.0E+00
* 0.6 um p++ and Al layers
* 7 hours preheat treatment
* ~ 100A oxide
5.0E-02
1.0E-01
1.5E-01
Voltage (V)
Figure 4: IV Curves for Earlier Device
2.0E-01
2.5E-01
3.0E-01
3.5E-01
Voltage (V)
Figure 5: IV Curves for Device with Longer Heat Treatment
Figure 4 shows a typical electrical characteristic curve for the earliest devices. As can be seen, the devices suffer from a
very high series resistance, presumably associated with the low area contact between the epitaxially grown material and
the n-type substrate. It has been found experimentally that this high series resistance can be reduced by increasing the
length of the heat treatment given to the device following the aluminium deposition at the rear and prior to the
amorphous silicon deposition. This enhances the reduction of the rear surface silicon dioxide layer by the overlying
aluminium. This appears to not only increase the density of the exposed regions of the wafer surface but also increase
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Buried Contact Solar Cells using Low Temperature Epitaxial Growth Processes
A.W.Y. Ho et al
the average area for each.
By increasing this heat treatment to 7 hours, the current/voltage characteristic curve of Figure 5 was achieved,
indicating a greatly reduced series resistance for the finished devices. The shape of the curve in Figure 5 is as expected
for typical solar cells indicating that parasitic resistive losses have been reduced to acceptable levels. The short circuit
current and open circuit voltage, however, are much lower than expected.
Analysis on one of these devices fabricated on phosphorous doped substrates at 1x1016 atoms.cm-3 has indicated that
high front and rear surface recombination velocities associated with the oxide passivation of the silicon substrate can be
shown to explain the poor current and voltage results. Of particular importance in understanding the device limitations,
the spectral response shown in Figure 8 clearly indicates extremely poor performance to short wavelengths of light
absorbed within the first half of the silicon. The response to these wavelengths of light is approximately zero which
could be explained by either a short minority carrier diffusion length for the substrate or else a high surface
recombination velocity. Figure 6 reflects the relatively small percentage change in the response for short wavelengths
when the substrate minority carrier lifetime is varied. In addition, the high surface recombination velocity has been
shown to be the primary cause of poor short wavelength response as shown in Figure 7. This puts a lower bound on the
front surface recombination velocity of at least 106 cm/second with the corresponding substrate lifetime having to be
around 500 microseconds for the PC1D model to explain the response to 1 micron wavelength light. Using the results
of this analysis, PC1D has been used to model the spectral response accurately as also shown in Figure 8.
IQE with Different Substrate Minority Lifetimes
%
40
35
30
25
20
Measured IQE
PC1D IQE with bulk t = 500us
15
PC1D IQE with bulk t = 50us
PC1D IQE with bulk t = 5us
10
5
0
300
400
500
600
700
800
900
1000
Wavelength (nm)
Figure 6: Spectral Response for Various Bulk Minority Lifetimes
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Proceedings of Solar 2002 - Australian and New Zealand Solar Energy Society
1100
1200
Buried Contact Solar Cells using Low Temperature Epitaxial Growth Processes
%
100
A.W.Y. Ho et al
IQE with Different Front Surface Recombination Velocities
90
80
70
Measured IQE
60
PC1D IQE with Sf = 1e6 cm/s
50
PC1D IQE with Sf = 1e4 cm/s
40
PC1D IQE with Sf = 1e2 cm/s
30
PC1D IQE with Sf = 1 cm/s
20
10
0
300
400
500
600
700
800
900
1000
1100
1200
Wavelength (nm)
Figure 7: Spectral Response for Various Front SRV’s
%
IQE, EQE, Reflectance
70
Measured EQE
PC1D EQE
60
Measured IQE
PC1D IQE
50
Measured Reflectance Data
PC1D Pri-Surface Total Reflectance
40
30
20
10
0
300
400
500
600
700
800
Wavelength (nm)
900
1000
1100
1200
Figure 8: Spectral Response Curves for Device B8-1
These conclusions indicate the importance of improving the surface passivation. This can be done in several ways
including either the use of a thicker passivating oxide grown at higher temperature, the use of silicon nitride passivation,
and/or the use of hydrogen passivation to reduce the recombination sites at the interface between the silicon dioxide and
the wafer surface. Other approaches such as doping the surfaces can also help to reduce the effective recombination
rate at the surfaces. Interestingly, Figure 7 shows the improvements in the spectral response that would be achieved
through improved surface recombination velocity. As can be seen, if the surface recombination velocity at the front
surface can be reduced to below 100 cm/second, a good response can be achieved for all wavelengths of light with a
corresponding device efficiency in the vicinity of 90% predicted. This appears to provide the greatest potential for
future work in this area, but may necessitate the use of temperatures in excess of the current maximum of 500-600°C.
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A.W.Y. Ho et al
CONSLUSIONS
It appears that the photovoltaic industry needs to explore the options of alternative substrate dopants to try and avoid the
commonly experienced defects associated with boron/oxygen complexes. N-type phosphorus doped substrates appear
to be a good alternative provided junction formation and metal contacting schemes can be developed. For low
temperature processing, aluminium induced solid phase epitaxial growth of p-type silicon can provide an effective
mechanism of forming a p-n junction with an n-type substrate. Despite the low quality of the epitaxially grown
material, provided its doping is significantly above that of the substrate, the electronic junction can still reside in the
good quality substrate material and therefore minimise junction recombination. The poor quality of the epitaxially
grown material, however, necessitates the use of such material in only localised regions to ensure the dark saturation
current is kept to acceptably low values.
N-type substrates with similar doping concentration have demonstrated substantially higher minority carrier lifetimes
than conventional p-type doped substrates of similar doping concentration. These results indicate that it may be feasible
to use a rear junction device structure that is able to capitalise on the much longer minority carrier diffusion lengths of
the n-type wafers so as to still collect the majority of the carriers generated throughout the wafer. Early experimental
devices have managed to demonstrate adequately low parasitic losses although inadequate surface passivation has led to
relatively low currents and voltages. Further work is required to evaluate whether suitably low surface recombination
velocities can be achieved to demonstrate the viability of such structures.
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ACKNOWLEDGEMENTS
The Key Centre for Photovoltaic Engineering is established and supported by the Australian Research Council while A.
Ho wishes to acknowledge the support of the Australia Government through the provision of her Australian
Postgraduate Awards scholarship. The valuable contributions of Per Widenborg and others from the Buried Contact
Cells Research Group are also acknowledged.
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