Digital Fundamentals: A Systems
Approach
Thomas L. Floyd
Latches, Flip-Flops, and Timers
Chapter 6
Ch.6 Summary
Traffic Signal Control
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Traffic Signal Control: State Diagram
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Traffic Signal Control: Block Diagram
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Traffic Signal Control: Timing Circuits
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Latches
A latch is a temporary storage device that has two stable states
(bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds to
active-HIGH inputs; with NAND gates, it responds to active-LOW inputs.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Latches
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
Assume the latch is initially
RESET (Q = 0) and the inputs
are at their inactive level (0). To
SET the latch (Q = 1), a
momentary HIGH signal is
applied to the S input while the
R remains LOW.
To RESET the latch (Q = 0), a
momentary HIGH signal is
applied to the R input while the
S remains LOW.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Latches
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET
(Q = 0) and the inputs are at their
inactive level (1). To SET the latch
(Q = 1), a momentary LOW signal is
applied to the S input while the R
remains HIGH.
To RESET the latch a momentary
LOW is applied to the R input
while S is HIGH.
Never apply an active set and reset at the same time (invalid).
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Latches
The three modes of
basic S-R operation
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Gated S-R Latch
A gated latch is a variation on the basic latch.
The gated latch has an additional input, called enable
(EN) that must be HIGH in order for the latch to
respond to the S and R inputs.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Gated D Latch
The D latch is an variation of the S-R latch but combines the
S and R inputs into a single D input as shown:
A simple rule for the D latch is:
Q follows D when the EN is active.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be
positive or negative.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Edge-Triggered Flip-flops
The output from an edgetriggered flip-flop changes
on the positive-going or
negative-going edge of its
clock signal.
A bubble on the clock
input indicates that it is a
negative-edge triggered
flip-flop.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Edge-Triggered D Flip-flops
The data bit at the D-input is transferred to the component output
on the edge of the clock signal.
Once triggered, the output (Q) equals the last value at the D input
until a new value is triggered in.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
J-K Flip-flops
The values at the
J and K inputs to
a J-K flip-flop
determine its
output state.
The results of
the four possible
input
combinations of
J and K are
shown.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Flip-flop Asynchronous Inputs
Synchronous (clocked) inputs are transferred on the
triggering edge of the clock. Most flip-flops have other inputs
that are asynchronous, meaning they operate independently
of the clock.
Asynchronous flip-flop inputs are
normally labeled preset (PRE) and clear
(CLR). These inputs are usually active
LOW. A J-K flip flop with active LOW
preset and CLR is shown.
Note that the asynchronous inputs
always override the synchronous inputs.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Flip-Flop Frequency Division
Flip-flops can be used as frequency dividers, as shown below.
The D and J-K flip flops on the left are wired as “divide-by-2” circuits.
The J-K flip-flops on the right are cascaded to form a “divide-by-4”
circuit.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Flip-Flop Counters
Flip-flops can be
used to count the
number of clock
signals they receive
as shown here.
Each CLK input triggers
the flip-flops, which are
wired to toggle whenever
triggered.
The QA and QB outputs
indicate the number of
CLK inputs received.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Traffic Signal Control: Sequential
Logic Diagram
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Flip-Flop Propagation Delay
Propagation delay time is specified for the rising and falling
outputs. It is measured between the 50% level of the clock to the
50% level of the output transition.
Propagation delay (tPLH) is measured as shown in (a). Propagation delay
(tPHL) is measured as shown in (b).
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Flip-flop Propagation Delay
Another propagation delay time specification is the time
required for an asynchronous input to cause a change in
the output. Again it is measured from the 50% levels.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Flip-flop Set-up Time
Another time-related specification is flip-flop set-up time.
This is the minimum time between the arrival of an input to
the D (or J-K) flip-flop and the CLK signal.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Flip-flop Hold Time
Another time-related specification is flip-flop hold time.
This is the minimum time over which the input to the D (or
J-K) flip-flop must remain stable after the arrival of the CLK
input for reliable triggering.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
One-Shots
The one-shot or monostable multivibrator is a device
with only one stable state. When triggered, it goes to its
unstable state for a predetermined length of time, then
returns to its stable state.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Nonretriggerable One-Shots
A nonretriggerable one-shot does not respond to any
triggers that occur while in its unstable state, as shown here.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Retriggerable One-Shots
Retriggerable one-shots respond to any trigger, even if it
occurs while the component is in its unstable state. If it
occurs during the unstable state, the state is extended by an
amount equal to its normal output pulse width.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
A One-Shot Sequential Timer
One-shots can be wired (as shown) to form a sequential
timer; a circuit that can set up a sequence of actions, such
as lighting a group of lights in a particular order.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
555 Timer One-Shot
The 555 timer can be configured in various ways, including as
a one-shot. The pulse width is approximately tW = 1.1R1C1.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
555 Timer Astable Multivibrator
An astable multivibrator (also called a free-running
multivibrator) is a circuit that produces a steady stream of
output pulses as long as power is applied.
In this circuit C1 charges
through R1 and R2 and
discharges through only
R2. The output frequency
is given by:
1.44
f 
(R1  2R2 )C1
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
S-R Latch with VHDL and Verilog
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
D Flip-Flop with VHDL and Verilog
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
J-K Flip-Flop with VHDL and Verilog
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Traffic Signal Control: Block Diagram
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Traffic Signal Control Programming
Model
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Key Terms
Latch
Bistable
Clock
D flip-flop
J-K flip-flop
A bistable digital circuit used for storing a bit.
Having two stable states. Latches and flipflops are bistable multivibrators.
A triggering input of a flip-flop.
A type of bistable multivibrator in which the
output assumes the state of the D input on the
triggering edge of a clock pulse.
A type of flip-flop that can operate in the SET,
RESET, no-change, and toggle modes.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Key Terms
Propagation
delay time
Set-up time
Hold time
Timer
The interval of time required after an input
signal has been applied for the resulting
output signal to change.
The time interval required for the input levels
to be on a digital circuit.
The time interval required for the input levels
to remain steady to a flip-flop after the
triggering edge in order to reliably activate the
device.
A circuit that can be used as a one-shot or as
an oscillator.
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Quiz
1. The output of a D latch will not change if
a. the output is LOW
b. Enable is not active
c. D is LOW
d. all of the above
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Quiz
2. The D flip-flop shown will ______ on the next
clock pulse
a. set
b. reset
c. latch
Q
D
CLK
CLK
Q
d. toggle
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Quiz
3. How many asynchronous inputs does the J-K fllipflop below have?
PRE
a. 1
b. 2
c. 3
d. 4
Q
J
CLK
K
Q
CLR
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Quiz
4. Assume the output from a leading-edge triggered
J-K flip flop is initially HIGH. With the inputs shown,
on which clock pulse with the output will go from
HIGH to LOW?
a. 1
CLK
b. 2
J
c. 3
K
1
2
3
4
d. 4
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Quiz
5. The time interval illustrated is called
a. tPHL
b. tPLH
50% point on triggering edge
CLK
c. set-up time
d. hold time
Q
50% point on LOW-toHIGH transition of Q
?
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Quiz
6. The time interval illustrated is called
a. tPHL
D
b. tPLH
CLK
c. set-up time
d. hold time
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
?
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Quiz
7. The circuit shown below is a/an
a. astable multivibrator
b. data storage device
c. frequency multiplier
HIGH
d. frequency divider
fin
HIGH
J QA
J QB
CLK
CLK
K
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
fout
K
© 2013 by Pearson Higher Education, Inc
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Ch.6 Summary
Quiz
8. The circuit shown has parallel
data inputs and outputs. What
kind of circuit is it?
Output
lines
Q0
a. An astable multivibrator
Q1
b. A data storage circuit
Q2
c. A frequency multiplier
d. A frequency divider
Q3
Clock
Clear
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Quiz
9. A retriggerable one-shot with an active HIGH
output has a pulse width of 20 ms and is triggered
from a 60 Hz line. The output will be a
a. series of 16.7 ms pulses
b. series of 20 ms pulses
c. constant LOW
d. constant HIGH
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Quiz
10. The circuit illustrated is a
a. astable multivibrator
+VCC
b. monostable multivibrator
c. frequency multiplier
(4)
R1
(7)
d. frequency divider
R2
(6)
(2)
C1
(4)
RESET VCC
DISCH
THRES
OUT
TRIG CONT
GND
(3)
(5)
(1)
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved
Ch.6 Summary
Answers
1. b
6. d
2. d
7. d
3. b
8. b
4. c
9. d
5. b
10. a
Digital Fundamentals: A Systems Approach
Thomas L. Floyd
© 2013 by Pearson Higher Education, Inc
Upper Saddle River, New Jersey 07458 • All Rights Reserved