DESIGN OF A PHASE ANGLE/ POWER FACTOR METER WITH MATCHING OUTPUT FOR COMPUTER INTERFACE NUR HIDAYAH BINTI SI-IAHUDIN This Report Is Submitted In Partial Fulfillment of Requirements for The Bachelor's Degree in Electrical Engineering (Industrial Power) Fakulti Kejuruteraan Elektrik Kolej Universiti Teknikal Kebangsaan Malaysia May 2006
ABSTRACT A phase angle/ power factor meter with matching output for computer interface
is proposed. Usually, a set of instruments composed by a voltmeter, an ammeter and a
wattmeter, is used as the power factor (PF) standard system. The PF is then calculated
from that value being, in a derived magnitude. Using the proposed phase angle meter,
the phase angle can be read directly based on the measurement of the time signals
between current and voltage zero crossing. The voltage and current are sampled from the
main supply. The number of pulse between the current and voltage zero crossing, will
go through a 3-digit up counter. The 7-segment digital read-out will display the phase
angle.
ABSTRAK Sebuah meter untuk mengira sudut/ faktor kuasa dan output bagi nilai sudut di
keluarkan dalam bentuk 'computer interface' telah di cadangkan untuk dibina.
Kebiasannya, peralatan pengujian seperti meter voltan, meter arus dan meter kuasa
digunakan untuk mendapatkan bacaan bg faktor kuasa. Nilai yang diperolehi dikira
menggunakan formula tertentu untuk mendapatkan faktor kuasa. Meter yang
dicadangkan ini amat mudah diperolehi komponennya dan sesuai untuk tujuan
pengajaran kepada pelajar-pelajar. 'Comparator' digunakan untuk membaca gelombang
voltan dan gelombang arus. Gelombang voltan dan arus diambil simpel dari litar utama.
Bilangan signal diantara arus dan voltan yang memintas nilai kosong, akan melalui '3digit up counter'. '7-segment digital read-out' akan memaparkan bacaan bagi sudut fasa.
P R W C T INTRODUCTION
The impedance phase angle for any component is the phase shift between voltage
across that component and current through that component. For a perfect resistor, the
voltage drop and current are always in phase with each other, and so the i
m
w
angle of a resistor is said to be 0°, it is can be seen in Figure 1.1. For a perfect inductor,
voltage drop always leads current by 90°, and so an inductor's impedance phase angle is
said to be +90°, it is can be seen in Figure 1.2. For a perfect capacitor, voltage drop
always lags current by 90°, and so a capacitor's impedance phase angle is said to be -90°,
it is can be seen in Figure 1.3. It is mean phase angle is varies, and we have more
procedures to get that value. My proposed project is to get that value in easy way. With
only use the several components we can measure the value of phase angle.
I
Resistor
R = LOOR
x=on
z = ~OOQLO"
Figure 1.1: Impedance Angles of Resistor
Inductor
R=OR
100 LUH
S = LOOR
159.15 Hz
z= roofi~w~
Figure 1.2: Impedance Angles of Inductor
Capacitor
R=OQ
L59.15 Hz
Figure 1.3: Impedance Angles of Capacitor
The main objectivesof this project are:
To design a phase angle/ power factor meter to measure phase angle directly
without use voltmeter and ammeter;
To get the output which will match for computer interface;
To design a one part system in mini power system;
1.3
PROBLEM STATEMENT
Nowadays, more patent of phase angle meter were used. The phase angle meter
in market is a complicated circuit and all ready to use. The phase angle meter that were
design is to fulfill the procedures of a learning process in colleague or university. The
designing is very simple, the component is easy to found and student can learning from
the circuit. It is also the one part in of a bigger project in the mini power system.
1.4
PROJJSCT SCOPE
Designing of a phase angle/ power factor meter with will match the output for
computer interface. This phase angle/ power factor meter is design for complete a one
part of mini power system. This meter is use to measure phase angle directly without use
voltmeter and ammeter. Student also can use this project in learning process because
components in this project are easy to found. Beside that it is can improve my
knowledge in electronic circuit.
1.5
PROJECT OVERVIEW
The first stage of the project, it was based on research for the data and
information is obtained through internet, journal fiom IEEE and other sources.
The purpose of the study is to study phase angle, voltage, current, the operation
of counter and digital 7-segment. To study how the circuit works, some research about
the function of every component were doing.
After understand about the function,the component were implement on the strip
board to test either it is running or not. More steps must be completed when doing this
project.
CHAPTER 2
LITERATURE REVIEW
2.1
INTRODUCTION
As electric utilities have grown in size and the number of interconnections has
increased, planning for future expansion has become increasingly complex. The
increasing cost of additions and modifications has made it imperative that utilities
consider a range of design options, and perform detailed studies of the effects on the
system of each option, based on a number of assumptions: normal and abnormal
operating conditions, peak and off -peak loadings, and present and future years of
operation. [I]
Phase angle meter is an important equipment to use in electric utilities. This
project is to design phase angle meter which student also can use this project in learning
process because components in this project are easy to found. Phase angle is calculated
by finding the ratio of reactance divided by resistance, and taking the arctangent of that
ratio. Phase angle is normally expressed in degrees. The phase angle meter is a valuable
tool for v e r i w g the proper installation of medium- and high-voltage primary metering
equipment and sophisticated protective relays that receive input fiom Potential and
Current Transformers. Phase angle meters are also used to verifL the correct connection
of three-phase transformer banks which must be paralleled with an existing electrical
bus or high voltage line.
This equipment is also used for conducting electrical system load and power
factor studies. The system power factor is equal to the cosine of the phase angle
(expressed as a percent) that exists between the system voltage and current. Once the
system power factor is determined, the system power triangle (true power in watts,
apparent power in volt-amperes, and reactive power in vars) can be developed and
analyzed. Phase angle measurement is also employed to analyze the operation of AC
synchronous generators and synchronous motors to verify the proper operation of field
regulators and synchronizing equipment.
Nowadays, we were use the modem phase angle meter as in Figure 2.1, but that
is very complicated for student in learning process. In learning process, student must
know briefly all about the circuit of the phase angle meter. A phase angle1 power factor
meter with matching output for computer interface is proposed.
Figure 2.1 :Phase Angle Meter
2.2
LITERATURE REVIEW
In doing this project, some research was done about the phase angle. Nowadays,
there have more phase angle in market. Some research was get fiom internet such as:
(
ClmkeHess Communication Research Corpor~~fion:
I
A four arm bridge has a single generator, and at least two arms are adjusted to
produce the minimum output. With the Phase Standard, two outputs exist with an
adjustable phase shift between them. This means that two arms are sufficient for the
bridge. The bridge can be balanced by adjusting the relative amplitude of the two
lgenerators and the phase angle between them. If the two impedance arms of the bridge
have identical phase angles, the bridge will balance when the phase angle between the
two bridge inputs is exactly 180°, and each input amplitude divided by the magnitude
ofthe impedance connected to its input has the same value. All of the bridges are
designed and constructed so that the two i m m c e s have identical phase angles over a
broad range of frequencies.
Unlike the standard meter and the standard Volt, there is no standard Phase
Angle at any of the national laboratories. Because of this, one has to rely on the
properly constructed bridge set as an intrinsic standard to verifj the proper performance
of phase generating devices at an angle of 180°
Tony Thorne Applications Engineering Xuntrex Technology Inc.
SW Series products are a flexible and versatile platform used in multiple
applications. Access to the phase angle adjustment is required to properly correct the
inverter's output voltage zero crossing and the utility voltage zero crossing point. The
'PWM phase angle adjustment' is located in a key-code protected, factory only tech
menu. The PWM phase angle is set as default in firmware and is not accessible by the
end user.
Special test equipment is typically used to measure phase shift and power factor
when adjustments are needed to solve a local issue. The PWM setting is only used by
qualified technicians under the supervision of Xantrex technology.
23
SUMMARY OF CHAPTER 2
The conclusion of this chapter is that the proposed phase angle meter is very
flexible compared to the phase angle meter that has been in market. This phase angle
meter is very useful to be used in learning process since the circuit created is very
simple. Besides that student can understand more about this meter and the components
of this meter are easy to found. The next chapter will discuss about the working planning
that is used to complete this project.
CHAPTER 3 WORKING PLANNING
3.1
INTRODUCTION
This chapter is discussed more about the procedures that will be used to complete
this project such as project methodology, methodology selection justification,
componentlequipment requirement and some testing that was be done to troubleshoot
this project. The testing was being done to make sure the circuit that was created is
running. It is also to avoid any mistaken when putting the component at the strip board.
More difficulties were facing when using the electronics component and by understand
the components will be avoiding any mistaken.
3.2
METHODOLOGY SELECTION JUSTIFICATION
I
7
Study ontheliteratureredew
I
IdenMy the related canponent
I
Wn
i g iad designing circuit
r-l-J
Testing the implementing circuit
Analyre the resdt,dimionand
concllsiors
Thesis mng
Figure 3.1 :Flow Chart
-
The Flow Chart in Figure 3.1 shown the methodology selectionjustification were
done to make this project completed. This step was started on the first semester in fourth
year. The first step is study the literature review about phase angle and phase angle
meter. Understanding about the phase angle is the major thing in this project. Then, to
starting this project, proposal was being done and then will be approved by supervisor
(Prof Madya Md. Noah Bin Jamal). After that, with helping fiom supervisor the circuit
was being modeling and designing. Then the related component was been defined to
implement this circuit.
After get several component that are needed, the circuit were implemented.
Then, every connection at the circuit must be checking the continuity. There have two
parts in this project. Every part has some stage to be done and must be test to make sure
the circuit is running. If both of this part success, the result will be analyzed, and then
making discussion and conclusions. If not success, the troubleshoot must be done and
the circuit will implement again. In the same time, thesis is in progress.
3.3
COMPONENT1 EQUIPMENT REQUIREMENT
From this time, there are instruments that measure phase angle/ power factor
directly. Based on the measurement of the phase angle between current and voltage,
through the signal enter the comparator. Then, the output of the comparator will go to a
3- digit up counter circuit and the phase angle will display at the 7-segment display.
The component mentioned below is those related component are using for every
main part in this project.
1.1 3-Digit BCD Counter
The MC14553B three-digit counter, shown in Figure 3.2, consists of three
rgative edge-triggered BCD counters which are cascaded in a synchronous fashion. A
lad latch at the output of each of the three BCD counters permits storage of any given
~unt.The three sets of BCD outputs (active high), after going through the latches, are
me division multiplexed, providing one BCD number or digit at a time. Digit select
utputs (active low) are provided for display control. All outputs are TTL compatible.
An on-chip oscillator provides the low fkquency scanning clock which drives
he multiplexer output selector. The frequency of the oscillator can be controlled
:xternally by a capacitor between pins 3 and 4, or it can be overridden and driven with
tn external clock at
pin 4. Multiple devices can be cascaded using the overflow output,
which provides one pulse for every 1000 counts. [3]
The Master Reset input, when taken high, initializes the three BCD counters and
the multiplexer scanning circuit. While Master Reset is high the digit scanner is set to
digit one; but all three digit select outputs are disabled to prolong display life, and the
scan oscillator is inhibited. The Disable input, when high, prevents the input clock &om
reaching the counters, while still retaining the last count. A pulse shaping circuit at the
clock input permits the counters to continue operating on input pulses with very slow
rise times. Information present in the counters when the latch input goes high, will be
stored in the latches and will be retained while the latch input is high, independent of
other inputs. Information can be recovered from the latches after the counters have been
reset if Latch Enable remains high during the entire reset cycle. Please refer to Appendix
A for more information.
Figure 3.2: Expanded Block Diagram
33.2 BCD-to-7-Segment Decoder1 Driver
The 74HCMCT4543 is BCD to 7-segment latch/decoder/drivers for liquid
crystal displays. They have four address inputs (DO to D3), in my 3-digit up counter
circuit the input is replace with (QO to Q3), an active HIGH latch disable input (LD), an
active HIGH blanking input (BI), an active HIGH phase input (PH) and seven buffered
segment outputs (Qa to Qg). The "4543" can invert the logic levels of the output
combination, The phase (PH), blanking (BI) and latch disable (LD) inputs are used to
reverse the function table phase, blank the display and store a BCD code, respectively.
For liquid crystal displays a square-wave is applied to PH and the electrical common
back-plane of the display. The outputs of the "4543" are directly connected to the
segments of the liquid crystal. Please refer to Appendix B for more information. Figure
3.3 shown the Logic Circuit for this IC. [3]
Figure 3.3: Logic Circuit
The applicationsof BCD to 7-segment latch/ decoder/ driver are:
Driving LCD displays
Driving fluorescent displays
Driving incandescent displays
Driving gas discharge displays
3 3 3 Seven Segment Display
A 7-Segment Display consists of 7 LED'S arranged in a figure-eight pattern, such
that by selectively powering various combinations of segments alphanumeric characters
may be displayed; a fbrther LED is present which, when powered, causes a dot or
decimal point to be displayed (Figure 3.4). Each LED is turned on by forward biasing its
respective anode, all segment cathodes being commoned (Common Anode devices also
exist).
The Digital Point LED is generally used to display numbers containing a noninteger part. Table 3.1 illustrates the required segment patterns for numeric
representation, including the optional Decimal Point character. Biasing can be either
continuous or multiplexed as long as the refksh frequency is high enough to ensure
image persistence for the human eye (at least 20 cycles per second to avoid flicker).
Please refer to Appendix C for more information.
Figure 3.4: Structure of a 7-Segment Display
Table 3.1 : LED'S turned on for a given digit
X = don't care
33.4 Comparator
In electronics, a comparator is a device which compares two voltages or currents,
and switches its output to indicate which is larger. More generally, the term is also used
to refer to a device that compares two items of data. A standard op-amp can be used as a
comparator as indicated in the Figure 3.5.
Figure 3.5: Standard op-amp
A dedicated voltage comparator chip, Iike the LM339, is designed to interface
directly to digital logic (such as TTL or CMOS), since the output is a binary state, and is
often used to interface real world signals to digital circuitry. The LM339 accomplishes
this with an open-collector output. When the inverting input is higher, the output of the
comparator is connected to the negative power supply. When the noninverting input is
higher, the output is floating (has a very high impedance to ground).
33.5 Gate
In the main voltage and current circuit, two gates were used. Not gate are
function as inverter. When the input is high '1' the output of the gate is low '0'. The
output is inverting the input. The Figure 3.6 shows the symbol of not gate.
Besides that, or gate (Figure 3.7) also were used in this circuit. These devices
contain four independent 2-input or gates. Table 3.2 shows the function table for or gate
for any input. Please refer to Appendix E for more information.
Figure 3.6: Not Gate
Figure 3.7: Or Gate
Table 3.2: Function table for or gate
OUTPUT
INF'UTS
A
B
Y
H
X
X
H
L
H
H
L
L
3.4
Project Methodology
There has two main parts in this project. A 3-digit up counter circuit and the
-mainsupply voltage and current circuit. Firstly the 3-digit up counter circuit was being
designed. After identify the related component, the circuit were implemented. The
circuit are using 3-digit BCD counter, BCD-to-7-segment decoder1 driver, and 7segment display. There have 3 stages in making this part.
The stage r e q u i d in making this part is mentioned below.
3.4.1
Stage 1
Firstly, the 3digit up counter circuit for the part one in this project was designed
using an OrCad. The 3-digit BCD counter BCD-to-7-segment decoder 1 driver and
display 7-segment are used. The resistor that was used is 220Q to match with the 5V
supply and the transistor is the PNP type. Figure 3.8 shows the circuit of 3-digit up
counter.
Figure 3.8: A 3-digit up counter circuit
3.4.2
Stage 2
After completed designing the part one of this circuit, the related component was
being identified to match with this circuit. The more information about the component is
briefly explained in chapter 3.3. Then, the component was implemented to bread board
before transfer it to strip board after making a testing and troubleshoot. Before
implement, every IC that was been used must check one by one. As example for the 7segment display, one by one must be checked by give the voltage supply 5V and the
ground. Afier that the light for every pins/ part at the 7-segment was been checked either
display1lighting or not.
3.43
Stage 3
When all components were completed implementing, a testing must being done
to make sure the circuit is running. In this stage there have more problems. This circuit
did not running completely. The troubleshoot must being done repeatedly to detect the
problem. Every component must test one by one to make sure the component did not
damage.
When making a testing, an input was giving to clock, master reset and latch
enable pins. At clock pins the 18 kHz sample of frequency were given from function
generator. Function generators are using to generate frequency to the counter. Figure 3.9
shows the model of function generator.
Figure 3.9: Function Generator
The input for master reset and latch enable pins will be grounded to making the
counter read for count (low = '0') and data passes (low = '0'). The supply of 5V is
getting from DC power supply. The 5V are using to supply voltage to every component
in this circuit.
3.4.4 Main voltage and current circuit
The main voltage and current circuit supply have a 15V AC supply, capacitor
and resistor in series, comparator, not gate and or gate. The output from not gate and or
gate will be an input at master reset and latch enable at 3-digit BCD counter. The Figure
3.10 shows the main circuit of voltage and current.
As a sample in doing this project, 15V AC was used as a sample voltage across
the load and current through the load. In this part, the load that will be use is capacitor
and resistor. The value of the load must exceed 15m. This is for avoid the overcurrent
on the circuit. This is because the maximum current of the component is 1mA.
The voltage and current will flow to comparator which the function of
comparator is to get the pulse for invert to binary code '0' or '1'. The output from the
comparator will be the input at or gate and not gate. Which the binary code (output) of
both of gate will be the input of master reset and latch enable at 3-digit up counter
circuit.
Figure 3.10:Main circuit of voltage and current
CHAPTER 4 EXPECTED RESULT 4.1
Introduction
The circuit of 3-Digit Up Counter Circuit from the part one of this project is
shown in Figure 4.1.
Figure 4.1: A3-digit up counter circuit
When this project is complete, the digital 7-segment will appear the value of
phase angle depends on the generating frequency. The data will pass or latch depends on
the voltage and current through the comparator. Master Reset will count if the input is 0
(low) and will reset if the input is 1 (high). Latch Enable (LE) will give data passes if the
input is 0 (low) and will data latched if the input of LE is 1 (high). A truth table drawn
in Table 4.1 for the 3-Digit BCD counter shows a few of the modes of operation. [4]
Table 4.1 :Truth Table
t
Mode of
INPUTS
OUTPUTS
MR
CLK
DIS
LE Master reset
1
X
X
0
0000 0000 OOOOBc~ Count up
0
1
0
0
Advance count by 1 Disable clock
0
X
1
0
No change Latch outputs
0
X
X
1
Latches BCD data Master
Clock
Disable
Latch
The Clock
enable
operation
reset
1
= HIGH-@-LOW transition of clock pulse X= Irrelevant o= LOW 1= HIGH 4.2
Working of 3-Digit BCD Counter Circuit (4553 IC)
The 4553 IC contains three cascaded decade counters. Cascading counters means
that the 1s BCD counter triggers the 10s counter as it recirculates from 100lscD to
1 0 0 0 ~In~ like
~ . manner, the 10s counter triggers the 100s counter as it recirculates from
000 lBCD
to 0000 B ~ D T
. he BCD output from the three counters is fed through the
three 4-bit transparent latches. The BCD data is then transferred to a display multiplexer
circuit (7-segment display). The display multiplexing circuit will drive three seven
segment displays.
The clock input to the 4553 is negative-edge triggered. The display multiplexer
circuitry turns on just one of the three decimal displays at a time feeding the correct
BCD output to the display. The multiplexing should occur at a rate of about 40- to 80-
Hz. An external capacitor (C1)can be attached between CIA and CIBpins of the IC to set
the scan oscillator frequency. Capacitor C1 would typically have a value of about
0.001uF.
The DISABLE clock, MASTER RESET (MR), and LATCH ENABLE (LE)
inputs to the 4553 counter IC are all active-HIGH inputs and the 4-bit BCD outputs (QO
- 4 3 ) are active-HIGH. The digit select @S1, DS2, and DS3) pins are active-LOW
outputs.
A Table 4.1 shows a few of the modes of operation. These modes of operation
are the most useful but several other combinations of inputs are possible. When the MR
input pins goes HIGH the outputs are reset to 0000 0000 0 0 0 0 ~ The
~ ~ .master reset
mode of operation is shown in line 1 of the truth table in Table 4.1. The count up mode
of operation is detailed in line 2 of the truth table. On the HIGH-to-LOW transition of