Using Jasper to Verify a
Highly Configurable OnChip Network
Jasper User Group Conference 2014
Outline
Introduction
NoC requirements and challenges
Our traditional verification approach
• Verifying a highly configurable NoC
Adding Jasper Apps to the mix
• Leveraging existing System Verilog protocol checkers and DUT OVL
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© 2014, All Rights Reserved, Sonics, Inc.
Sonics – NoC IP Vendor-of-Choice
Sonics’ NoC IPs help leading SoC designers solve
Interconnect challenges in the SoC design
1333 MHz
1066 MHz
533 MHz
CortexA15
Cluster
533 MHz
CortexA7
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MaliT658
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DMA
SATA
267 MHz
133 MHz
267 MHz
267 MHz
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Memory Throughput
Physical Design
Power Management
Security
Time-to-market
Development costs
Sonics System IP:
On-chip Networks, Memory Subsystem, Power Partitioning & Management,
Performance Monitor & Debug, Security Firewalls
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About Sonics
Privately held Co. founded in 1996
•
•
Licensees
CEO: Grant A. Pierce
CTO: Drew E. Wingard, Ph.D.
More than 2.5 billion SoC units
shipped using Sonics IPs
Leading supplier of NoC interconnect
IPs with 200+ successful SoC tapeouts
138+ patented properties
Website: www.sonicsinc.com
Sonics Offices
•
•
•
Headquarters: Milpitas, California, USA
Design Centers: Chicago, Armenia
International Sales: France, India, Israel,
Japan, South Korea, Taiwan
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© 2014, All Rights Reserved, Sonics, Inc.
Partners
Sonics NoC Technology At-a-Glance
Performance: up to 2GHz speed
Scalability: Large SoCs up to 256 cores
Low Power: Fully clock gated, support
many clock and power domains
Concurrency: Virtual Channels support
to improve QoS
System Coherency: AXI ACE-lite +
AXI/OCP support
Security: TrustZone extended firewalls
Layout: Serialized router-based fabric
•
Power/Clock domains: Integrated GALS
support
•
Layout friendly: Virtual Channels, easy
domain partitioning
SoC Design Environment: Design
capture, verification, performance analysis
Sonics GHz Network-on-Chip
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© 2014, All Rights Reserved, Sonics, Inc.
Sonics NoC Architecture
Agents (IA and TA) provide…
•
Protocol conversion
•
IP core decoupling
•
Address decoding
•
Data width conversion
•
Fabric Packetization / De-packetization
•
Other advanced features
Agents and Fabric combine to form an NoC Network
User
Cores
(masters)
SGN
IA
IA
IA
IA
IA
Initiator
Agent
Fabric provides…
•
Router-based network
•
Independent request / response paths
SGN Fabric
Router
Routers support independent
data widths per input/output port
Links support clock / voltage /
power domain crossing
TA
TA
Built-In Credit-Based Flow
Control
TA
TA
TA
Target
Agent
User
Cores
(slaves)
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© 2014, All Rights Reserved, Sonics, Inc.
A highly configurable NoC
Socket protocol (AXI, OCP)
• Optional sub-setting of protocols
- MReqInfo, SRespInfo / *USER
- Opcode and/or Burst Sequence support
- Threads / Tags (concurrency)
Data width conversion between initiators and targets
• 16-bits to 256-bits
Advanced Feature Support
• ACE-Lite
• Power Management
Performance Options
• Socket retiming (pass-through or registered)
• Maximum Open Transactions (requests in-flight)
• Quality of Service
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© 2014, All Rights Reserved, Sonics, Inc.
Simulation-Based Verification
Requires Configuration Dependent:
• Directed Random Test Sequences
• Master and Slave Interface models
• DUT interface protocol checkers
• SystemC cycle-accurate reference model
- Used for cycle-by-cycle transaction verification
•
Scoreboard
Each IP block can be verified independently as well as in systems
• IA, TA, Router, AHB/APB protocol converters
• Same verification flow replicated across all IP blocks.
Must be able to run hundreds/thousands of constrained random
configurations overnight to cover the large configuration space.
• Automated PASS / FAIL summary analysis
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© 2014, All Rights Reserved, Sonics, Inc.
Verification Environment
Simulation Testbench
SVA Checker
Equivalence
Checker
TLM Adapter
AXI / OCP
OVL
DUT
OVL
SystemC
Reference Unit
Sonics Proprietary
Equivalence
Checker
SVA Checker
DUT – Design Under Test
OVL – Open Verilog (Assertion) Library
SVA – System Verilog Assertion
TLM – Transaction Level Model
© 2014 Sonics, Inc. Sonics, All rights reserved
TLM Adapter
Simulation Limitations
Build up test traffic by adding sequences:
• Testbench starts by defining and pursuing a test plan.
• Implementing that plan consumes much of the design cycle.
• In addition to taking time, coverage metrics are typically not analyzed until
the planned implementation is complete.
• This can delay finding unexpected situations until (too) late in the project.
Master and Slave behaviors are well behaved:
• To prevent false negatives
• The tested behavior is only measured by explicit cover points which are not
exploring all legal possibilities (over-constrained).
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© 2014 Sonics, Inc. Sonics, All rights reserved
Adding JasperGold® Formal Verification to the Mix
Desire was to leverage existing verification infrastructure:
• Protocol checkers
• OVL assertions
Formal verification expertise not required for implementation
Needs to work in Sonics’ regression environment
• Able to run numerous constrained random DUT configurations in a
reasonable timeframe with good coverage
• Easy to generate FV inputs in batch mode
• Easily generalized across different IP (DUT) blocks
• Support automated PASS / FAIL analysis
- No assertion failures + coverage goals achieved
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© 2014 Sonics, Inc. Sonics, All rights reserved
Verification Environment with JasperGold®
Simulation Testbench
Assume
Assert
SVA Checker
Equivalence
Checker
TLM Adapter
AXI / OCP
JasperGold®
OVL
Scoreboard
DUT
OVL
SystemC
Reference Unit
Equivalence
Checker
Assume
Assert
Sonics Proprietary
SVA Checker
DUT – Design Under Test
OVL – Open Verilog (Assertion) Library
SVA – System Verilog Assertion
TLM – Transaction Level Model
© 2014 Sonics, Inc. Sonics, All rights reserved
TLM Adapter
Verification Environment with JasperGold®
Assume
Assert
SVA Checker
Interface SVA Protocol
assertions are used asis or translated into
assumptions.
AXI / OCP
JasperGold®
OVL
Scoreboard
DUT
OVL
Assume
Assert
Sonics Proprietary
SVA Checker
DUT – Design Under Test
OVL – Open Verilog (Assertion) Library
SVA – System Verilog Assertion
TLM – Transaction Level Model
© 2014 Sonics, Inc. Sonics, All rights reserved
DUT OVL assertions are
translated into
Assume/Assert
statements based on
their context or
implementation.
Getting the JasperGold® flow running
Needed to re-write about 15% (~870 lines) of our OCP SVA checker to be
more JasperGold friendly.
• Replaced SV queue usage with synthesizable FIFO structures
• Added a couple of missing protocol assertions
• Modifying assertions to fire on presentation instead of acceptance
Checkers for other protocols needed only minimal changes.
Updated SVA checkers are shared with the Simulation Testbench.
JasperGold Tcl scripts to translate certain interface (master vs. slave)
protocol SVA assertions into assumptions and convert DUT OVL assertions
into Assume/Assert statements.
Automated the configuration inputs for JasperGold’s AXI and AHB proof kits.
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© 2014 Sonics, Inc. Sonics, All rights reserved
Results
Successfully integrated JasperGold into our constrained randomized
configuration regression strategy.
Achieved reasonable run times and coverage so that multiple configurations
of multiple IP blocks can be completed on a daily basis.
Successfully detected known design faults which gave us confidence in
JasperGold and our flow implementation.
Subsequently have identified additional DUT issues which had not previously
been encountered.
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Thank You
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© 2014, All Rights Reserved, Sonics, Inc.
