TRF3722 Quadrature Modulator with Integrated
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Sample & Buy Product Folder Tools & Software Technical Documents Support & Community TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 TRF3722 具有集成 PLL 和 VCO 的正交调制器 1 特性 • • • • • • • 1 • • • 3 说明 具有集成 PLL 和 VCO 的 IQ 调制器 整数 N/分数 N PLL 调制器支持 400MHz 至 4200MHz 频率范围 PLL 和 VCO 支持 256MHz 至 4100MHz 频率范围 900MHz 时的 OIP3 为 31 dBm 1800MHz 时的 OIP3 为 30 dBm VCO 1800MHz 开环相位噪声：1MHz 偏移时为 141 dBc/Hz 独立式 LO 输出支持 1/2/4/8 分频 调制器低功耗和高增益模式 多种断电模式 TRF3722 是一款高性能直接转换正交调制器，具有优 异的线性和低噪声性能。 基带共模电压典型值为 0.25V，支持与电流源 DAC 无缝连接。 此器件集成了 PLL 和 VCO，能够为调制器提供本地振荡器 (LO)。 PLL 和 VCO 可实现卓越的相位噪声性能，能够满足最 为严格的传输通信要求。 此器件还提供了额外的 LO 输出，用于驱动其它调制器或降频混频器。 调制器的 高增益模式可实现典型的 3dB 增益提升，低功耗模式 适合需要优化功耗的应用。 器件信息 (1) 2 应用 • • • • 部件号 封装 封装尺寸（标称值） TRF3722 VQFN (48) 7.00mm x 7.00mm (1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。 无线基础设施 – CDMA：IS95，UMTS，CDMA2000，TDSCDMA – LTE，TD-LTE，LTE Advanced – TDMA：GSM，EDGE，MC-GSM 点对点微波，点对多点微波 软件定义的无线电 射频中继器，分布式天线系统 4 方框图 BBI_P 27 29 34 36 28 25 24 13 12 6 31 VTUNE EXT_VCO BBI_N NC LO_OUTN 38 LO Div LO_OUTP 39 44 PLL Div Charge Pump PFD R Div TX Div N Div 90O 18 RFOUT 6 45 43 40 GND 37 30 26 48 BBQ_N BBQ_P 22 20 19 17 15 11 7 5 PD RDBK LD 10 CLK Serial Interface 8 47 3 DATA 1 46 VCC 4 0O Pre Scaler SDM LE 2 REFIN 41 VCC_TK 9 CP_OUT 32 35 33 42 23 21 16 14 GND 1 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. English Data Sheet: SLWS245 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 目录 1 2 3 4 5 6 7 特性 .......................................................................... 应用 .......................................................................... 说明 .......................................................................... 方框图 ...................................................................... 修订历史记录 ........................................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 1 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 Handling Ratings....................................................... 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 5 Electrical Characteristics........................................... 5 Typical Characteristics .............................................. 9 Typical Characteristics - Output Power................... 10 Typical Characteristics - Gain ................................. 11 Typical Characteristics - OIP3 ................................ 12 Typical Characteristics - OIP2 .............................. 13 Typical Characteristics - OP1dB ........................... 14 Typical Characteristics - Noise ............................. 15 Typical Characteristics - Unadjusted CF............... 16 Typical Characteristics - Unadjusted SBS ............ 17 Typical Characteristics - LO Harmonic ................. 18 Typical Characteristics - BB Harmonic ................. 20 7.17 7.18 7.19 7.20 Typical Typical Typical Typical Characteristics Characteristics Characteristics Characteristics - RF Output Return Loss . 22 - PLL/VCO ....................... 23 - Current Consumption .... 29 - Power Dissipation.......... 31 8 Parameter Measurement Information ................ 33 9 Detailed Description ............................................ 35 8.1 Serial Interface Timing Diagram ............................. 33 9.1 9.2 9.3 9.4 9.5 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Register Maps ........................................................ 35 35 36 39 42 10 Applications and Implementation...................... 55 10.1 Application Information.......................................... 55 11 Power Supply Recommendations ..................... 57 12 Layout................................................................... 58 12.1 Layout Guidelines ................................................. 58 12.2 Layout Example .................................................... 58 13 器件和文档支持 ..................................................... 59 13.1 Trademarks ........................................................... 59 13.2 Electrostatic Discharge Caution ............................ 59 13.3 术语表 ................................................................... 59 14 机械封装和可订购信息 .......................................... 59 5 修订历史记录 Changes from Original (May 2014) to Revision A Page • 从单页产品预览更改为生产..................................................................................................................................................... 1 2 Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 6 Pin Configuration and Functions CLK DATA LE GND REFIN GND VCC_PLL CP_OUT GND LO_OUTP LO_OUTN GND VQFN PACKAGE (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 PD 1 36 NC RDBK 2 35 VCC_LO2 LD 3 34 VTUNE VCC_DIG 4 33 VCC_VCO GND 5 32 VCC_TK VCC_LO1 6 GND 7 BBQ_N 8 29 BBI_N NC 9 28 NC TRF3722 31 EXT_VCO 30 GND BBQ_P 10 27 BBI_P GND 11 26 GND NC 12 NC 24 VCC_MOD4 23 GND 22 VCC_MOD3 21 GND 20 GND 19 RFOUT 18 GND 17 VCC_MOD2 16 GND 15 VCC_MOD1 14 NC 13 25 NC Pin Functions Pin I/O DESCRIPTION NAME NO. BBI_N 29 I BB in-phase input: negative BBI_P 27 I BB in-phase input: positive BBQ_N 8 I BB quadrature input: negative BBQ_P 10 I BB quadrature input: positive CLK 48 I Serial interface clock input; digital input CP_OUT 41 O Charge pump output DATA 47 I Serial interface data input; digital input EXT_VCO 31 I External local oscillator input GND 5, 7, 11, 15, 17, 19, 20, 22, 26, 30, 37, 40, 43, 45 LD 3 LE LO_OUTN LO_OUTP Ground O PLL lock detect output 46 I Serial interface latch enable; digital input 38 O Local oscillator output: negative 39 O Local oscillator output: positive NC 9, 12, 13, 24, 25, 36 NC 28 PD 1 Copyright © 2014, Texas Instruments Incorporated No connect No connect; N/C or ground to paddle I LO Div, TX Div, modulator power down (High = PD) 3 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Pin Functions (continued) Pin NAME NO. I/O DESCRIPTION RDBK 2 O Serial interface internal registers readback output REFIN 44 I Reference clock input RFOUT 18 O RF output VCC_DIG 4 3.3 V digital power supply VCC_LO1 6 3.3 V TX Div power supply VCC_LO2 35 3.3 V LO Div power supply VCC_MOD1 14 3.3 V modulator power supply VCC_MOD2 16 3.3 V modulator power supply VCC_MOD3 21 3.3 V modulator power supply VCC_MOD4 23 3.3 V modulator power supply VCC_PLL 42 3.3 V PLL power supply VCC_TK 32 3.3 V or 5 V VCO tank power supply VCC_VCO 33 3.3 V VCO power supply VTUNE 34 I VCO control voltage input 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT All VCC except VCC_TK –0.3 +3.6 V VCC_TK –0.3 +5.5 V Digital I/O voltage range –0.3 3.6 V Operating junction temperature range –40 150 °C Supply voltage range (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 Handling Ratings TSTG VESD (1) (2) Storage temperature range Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) MIN MAX UNIT –40 150 °C –2 2 kV –750 750 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) VCC MIN NOM MAX 3.3 V power-supply voltage 3 3.3 3.6 UNIT 5 V or 3.3 V power-supply voltage, VCC _TK 3 3.3/5 5.5 V V TJ Operating junction temperature range –40 125 °C TA Ambient temperature range –40 85 °C 4 Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 7.4 Thermal Information OFN THERMAL METRIC (1) RθJA Junction-to-ambient thermal resistance 27.5 RθJC(top) Junction-to-case (top) thermal resistance 12.8 RθJB Junction-to-board thermal resistance 4.3 ψJT Junction-to-top characterization parameter 0.2 ψJB Junction-to-board characterization parameter 4.3 RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8 (1) UNIT 48 PINS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C. Optimized bias settings as per Table 16 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC Parameters ICC 3.3 V Supply Current ICC_TK 5 V Supply Current PDISS IPD Total Power Dissipation Power Down Current Typical Operating Mode; LO out = Off 328 (1) mA Typical Operating Mode; LO out = On 374 mA 21 mA Typical Operating Mode; LO out = Off 1.18 W Typical Operating Mode; LO out = On 1.34 W Low Power Mode (Mod); LO out = Off 0.91 W 76 mA 2 mA Hardware Power Down Serial interface Power Down RFOUT Frequency Frequency 400 4200 MHz IQ Modulator ƒLO = 750 MHz Gain G Gain Flatness Typical Operating Mode 0.8 High Gain Mode 3.6 In 300MHz bandwidth –0.5 dB dB 0.5 dB OP1dB Output Compression Point OIP3 Output 3rd Order Intercept Point OIP2 Output 2nd Order Intercept Point SBS Unadj. SideBand Suppression –42 dBc CF Unadj. Carrier Feedthrough –50 dBm NSDO Output Noise Spectral Density BB inputs terminated on 50 Ω –159 dBm/Hz HD2LO LO Second Harmonic Measured at 2 x fLO –49 dBc HD3LO LO Third Harmonic Measured at 3 x fLO –47 dBc HD2BB Baseband Second Harmonic Measured at fLO ± 2 x fBB –72 dBc HD3BB Baseband Third Harmonic Measured at fLO ± 3 x fBB –70 dBc (1) 10.2 dBm FBB = 4.5, 5.5 MHz 31 dBm FBB = 4.5, 5.5 MHz 62 dBm Powered down output buffer and LO divider. Copyright © 2014, Texas Instruments Incorporated 5 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Electrical Characteristics (continued) Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C. Optimized bias settings as per Table 16 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ Modulator ƒLO = 900 MHz G Gain Gain Flatness Typical Operating Mode 0.8 High Gain Mode 3.6 In 300MHz bandwidth OP1dB Output Compression Point OIP3 Output 3rd Order Intercept Point OIP2 Output 2nd Order Intercept Point SBS Unadj. Side Band Suppression CF Unadj. Carrier Feed through NSDO Output Noise Spectral Density BB inputs terminated on 50 Ω HD2LO LO Second Harmonic HD3LO LO Third Harmonic HD2BB HD3BB –0.5 dB dB 0.5 dB 10 dBm FBB = 4.5, 5.5 MHz 31 dBm FBB = 4.5, 5.5 MHz 62.5 dBm –42.5 dBc –50 dBm –159 dBm/Hz Measured at 2 x fLO –47 dBc Measured at 3 x fLO –54.5 dBc Baseband Second Harmonic Measured at fLO ± 2 x fBB –65.5 dBc Baseband Third Harmonic Measured at fLO ± 3 x fBB –71.5 dBc 0.3 dB IQ Modulator ƒLO = 1800 MHz G Gain Gain Flatness OP1dB Output Compression Point OIP3 Output 3rd Order Intercept Point OIP2 Output 2nd Order Intercept Point SBS Unadj. Side Band Suppression CF Unadj. Carrier Feed through NSDO Output Noise Spectral Density HD2LO LO Second Harmonic HD3LO Typical Operating Mode High Gain Mode In 300 MHz bandwidth 3 –0.5 dB 0.5 dB 13 dBm fBB = 4.5, 5.5 MHz 29.5 dBm fBB = 4.5, 5.5 MHz 57 dBm –54.5 dBc –57 dBm BB inputs terminated on 50 Ω –158 dBm/Hz Measured at 2 x fLO –36.5 dBc LO Third Harmonic Measured at 3 x fLO –33.5 dBc HD2BB Baseband Second Harmonic Measured at fLO ± 2 x fBB –65.5 dBc HD3BB Baseband Third Harmonic Measured at fLO ± 3 x fBB –73 dBc RLO RF Output Return Loss 6 dB 0.2 dB IQ Modulator ƒLO = 2150 MHz G Gain Gain Flatness Typical Operating Mode High Gain Mode In 300 MHz bandwidth 3 –0.5 dB 0.5 dB OP1dB Output Compression Point OIP3 Output 3rd Order Intercept Point OIP2 Output 2nd Order Intercept Point SBS Unadj. Side Band Suppression –43 dBc CF Unadj. Carrier Feedt hrough –42 dBm NSDO Output Noise Spectral Density BB inputs terminated on 50 Ω –157 dBm/Hz HD2LO LO Second Harmonic Measured at 2 x fLO –40 dBc HD3LO LO Third Harmonic Measured at 3 x fLO –31 dBc HD2BB Baseband Second Harmonic Measured at fLO ± 2 x fBB –51 dBc HD3BB Baseband Third Harmonic Measured at fLO ± 3 x fBB –69 dBc 6 11.6 dBm FBB = 4.5, 5.5 MHz 30 dBm FBB = 4.5, 5.5 MHz 43 dBm Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 Electrical Characteristics (continued) Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C. Optimized bias settings as per Table 16 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ Modulator ƒLO = 2700 MHz G Gain Gain Flatness Typical Operating Mode 0 High Gain Mode In 300MHz bandwidth OP1dB Output Compression Point OIP3 Output 3rd Order Intercept Point OIP2 Output 2nd Order Intercept Point SBS Unadj. Side Band Suppression CF Unadj. Carrier Feed through NSDO Output Noise Spectral Density BB inputs terminated on 50 Ω HD2LO LO Second Harmonic HD3LO LO Third Harmonic HD2BB HD3BB dB 2.4 –0.5 dB 0.5 dB 10.4 dBm FBB = 4.5, 5.5 MHz 29.5 dBm FBB = 4.5, 5.5 MHz 45.5 dBm –33 dBc –39.6 dBm –156 dBm/Hz Measured at 2 x fLO –29 dBc Measured at 3 x fLO –37 dBc Baseband Second Harmonic Measured at fLO ± 2 x fBB –53 dBc Baseband Third Harmonic Measured at fLO ± 3 x fBB –68 dBc Typical Operating Mode –2 dB High Gain Mode 0.4 dB 8.7 dBm IQ Modulator ƒLO = 3600 MHz G Gain OP1dB Output Compression Point OIP3 Output 3rd Order Intercept Point FBB = 4.5, 5.5 MHz 24.5 dBm OIP2 Output 2nd Order Intercept Point FBB = 4.5, 5.5 MHz 45.5 dBm SBS Unadj. Side Band Suppression –31.5 dBc CF Unadj. Carrier Feed through –39.5 dBm HD2LO LO Second Harmonic Measured at 2 x fLO –28.4 dBc HD3LO LO Third Harmonic Measured at 3 x fLO –31.5 dBc HD2BB Baseband Second Harmonic Measured at fLO ± 2 x fBB –55 dBc HD3BB Baseband Third Harmonic Measured at fLO ± 3 x fBB –65 dBc Baseband Inputs VCM Common Mode Voltage Baseband I/Q input BWBB Baseband Bandwidth 1 dB Bandwidth ZinBB Baseband Input Impedance 0 0.25 0.5 900 V MHz Resistance 5 kΩ Capacitance 4 pF Reference Oscillator Parameters Fref Zinref Reference Frequency Max Reference Input Sensitivity Reference Input Impedance 350 0.2 Parallel capacitance Parallel resistance MHz 3.3 VPP 2 pF 2.2 kΩ PFD, CP FPFD PFD Frequency Max, refer to the Application Information ICP_OUT Charge Pump Current Max 1.94 mA In-band Normalized PN Floor Integer Mode –221 dBc/Hz Copyright © 2014, Texas Instruments Incorporated 65 MHz 7 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Electrical Characteristics (continued) Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C. Optimized bias settings as per Table 16 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCO fVCO VCO Frequency range KV VCO gain VTUNE = 1.1 V VCO Open Loop Phase Noise; fVCO = 3600 MHz; TX Div = Div-by-1; fOUT = 3600 MHz VTUNE = 1.1 V 10 kHz –74 100 kHz –109 1 MHz –135 10 MHz –152 40 MHz –156 PN VCO Open Loop Phase Noise; fVCO = 3600 MHz; TX Div = Div-by-2; fOUT = 1800 MHz; VTUNE = 1.1 V 2050 4100 30 10 kHz –80 100 kHz –115 1 MHz –141 10 MHz –156 40 MHz –158 MHz MHz/V dBc/Hz dBc/Hz LO Output fOUT Output frequency range PLO Output power Divide by 1 2050 4100 Divide by 2 1025 2050 Divide by 4 512.5 1025 Divide by 8 256.25 SE at 1800 MHz, OUTBUF_BIAS = 2 512.5 1 External VCO input Frequency Range 250 External VCO Input Level –10 MHz 0 dBm 4200 MHz 10 dBm Close Loop PLL or VCO Integrated Phase Noise VCO Close Loop Phase Noise; fVCO = 3600 MHz; TX DIV = Div-by-2; fOUT = 1800 MHz; Integer Mode, PFD = 2.56MHz Frac-N; PFD = 15.36 MHz; fOUT = 3532.89 MHz; Integration BW =1 kHz to 10 MHz; SSB -45.2 dB Int-N; PFD = 2.56 MHz; fOUT = 1799.68 MHz; Integration BW = 500 Hz to 20 MHz; SSB -49.8 dB 10 kHz –96 100 kHz –114 1 MHz –140 10 MHz –156 40 MHz –158 dBc/Hz Digital Interface VIH High Level Input Voltage 2 VIL Low Level Input Voltage 0 VOH High Level Output Voltage Referenced to VCC_DIG VOL Low Level Output Voltage Referenced to VCC_DIG 8 3.3 V 0.8 0.8 x VCC V V 0.2 x VCC V Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 7.6 Typical Characteristics 7.6.1 Modulator Output Spectrum BB HD 3 d Sig M De sir e er I M Un w an te d Sid eb a nd 2 3 nd rd Or d Or d er I BB HD 2 na l Graphical illustration of the modulator output spectrum with two tones is shown in Figure 1. = (F B2 ± B2 1 BB FB -F 2 BB LO LO B 3F + 1 LO F BB 3 + LO LO 2 )+ BB B1 FB 2F + + 2 LO (F BB = 1 H BB nd F 2 2F + LO F1 22F O = L H + rd F3 B2 F B LO = + F2 B1 FB 2 = -F F1 F1 2 LO )+ 1 BB -F L = nd L rd F2 F3 LO = B1 B2 FB B1 B2 FB FB FB = -2 -3 -3 -2 B1 B2 LS LS LO LO LO LO FBBn = Fn = F3rdH/L F2ndH/L LO = LSBn HD2BB HD3BB Freq. Baseband Frequency RF Frequency = 3rd Order Intermodulation Product Frequency (High Side / Low Side) = 2nd Order Intermodulation Product Frequency (High Side / Low Side) Local Oscillator Frequency = Lower Sideband Frequency = Baseband second harmonic (High Side / Low Side) = Baseband thrid harmonic (High Side / Low Side) Figure 1. Graphical Illustration of Modulator Output Spectrum Copyright © 2014, Texas Instruments Incorporated 9 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 7.7 Typical Characteristics - Output Power Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, I/Q frequency (fBB) 4.5 MHz and 5.5 MHz,500 mVPP, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16. Total Pout is two tones combined power. 6 6 TA = -40qC TA = 25qC TA = 85qC 2 2 0 0 -2 -4 -2 -4 -6 -6 -8 -8 -10 -10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D015 0 Figure 2. Total POUT vs Temperature, Typical operating mode. 6 6 4 4 2 2 0 0 -2 -4 TA = -40qC TA = 25qC TA = 85qC -8 -2 -4 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -8 -10 -10 0 500 0 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D017 Figure 4. Total POUT vs Temperature, High Gain Mode 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D219 Figure 5. Total POUT vs Supply, High Gain Mode 6 6 TA = -40qC TA = 25qC TA = 85qC 4 2 2 0 0 -2 -4 -2 -4 -6 -6 -8 -8 -10 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 4 POUT (dBm) POUT (dBm) 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D218 -6 -6 -10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D019 Figure 6. Total POUT vs Temperature, Low Power Mode 10 500 Figure 3. Total POUT vs Supply, Typical Operating Mode POUT (dBm) POUT (dBm) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 4 POUT (dBm) POUT (dBm) 4 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D220 Figure 7. Total POUT vs Supply, Low Power Mode Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 7.8 Typical Characteristics - Gain Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, I/Q frequency (fBB) 4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16. 6 6 TA = -40qC TA = 25qC TA = 85qC 2 2 0 0 -2 -4 -6 -6 -8 -8 -10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D003 0 Figure 8. Voltage Gain vs Temperature, Typical Operating Mode 6 6 4 4 2 2 0 0 -2 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D004 Figure 9. Voltage Gain vs Supply, Typical Operating Mode G (dB) G (dB) -2 -4 -10 -4 -2 -4 -6 -6 TA = -40qC TA = 25qC TA = 85qC -8 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -8 -10 -10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D005 0 Figure 10. Voltage Gain vs Temperature, High Gain Mode 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D006 Figure 11. Voltage Gain vs Supply, High Gain Mode 6 6 TA = -40qC TA = 25qC TA = 85qC 4 2 2 0 0 -2 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 4 G (dB) G (dB) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 4 G (dB) G (dB) 4 -2 -4 -4 -6 -6 -8 -8 -10 -10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D007 Figure 12. Voltage Gain vs Temperature, Low Power Mode Copyright © 2014, Texas Instruments Incorporated 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D008 Figure 13. Voltage Gain vs Supply, Low Power Mode 11 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 7.9 Typical Characteristics - OIP3 Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, I/Q frequency (fBB) 4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16. Reported OIP3 is minimum of low side and high side. 34 34 TA = -40qC TA = 25qC TA = 85qC 32 30 32 30 28 OIP3 (dBm) OIP3 (dBm) 28 26 24 26 24 22 22 20 20 18 18 16 16 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D009 0 Figure 14. OIP3 vs Temperature, Typical Operating Mode 30 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 32 30 28 OIP3 (dBm) 28 26 24 26 24 22 22 20 20 18 18 16 16 0 500 0 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D011 Figure 16. OIP3 vs Temperature, High Gain Mode 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D012 Figure 17. OIP3 vs Supply, High Gain Mode 34 34 TA = -40qC TA = 25qC TA = 85qC 32 30 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 32 30 28 OIP3 (dBm) 28 OIP3 (dBm) 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D010 34 TA = -40qC TA = 25qC TA = 85qC 32 26 24 26 24 22 22 20 20 18 18 16 16 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D013 Figure 18. OIP3 vs Temperature, Low Power Mode 12 500 Figure 15. OIP3 vs Supply, Typical Operating Mode 34 OIP3 (dBm) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D014 Figure 19. OIP3 vs Supply, Low Power Mode Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 7.10 Typical Characteristics - OIP2 Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, I/Q frequency (fBB) 4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16. Reported OIP2 is minimum of low side and high side. 70 70 TA = -40qC TA = 25qC TA = 85qC 60 60 55 55 50 45 50 45 40 40 35 35 30 30 0 500 0 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D021 Figure 20. OIP2 vs Temperature, Typical Operating Mode 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D022 70 TA = -40qC TA = 25qC TA = 85qC 65 60 55 55 OIP2 (dBm) 60 50 45 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 65 50 45 40 40 35 35 30 30 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D023 0 Figure 22. OIP2 vs Temperature, High Gain Mode 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D024 Figure 23. OIP2 vs Supply, High Gain Mode 70 70 TA = -40qC TA = 25qC TA = 85qC 65 60 60 55 55 50 45 50 45 40 40 35 35 30 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 65 OIP2 (dBm) OIP2 (dBm) 500 Figure 21. OIP2 vs Supply, Typical Operating Mode 70 OIP2 (dBm) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 65 OIP2 (dBm) OIP2 (dBm) 65 30 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D025 Figure 24. OIP2 vs Temperature, Low Power Mode Copyright © 2014, Texas Instruments Incorporated 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D026 Figure 25. OIP2 vs Supply, Low Power Mode 13 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 7.11 Typical Characteristics - OP1dB Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, I/Q frequency (fBB) 5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16. 16 16 TA = -40qC TA = 25qC TA = 85qC 14 12 12 OP1dB (dBm) OP1dB (dBm) 10 14 8 6 4 8 6 4 2 2 0 0 -2 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D027 0 Figure 26. OP1dB vs Temperature, Typical Operating Mode TA = -40qC TA = 25qC TA = 85qC 12 12 OP1dB (dBm) 10 14 8 6 4 10 8 6 4 2 2 0 0 -2 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D029 0 Figure 28. OP1dB vs Temperature, High Gain Mode 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D030 Figure 29. OP1dB vs Supply, High Gain Mod 16 16 TA = -40qC TA = 25qC TA = 85qC 14 12 10 8 6 4 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 14 12 OP1dB (dBm) OP1dB (dBm) 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D028 16 14 10 8 6 4 2 2 0 0 -2 -2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D031 Figure 30. OP1dB vs Temperature, Low Power Mode 14 500 Figure 27. OP1dB vs Supply, Typical Operating Mode 16 OP1dB (dBm) 10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D032 Figure 31. OP1dB vs Supply, Low Power Mode Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 7.12 Typical Characteristics - Noise -150 -150 -152 -152 -154 -154 -156 -156 NSD (dBm/Hz) NSD (dBm/Hz) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, BB inputs terminated to 50 ohms and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16. -158 -160 -162 -164 -160 -162 -164 -166 -166 TA = -40qC TA = 25qC TA = 85qC -168 -170 200 600 1000 1400 1800 Frequency (MHz) 2200 -170 200 2600 600 1000 D045 -152 -152 -154 -154 -156 -156 NSD (dBm/Hz) -150 -158 -160 -162 1400 1800 Frequency (MHz) 2200 2600 D046 Figure 33. Noise vs Supply, Typical Operating Mode -150 -164 -158 -160 -162 -164 -166 -166 TA = -40qC TA = 25qC TA = 85qC -168 -170 200 600 1000 1400 1800 Frequency (MHz) 2200 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -168 -170 200 2600 600 1000 D047 Figure 34. Noise vs Temperature, High Gain Mode -150 -152 -152 -154 -154 -156 -156 -158 -160 -162 -164 1400 1800 Frequency (MHz) 2200 2600 D048 Figure 35. Noise vs Supply, High Gain Mode -150 NSD (dBm/Hz) NSD (dBm/Hz) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -168 Figure 32. Noise vs Temperature, Typical Operating Mode NSD (dBm/Hz) -158 -158 -160 -162 -164 -166 -166 TA = -40qC TA = 25qC TA = 85qC -168 -170 200 600 1000 1400 1800 Frequency (MHz) 2200 -170 200 2600 D049 Figure 36. Noise vs Temperature, Low Power Mode Copyright © 2014, Texas Instruments Incorporated VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -168 600 1000 1400 1800 Frequency (MHz) 2200 2600 D050 Figure 37. Noise vs Supply, Low Power Mode 15 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 7.13 Typical Characteristics - Unadjusted CF -30 -30 -35 -35 -40 -40 Unadj. CF (dBm) Unadj. CF (dBm) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, TA = 25°C, I/Q frequency (fBB) 4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT.Optimized bias settings as per Table 16. -45 -50 -55 -60 -45 -50 -55 -60 TA = -40qC TA = 25qC TA = 85qC -65 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -65 -70 -70 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D033 0 -30 -30 -35 -35 -40 -40 -45 -50 -55 -60 -50 -55 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -65 -70 -70 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D035 0 Figure 40. Unadjustable CF vs Temperature, High Gain Mode -30 -30 -35 -35 -40 -40 -45 -45 -50 -55 -60 -65 -70 TA = -40qC TA = 25qC TA = 85qC -75 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D036 Figure 41. Unadjustable CF vs Supply, High Gain Mode Unadj. CF (dBm) Unadj. CF (dBm) -45 -60 TA = -40qC TA = 25qC TA = 85qC -65 -50 -55 -60 -65 -70 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -75 -80 -80 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D037 Figure 42. Unadjustable CF vs Temperature, Low Power Mode 16 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D034 Figure 39. Unadjustable CF vs Supply, Typical Operating Mode Unadj. CF (dBm) Unadj. CF (dBm) Figure 38. Unadjustable CF vs Temperature, Typical Operating Mode 500 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D038 Figure 43. Unadjustable CF vs Supply, Low Power Mode Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 7.14 Typical Characteristics - Unadjusted SBS -25 -25 -30 -30 -35 -35 Unadj. SBS (dBc) Unadj. SBS (dBc) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA = 25°C, I/Q frequency (fBB) 4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT.Optimized bias settings as per Table 16. -40 -45 -50 TA = -40qC TA = 25qC TA = 85qC -55 -40 -45 -50 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -55 -60 -60 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D221 0 -25 -25 -30 -30 -35 -35 -40 -45 -50 TA = -40qC TA = 25qC TA = 85qC -55 -40 -45 -50 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -55 -60 -60 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D223 0 Figure 46. Unadjustable SBS vs Temperature, High Gain Mode -25 -25 -30 -30 -35 -35 -40 -45 -50 TA = -40qC TA = 25qC TA = 85qC -55 -60 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D224 Figure 47. Unadjustable SBS vs Supply, High Gain Mode Unadj. SBS (dBc) Unadj. SBS (dBc) 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D222 Figure 45. Unadjustable SBS vs Supply, Typical Operating Mode Unadj. SBS (dBc) Unadj. SBS (dBc) Figure 44. Unadjustable SBS vs Temperature, Typical Operating Mode 500 -40 -45 -50 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -55 -60 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D225 Figure 48. Unadjustable SBS vs Temperature, Low Power Mode Copyright © 2014, Texas Instruments Incorporated 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D226 Figure 49. Unadjustable SBS vs Supply, Low Power Mode 17 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 7.15 Typical Characteristics - LO Harmonic -20 -20 -25 -25 -30 -30 HD2LO (dBc) HD2LO (dBc) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C, I/Q frequency (fBB) 4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16. -35 -40 -45 -50 -35 -40 -45 -50 TA = -40qC TA = 25qC TA = 85qC -55 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -55 -60 -60 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D051 0 -20 -20 -25 -25 -30 -30 -35 -40 -45 -50 -35 -40 -45 -50 TA = -40qC TA = 25qC TA = 85qC -55 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -55 -60 -60 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D053 0 -20 -20 -25 -25 -30 -30 -35 -40 -45 -50 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D202 Figure 53. LO Second Harmonic vs Supply, High Gain Mode HD2LO (dBc) HD2LO (dBc) Figure 52. LO Second Harmonic vs Temperature, High Gain Mode -35 -40 -45 -50 TA = -40qC TA = 25qC TA = 85qC -55 -60 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -55 -60 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D055 Figure 54. LO Second Harmonic vs Temperature, Low Power Mode 18 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D201 Figure 51. LO Second Harmonic vs Supply, Typical Operating Mode HD2LO (dBc) HD2LO (dBc) Figure 50. LO Second Harmonic vs Temperature, Typical Operating Mode 500 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D203 Figure 55. LO Second Harmonic vs Supply, Low Power Mode Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 Typical Characteristics - LO Harmonic (continued) -25 -25 -30 -30 -35 -35 -40 -40 -45 -45 HD3LO (dBc) HD3LO (dBc) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C, I/Q frequency (fBB) 4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16. -50 -55 -60 -65 -50 -55 -60 -65 -70 -70 TA = -40qC TA = 25qC TA = 85qC -75 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -75 -80 -80 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D057 0 -25 -25 -30 -30 -35 -35 -40 -40 -45 -45 -50 -55 -60 -65 -50 -55 -60 -65 -70 -70 TA = -40qC TA = 25qC TA = 85qC -75 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -75 -80 -80 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D059 0 Figure 58. LO Third Harmonic vs Temperature, High Gain Mode -25 -25 -30 -30 -35 -35 -40 -40 -45 -45 -50 -55 -60 -65 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D205 Figure 59. LO Third Harmonic vs Supply, High Gain Mode HD3LO (dBc) HD3LO (dBc) 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D204 Figure 57. LO Third Harmonic vs Supply, Typical Operating Mode HD3LO (dBc) HD3LO (dBc) Figure 56. LO Third Harmonic vs Temperature, Typical Operating Mode 500 -50 -55 -60 -65 -70 TA = -40qC TA = 25qC TA = 85qC -75 -80 -70 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -75 -80 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D061 Figure 60. LO Third Harmonic vs Temperature, Low Power Mode Copyright © 2014, Texas Instruments Incorporated 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D206 Figure 61. LO Third Harmonic vs Supply, Low Power Mode 19 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 7.16 Typical Characteristics - BB Harmonic -40 -40 -45 -45 -50 -50 HD2BB (dBc) HD2BB (dBc) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA = 25°C, I/Q frequency (fBB) 4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16. Reported BB harmonic is from (fBB) 4.5MHz. -55 -60 -65 -70 -60 -65 -70 TA = -40qC TA = 25qC TA = 85qC -75 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -75 -80 -80 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D063 0 Figure 62. BB-HD2 vs Temperature, Typical Operating Mode -40 -40 -45 -45 -50 -50 -55 -60 -65 -70 -55 -60 -65 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -75 -80 -80 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D065 0 Figure 64. BB-HD2 vs Temperature, High Gain Mode -40 -40 -45 -45 -50 -50 -55 -60 -65 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D208 Figure 65. BB-HD2 vs Supply, High Gain Mode HD2BB (dBc) HD2BB (dBc) 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D207 -70 TA = -40qC TA = 25qC TA = 85qC -75 -55 -60 -65 -70 -70 TA = -40qC TA = 25qC TA = 85qC -75 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -75 -80 -80 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D067 Figure 66. BB-HD2 vs Temperature, Low Power Mode 20 500 Figure 63. BB-HD2 vs Supply, Typical Operating Mode HD2BB (dBc) HD2BB (dBc) -55 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D209 Figure 67. BB-HD2 vs Supply, Low Power Mode Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 Typical Characteristics - BB Harmonic (continued) -50 -50 -55 -55 -60 -60 HD3BB (dBc) HD3BB (dBc) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA = 25°C, I/Q frequency (fBB) 4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16. Reported BB harmonic is from (fBB) 4.5MHz. -65 -70 -75 -80 -70 -75 -80 TA = -40qC TA = 25qC TA = 85qC -85 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -85 -90 -90 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D069 0 Figure 68. BB-HD3 vs Temperature, Typical Operating Mode -50 -55 -55 -60 -60 -65 -70 -75 -80 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D210 -65 -70 -75 -80 TA = -40qC TA = 25qC TA = 85qC -85 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -85 -90 -90 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D071 0 Figure 70. BB-HD3 vs Temperature, High Gain Mode -50 -55 -55 -60 -60 -65 -70 -75 -80 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D211 Figure 71. BB-HD3 vs Supply, High Gain Mode -50 HD3BB (dBc) HD3BB (dBc) 500 Figure 69. BB-HD3 vs Supply, Typical Operating Mode -50 HD3BB (dBc) HD3BB (dBc) -65 -65 -70 -75 -80 TA = -40qC TA = 25qC TA = 85qC -85 -90 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -85 -90 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D073 Figure 72. BB-HD3 vs Temperature, Low Power Mode Copyright © 2014, Texas Instruments Incorporated 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D212 Figure 73. BB-HD3 vs Supply, Low Power Mode 21 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 7.17 Typical Characteristics - RF Output Return Loss Unless specified all plots were created at RFOUT pin using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA = 25°C 5 2.5 S22 RFOUT S22 (dB) 0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 400 Frequency (400 MHz to 4200 MHz) 800 1200 1600 2000 2400 2800 3200 3600 4000 Frequency (MHz) D120 Figure 75. RFOUT S22 vs Frequency Figure 74. Smith Chart 22 Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 7.18 Typical Characteristics - PLL/VCO Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set to 61.44 MHz. Optimized bias settings as per Table 16. -25 -25 TA = -40qC TA = 25qC TA = 85qC -75 -100 -125 -150 10k 100k 1M Offset Frequency (Hz) 10M -100 -125 -175 500 1k 40M 10k D087 Figure 76. Open Loop Phase Noise at 450 MHz vs Temperature 100k 1M Offset Frequency (Hz) 10M 40M D088 Figure 77. Open Loop Phase Noise at 450 MHz vs Supply -25 -25 TA = -40qC TA = 25qC TA = 85qC VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -50 Phase Noise (dBc/Hz) -50 Phase Noise (dBc/Hz) -75 -150 -175 500 1k -75 -100 -125 -150 -75 -100 -125 -150 -175 500 1k 10k 100k 1M Offset Frequency (Hz) 10M -175 500 1k 40M 100k 1M Offset Frequency (Hz) 10M 40M D090 Figure 79. Open Loop Phase Noise at 900 MHz vs Supply -25 -25 TA = -40qC TA = 25qC TA = 85qC VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -50 Phase Noise (dBc/Hz) -50 -75 -100 -125 -75 -100 -125 -150 -150 -175 500 1k 10k D089 Figure 78. Open Loop Phase Noise at 900 MHz vs Temperature Phase Noise (dBc/Hz) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -50 Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) -50 10k 100k 1M Offset Frequency (Hz) 10M 40M D091 Figure 80. Open Loop Phase Noise at 1800 MHz vs Temperature Copyright © 2014, Texas Instruments Incorporated -175 500 1k 10k 100k 1M Offset Frequency (Hz) 10M 40M D092 Figure 81. Open Loop Phase Noise at 1800 MHz vs Supply 23 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Typical Characteristics - PLL/VCO (continued) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set to 61.44 MHz. Optimized bias settings as per Table 16. -25 Phase Noise (dBc/Hz) -50 -75 Phase Noise (dBc/Hz) 450 MHz 900 MHz 1800 MHz 2150 MHz 2700 MHz 3600 MHz 4000 MHz -100 -125 -150 -175 500 1k 10k 100k 1M Offset Frequency (Hz) 10M 40M Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) 100k 1M Offset Frequency (Hz) 10M 40M Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) 100k 1M Offset Frequency (Hz) 10M 40M D098 Figure 86. 1800 MHz Frac-N (Closed Loop Phase Noise) vs Supply 24 100k 1M Offset Frequency (Hz) 10M 40M D095 TA = -40qC TA = 25qC TA = 85qC 10k 100k 1M Offset Frequency (Hz) 10M 40M D097 Figure 85. 1800 MHz Frac-N (Closed Loop Phase Noise) vs Temperature VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 10k -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k D096 Figure 84. 450 MHz Frac-N (Closed Loop Phase Noise) vs Supply -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k 10k Figure 83. 450 MHz Frac-N (Closed Loop Phase Noise) vs Temperature VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 10k TA = -40qC TA = 25qC TA = 85qC D215 Figure 82. Open Loop Phase Noise vs Frequency -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k TA = -40qC TA = 25qC TA = 85qC 10k 100k 1M Offset Frequency (Hz) 10M 40M D099 Figure 87. 2150 MHz Frac-N (Closed Loop Phase Noise) vs Temperature Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 Typical Characteristics - PLL/VCO (continued) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V Phase Noise (dBc/Hz) -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k 10k 100k 1M Offset Frequency (Hz) 10M 40M -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k TA = -40qC TA = 25qC TA = 85qC 10k D100 100k 1M Offset Frequency (Hz) 10M 40M D101 Figure 88. 2150 MHz Frac-N (Closed Loop Phase Noise) vs Supply Figure 89. 2700 MHz Frac-N (Closed Loop Phase Noise) vs Temperature -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k Phase Noise (dBc/Hz) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 10k 100k 1M Offset Frequency (Hz) 10M 40M TA = -40qC TA = 25qC TA = 85qC 10k D102 100k 1M Offset Frequency (Hz) 10M 40M D103 Figure 90. 2700 MHz Frac-N (Closed Loop Phase Noise) vs Supply Figure 91. 3600 MHz Frac-N (Closed Loop Phase Noise) vs Temperature -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 1k VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set to 61.44 MHz. Optimized bias settings as per Table 16. 10k 100k 1M Offset Frequency (Hz) 10M 40M D104 Figure 92. 3600 MHz Frac-N (Closed Loop Phase Noise) vs Supply Copyright © 2014, Texas Instruments Incorporated 450MHz, Div8 900MHz, Div4 1800MHz, Div2 3600MHz, Div1 10k 100k 1M Offset Frequency (Hz) 10M 40M D105 Figure 93. 450, 900, 1800, 3600 MHz Closed Loop Phase Noise vs Offset Frequency 25 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Typical Characteristics - PLL/VCO (continued) -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 TA = -40qC TA = 25qC TA = 85qC PFD Spur (dBc) PFD Spur (dBc) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set to 61.44 MHz. Optimized bias settings as per Table 16. 0 500 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D106 VCC = 3.15,4.75 VCC = 3.30,5.00 VCC = 3.45,5.25 0 500 Figure 95. PFD Spur vs Supply 1 x PFD 2 x PFD 3 x PFD PFD Spur (dBc) PFD Spur (dBc) Figure 94. PFD Spur vs Temperature -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 0 500 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D108 PFD = 0.68MHz PFD = 1.28MHz PFD = 2.56MHz 0 500 TA = -40qC TA = 25qC TA = 85qC 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D213 Figure 98. 1 x Reference Spur vs Temperature 26 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D227 Figure 97. PFD Spur vs Frequency REF Spur (dBc) REF Spur (dBc) Figure 96. PFD Spur vs PFD Multiples -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D107 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 VCC = 3.15,4.75 VCC = 3.30,5.00 VCC = 3.45,5.25 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D214 Figure 99. Reference Spur vs Supply Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 Typical Characteristics - PLL/VCO (continued) -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 Frac Spur (dBc) REF Spur (dBc) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set to 61.44 MHz. Optimized bias settings as per Table 16. 1 x REF 2 x REF 3 x REF 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) - 61.44MHz D111 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 0.0001 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 0.0001 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 0.001 0.01 0.1 0.2 0.5 1 2 3 5 10 20 Frequency (MHz) - 3609.6MHz D113 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 0.0001 0.01 0.1 0.2 0.5 1 2 3 5 10 20 Frequency (MHz) - 3609.6MHz D112 TA = -40qC TA = 25qC TA = 85qC 0.001 0.01 0.1 0.2 0.5 1 2 3 5 10 20 Frequency (MHz) - 1843.2MHz D114 Figure 103. 1843.2 MHz Integer Boundary Spur vs Temperature -18 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -20 -22 -24 Kv (MHz/V) Frac Spur (dBc) Figure 102. 3609.6 MHz Integer Boundary Spur vs Supply -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 0.0001 0.001 Figure 101. 3609.6 MHz Integer Boundary Spur vs Temperature Frac Spur (dBc) Frac Spur (dBc) Figure 100. Reference Spur vs Reference Multiples TA = -40qC TA = 25qC TA = 85qC -26 -28 -30 -32 VCO_SEL 0 VCO_SEL 1 -34 VCO_SEL 2 VCO_SEL 3 -36 0.001 0.01 0.1 0.2 0.5 1 2 3 5 10 20 Frequency (MHz) - 1843.2MHz D115 0 5 10 15 20 25 30 35 40 45 50 55 60 65 VCO_TRIM D217 V(tune) = 1.1 V Figure 104. 1842.2 MHz Integer Boundary Spur vs Supply Copyright © 2014, Texas Instruments Incorporated Figure 105. KVCO vs VCO Trim 27 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Typical Characteristics - PLL/VCO (continued) 8 4600 4400 4200 4000 3800 3600 3400 3200 3000 2800 2600 2400 2200 2000 1800 VCO_SEL 0 VCO_SEL 1 VCO_SEL 2 VCO_SEL 3 7 6 LO POUT (dBm) Frequency (MHz) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set to 61.44 MHz. Optimized bias settings as per Table 16. 5 4 3 2 1 0 TA = -40qC TA = 25qC TA = 85qC -1 -2 0 5 0 10 15 20 25 30 35 40 45 50 55 60 65 VCO_TRIM D216 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D116 V(tune) = 1.1 V Figure 106. Frequency vs VCO_TRIM Figure 107. LO Output Power at LO_OUTP vs Temperature 8 7 LO Harmonics (dBc) LO POUT (dBm) 6 5 4 3 2 1 0 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V -1 -2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D117 Figure 108. LO Output Power at LO_OUTP vs Supply 28 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 2nd Harmonic 3rd Harmonic 5th Harmonic 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D118 Figure 109. LO Harmonics at LO_OUTP vs Frequency Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 7.19 Typical Characteristics - Current Consumption Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA = 25°C, . Optimized bias settings as per Table 16 420 420 TA = -40qC TA = 25qC TA = 85qC 412 404 396 396 388 388 ICC (mA) ICC (mA) 404 380 372 372 364 356 356 348 348 340 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D228 0 Figure 110. 3.3V Supply Current vs Temperature, Typical Operating Mode 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D229 Figure 111. 3.3V Supply Current vs Supply, Typical Operating Mode 420 420 TA = -40qC TA = 25qC TA = 85qC 412 404 404 396 396 388 388 380 372 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 412 ICC (mA) ICC (mA) 380 364 340 380 372 364 364 356 356 348 348 340 340 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D230 Figure 112. 3.3V Supply Current vs Temperature, High Gain Mode 256 254 252 250 248 246 244 242 240 238 236 234 232 230 0 TA = -40qC TA = 25qC TA = 85qC 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D232 Figure 114. 3.3V Supply Current vs Temperature, Low Power Mode Copyright © 2014, Texas Instruments Incorporated 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D231 Figure 113. 3.3V Supply Current vs Supply, High Gain Mode ICC (mA) ICC (mA) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 412 256 254 252 250 248 246 244 242 240 238 236 234 232 230 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D233 Figure 115. 5V Supply Current vs Supply, Low Power Mode 29 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Typical Characteristics - Current Consumption (continued) 28 28 TA = -40qC TA = 25qC TA = 85qC 27.8 27.6 27.6 27.4 ICC_TK (mA) ICC_TK (mA) 27.4 27.2 27 26.8 27.2 27 26.8 26.6 26.6 26.4 26.4 26.2 26.2 26 26 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D234 Figure 116. 5V Supply Current vs Temperature, Typical Operating Mode 30 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 27.8 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D235 Figure 117. 5V Supply Current vs Temperature, Typical Operating Mode Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 7.20 Typical Characteristics - Power Dissipation Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA = 25°C, . Optimized bias settings as per Table 16. 1.8 1.8 TA = -40qC TA = 25qC TA = 85qC 1.7 1.6 1.6 1.5 3.3V PDISS (W) 1.5 3.3V PDISS (W) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 1.7 1.4 1.3 1.2 1.4 1.3 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D075 0 500 Figure 118. 3.3 V PDISS vs Temperature, Typical Operating Mode Figure 119. 3.3 V PDISS vs Supply, Typical Operating Mode 1.8 1.8 TA = -40qC TA = 25qC TA = 85qC 1.7 1.6 1.6 1.5 3.3V PDISS (W) 3.3V PDISS (W) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 1.7 1.5 1.4 1.3 1.2 1.1 1.4 1.3 1.2 1.1 1 1 0.9 0.9 0.8 0.8 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D077 0 500 Figure 120. 3.3 V PDISS vs Temperature, High Gain Mode 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D078 Figure 121. 3.3 V PDISS vs Supply, High Gain Mode 1.4 1.4 TA = -40qC TA = 25qC TA = 85qC 1.3 1.2 1.1 1 0.9 0.8 1.2 1.1 1 0.9 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D079 Figure 122. 3.3 V PDISS vs Temperature, Low Power Mode Copyright © 2014, Texas Instruments Incorporated VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 1.3 3.3V PDISS (W) 3.3V PDISS (W) 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D076 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D080 Figure 123. 3.3 V PDISS vs Supply, Low Power Mode 31 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Typical Characteristics - Power Dissipation (continued) Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA = 25°C, . Optimized bias settings as per Table 16. 1.8 1.8 TA = -40qC TA = 25qC TA = 85qC 1.7 1.6 1.5 1.5 1.4 1.4 PDISS (W) PDISS (W) 1.6 1.3 1.2 1.3 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D081 0 Figure 124. Total PDISS vs Temperature, Typical Operating Mode 1.6 1.6 1.5 1.4 1.4 PDISS (W) 1.5 1.3 1.2 VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 1.7 1.1 1.3 1.2 1.1 1 1 0.9 0.9 0.8 0.8 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D083 0 Figure 126. Total PDISS vs Temperature, High Gain Mode 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D084 Figure 127. Total PDISS vs Supply, High Gain Mode 1.4 1.4 TA = -40qC TA = 25qC TA = 85qC 1.3 1.2 1.2 1.1 1.1 1 1 0.9 0.8 0.9 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D085 Figure 128. Total PDISS vs Temperature, Low Power Mode VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 1.3 PDISS (W) PDISS (W) 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D082 1.8 TA = -40qC TA = 25qC TA = 85qC 1.7 32 500 Figure 125. Total PDISS vs Supply, Typical Operating Mode 1.8 PDISS (W) VCC = 3.15V, 4.75V VCC = 3.30V, 5.00V VCC = 3.45V, 5.25V 1.7 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) D086 Figure 129. Total PDISS vs Supply, Low Power Mode Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 8 Parameter Measurement Information 8.1 Serial Interface Timing Diagram The TRF3722 features a four-wire serial programming interface (4WI) that controls an internal 32-bit shift register with seven parallel registers. There are total of three signals that must be applied: the clock (CLK), the serial data (DATA), and the latch enable (LE). The fouth signal is the read back (RDBK) signal. The serial data (DB0-DB31) are loaded least significant bit (LSB) first, and read on the rising edge of the CLK. LE is asynchronous to the CLK signal; at its rising edge, the data in the shift register are loaded into the selected internal register. Figure 130 shows the timing diagram the 4WI. Table 1 lists the 4WI timing for the write operation. tsu1 REGISTER WRITE t(CLK) t(CH) 32nd Write clock pulse 1st Write clock pulse CLOCK DB0 (LSB) Address Bit0 DATA t(CL) th DB1 Address Bit1 DB2 Address Bit2 DB3 Address Bit3 DB29 DB30 tsu3 DB31 (MSB) tsu2 tw End of Write Cycle pulse LATCH ENABLE Figure 130. 4WI Writing Timing Diagram Table 1. 4WI Timing for Write Operation Parameter Symbol Min Typ Max Units Hold time, data to clock th 20 ns Setup time, data to clock tSU1 20 ns Clock low duration tCH 20 ns Clock High duration tCL 20 ns Setup time, clock to enable tSU2 20 ns Clock period tCLK 50 ns Enable Time tW 50 ns Setup time, Latch to Data tSU3 70 ns Copyright © 2014, Texas Instruments Incorporated 33 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn TRF3722 integrates 7 registers: Register 0 (000) to Register 6 (110). Registers 1 through 6 are used to set-up and control the TRF3722 functionalities, while register 0 is used for the read-back function. Each read-back is composed by two phases: writing followed by the actual reading of the internal data. This is shown in the timing diagram in Figure 131. tsu1 th t( CLK) T(CL) nd 32 Write clock pulse st REG ISTER WR ITE 1 CLOCK Write clock pulse T(CH) DB0 (LSB) Address Bit0 DB1 Address Bit1 DB3 Address Bit3 DB2 Address Bit2 DB29 DB30 DB 31 (MSB) DATA tsu2 tw ³(QGRI:ULWH&\FOH´ pulse LATCH ENABLE nd CLOCK 32 Write clock pulse st 1 Read clock pulse READBACK nd rd 32 Read clock pulse 33 Read clock pulse tw tsu2 LATCH ENABLE nd 2 Read clock pulse ³(QGRI:ULWH&\FOH´ pulse td ReadBack Data Bit0 READBACK DATA Read Back Data Bit29 Read Back Data Bit1 ReadBack Data Bit31 ReadBack Data Bit30 Figure 131. 4WI Read-Back Timing Diagram During the writing phase a command is sent to TRF3722 register 0 to set it in read-back mode and to specify which register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred into the RDBK pin and can be read at the following falling edge (LSB first). The first clock after the LE goes high (end of writing cycle) is idle and the following 32 clocks pulses will transfer the internal register content to the RDBK pin. Table 2 shows the Readback timing. Table 2. 4WI Timing for Readback Timing Parameter Symbol Min Hold time, data to clock th 20 Typ Max Units ns Setup time, data to clock tSU1 20 ns Clock low duration tCH 20 ns Clock High duration tCL 20 ns Setup time, clock to enable tSU2 20 ns Setup time, enable to Readback clock tSU3 20 ns Delay time, clock to Readback data output td 10 Enable Time tW 50 ns Clock period t(CLK) 50 ns 34 Comments Equals Clock period Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 9 Detailed Description 9.1 Overview TRF3722 integrates a high performance direct conversion quadrature modulator with exceptional linearity and low noise performance. The modulator which upconverts low frequency baseband signal to high frequency RF typically operates at 0.25 V common mode. It supports seamless interface with current source DACs. It also features high gain and low power operating modes. Additionally, TRF3722 integrates PLL and VCO to provide the local oscillator (LO) to the integrated modulator. The PLL and VCO provides excellent phase noise and extremely low spurious performance. The device also provides an LO output for driving another modulator or mixer. TRF3722 supports the use of an external VCO or LO signal. 9.2 Functional Block Diagram BBI_P 27 29 34 36 28 25 24 13 12 6 31 VTUNE EXT_VCO BBI_N NC LO_OUTN 38 LO Div LO_OUTP 39 44 PLL Div Charge Pump PFD R Div TX Div N Div 90O 45 43 40 GND 37 30 26 48 Serial Interface Copyright © 2014, Texas Instruments Incorporated BBQ_N BBQ_P 22 20 19 17 15 11 7 5 PD RDBK LD 10 CLK VCC 18 RFOUT 6 8 47 3 DATA 1 46 35 33 42 23 21 16 14 4 0O Pre Scaler SDM LE 2 REFIN 41 VCC_TK 9 CP_OUT 32 GND 35 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 9.3 Feature Description 9.3.1 RF Output The RF output is single ended and can drive a 50-Ω load. It can be tuned with the use of an output matching network to optimize the linearity and return loss performance within a selected band. 9.3.2 Baseband Inputs The baseband inputs consist of the in-phase signal (I) and the quadrature-phase signals (Q). These I and Q signals are differential. The baseband lines are nominally biased at 0.25-V common-mode voltage (VCM); however, the device can operate with a VCM in the range of 0 V to 0.5 V. The baseband input lines are normally terminated externally 50 Ω on TRF3722 evaluation board, though it is possible to modify this value if necessary to match to an external filter load impedance requirement. 9.3.3 LO Output The LO outputs are open collector differential outputs and are biased externally. These differential outputs can be tuned to optimized output power along with OUTBUF_BIAS register settings. It also is possible to use LO outputs in single ended mode. 9.3.4 PLL Architecture Figure 132 shows a block diagram of the PLL architecture. The VCO output frequency (fVCO) is given by Equation 1: f f VCO = REF x PLL DIV x RDIV æ ö ççNINT + NFRAC ÷÷ ÷ ççè 25 ø÷ 2 (1) f fPFD = REF RDIV (2) PLL DIV = 2PLL_DIV_SEL (3) æ NFRAC ö÷ ÷÷ f VCO = fPFD x PLL DIV x çççNINT + çè 225 ø÷ (4) Where fREF is the reference input frequency, RDIV is the reference divider division ratio and the phase frequency detector frequency is fPFD. PLL_DIV_SEL controls the division ratio of the programmable divider (PLL DIV) before the dual-modulus prescaler (DMP). NINT and NFRAC/225 is the integer and fractional part of the fractional divider (N.f), respectively. In Integer mode, the fractional setting is ignored and Equation 5 is applied. f VCO = fPFD x PLL DIV x NINT (5) The complete feedback divider block consists of a PLL DIV, DMP, and N.f. The prescaler can be programmed as either a 4/5 or an 8/9. N.f includes an A and M digital counters. 36 Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 Feature Description (continued) Ext VCO/ Ext LO Ext Loop Filter LO_DIV_SEL CP_OUT LO Div fREF RDIV fPFD PFD Charge Pump TX Quad Div fVCO VTUNE fLO O° fTX 9O° TX_DIV_SEL NINT N Div SDM DMP 4/5 8/9 PLL DIV PRSC_SEL PLL_DIV_SEL NFRAC_DIV Figure 132. PLL Architecture 9.3.5 External VCO An external LO or VCO signal may be applied. If an external LO is used the internal PLL can be powered down. Alternatively, dividers, phase-frequency detector, and charge pump can remain enabled and may be used to control the VTUNE of an external VCO. EN_EXTVCO is used to select the internal or external VCO. 9.3.6 Loop Filter Loop filter design is critical for achieving low closed loop phase noise. Complete modulator performance data has been measured using integer mode loop filter. The integer mode loop filter was designed considering loop bandwidth 40 kHz and fPFD 2.56 MHz. Phase margin of 60 degrees was considered. Refer to TRF3722EVM User’s Guide to obtain the details on TRF3722 loop component calculations. Figure 133, shows integer loop filter. VTUNE CP_OUT C2 2.2nF C1 150pF R3 1.5K C3 150pF R4 0R C4 NS R2 6.49K Figure 133. Integer Loop Filter Copyright © 2014, Texas Instruments Incorporated 37 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Feature Description (continued) Frac-N performance data is obtained using the fractional loop filter shown in Figure 134. 40 kHz loop bandwidth and 15.36 MHz PFD was considered. VTUNE CP_OUT C2 10nF C1 1nF R3 1.1K C3 330pF R4 1.1K C4 330pF R2 1.1K Figure 134. Fractional Loop Filter 9.3.7 Lock Detect The lock detect signal is generated in the phase frequency detector by comparing the two input signals. When the two compared phase signals remain aligned for several clock cycles, an internal signal goes high. The precision of this comparison is controlled through the LD_ANA_PREC bits. This internal signal is then averaged and compared against a reference voltage to generate the lock detect (LD) signal. The number of averages used is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked, LD is high. When the VCO frequency is not locked, LD may pulse high or exhibit periodic behavior. By default, the internal lock detect signal is made available on the LD terminal. Register bits MUX_CTRL can be used to control a multiplexer to output other diagnostic signals on the LD output. 38 Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 9.4 Device Functional Modes 9.4.1 Selecting PLL Divider Values With reference to the PLL architecture shown in Figure 132, operation of the PLL requires TX_DIV_SEL / LO_DIV_SEL, PLL_DIV_SEL, RDIV, NINT, NFRAC and PRSC_SEL bits to be calculated. a. TX_DIV_SEL / LO_DIV_SEL The LO to the integrated modulator (ƒTX) and additional LO output (ƒLO) frequency is related to fVCO according to the following: ƒTX = fVCO / TX DIV ƒLO = fVCO / LO DIV Where TX DIV and LO DIV are related to TX_DIV_SEL and LO_DIV_SEL as: TX_DIV_SEL / LO_DIV_SEL TX_DIV / LO_DIV Frequency Range TX_DIV_SEL = 0 TX DIV = 1 2050 MHz ≤ ƒTX ≤ 4100 MHz TX_DIV_SEL = 1 TX DIV = 2 1025 MHz ≤ ƒTX ≤ 2050 MHz TX_DIV_SEL = 2 TX DIV = 4 512.5 MHz ≤ ƒTX ≤ 1025 MHz TX_DIV_SEL = 3 TX DIV = 8 256.25 MHz ≤ ƒTX ≤ 512.5 MHz LO_DIV_SEL = 0 LO DIV = 1 2050 MHz ≤ ƒLO ≤ 4100 MHz LO_DIV_SEL = 1 LO DIV = 2 1025 MHz ≤ ƒLO ≤ 2050 MHz LO_DIV_SEL = 2 LO DIV = 4 512.5 MHz ≤ ƒLO ≤ 1025 MHz LO_DIV_SEL = 3 LO DIV = 8 256.25 MHz ≤ ƒLO ≤ 512.5 MHz b. PLL_DIV_SEL Given fVCO, select PLL_DIV_SEL so that the division ratio PLL DIV limits the input frequency to the prescaler , fDMP, is limited to a maximum of 3000 MHz. PLL DIV = min(1, 2, 4) such that fDMP ≤ 3000 MHz PLL DIV is related to PLL_DIV_SEL according to the following equation: PLL_DIV = 2PLL_DIV_SEL This calculation can be restated as Equation 6. æ LO DIV x fLO ÷ö ÷ = Ceiling PLL DIV = Ceiling çç çè 3000 MHz ÷ø çæ TX DIV x fTX ÷÷ö ççè 3000 MHz ÷ø (6) For both integer and fractional mode it is preferable to operate the fPFD at the highest possible frequency determined by the required frequency step of the RFOUT or LO_OUT. In Integer mode, select the maximum fPFD according to Equation 7. fPFD = f VCO, Stepsize PLL DIV = fTX, Stepsize x TX DIV PLL DIV (7) In Fractional mode, small RF stepsize can be obtained through the fractional divider. In this case, the highest fPFD frequency should be selected according to the reference clock and system requirements. Copyright © 2014, Texas Instruments Incorporated 39 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn c. RDIV, NINT, NFRAC, PRSC_SEL The remaing PLL parameters are calculated according to the following equations: RDIV = fREF fPFD æ f ö NINT = floor ççç VCO x RDIV ÷÷÷ çè fREF x PLL DIV ÷ø éææ f ù ö ÷ö NFRAC = floor êêçççççç VCO x RDIV ÷÷÷ - NINT÷÷÷ x 225 úú ÷ ç ç ÷ f x PLL DIV è ø ø ëêè REF ûú The DMP division ratio (P/P+1) can be set to 4/5 or 8/9 through the PRSC_SEL bit. To allow proper fractional operation, set PRSC_SEL according to: PRSC_SEL = 0, (P/P+1) = 4/5 for 20 ≤ NINT < 72 in integer mode or 23 ≤ NINT < 75 in fractional mode. PRSC_SEL = 1, (P/P+1) = 8/9 for NINT ≥ 72 in integer mode or NINT ≥ 75 in fractional mode. The PRSC_SEL limit at NINT < 75 applies to Fractional mode with third-order modulation. In Integer mode, the PRSC_SEL = 8/9 should be used with NINT as low as 72. The divider block accounts for either value of PRSC_SEL without requiring NINT or NFRAC to be adjusted. Then, calculate the maximum input frequency (fN) to the digital divider. Use the lower of the possible prescaler divide settings, P = (4,8), as shown by Equation 8. fN = f VCO PLL DIV x P (8) Verify that the frequency into the digital divider, fN, is less than or equal to 375 MHz. If fN exceeds 375 MHz, choose a larger value for PLL_DIV_SEL and recalculate fPFD, RDIV, NINT, NFRAC, and PRSC_SEL. 9.4.2 Setup Example for Integer Mode Suppose the following operating characteristics fractional example are desired for Integer mode operation: • fREF = 61.44 MHz (reference input frequency) • Step at RF = 2.56 MHz (RF channel spacing) • fRF = 1799.68 MHz (RF frequency) The VCO range is 2050 MHz to 4100 MHz. Therefore: • LO DIV = 2 (LO_DIV_SEL = 1) • fVCO = LO DIV × 1799.68 MHz = 3599.36 MHz In order to keep the frequency of the prescaler below 3000 MHz: • PLL_DIV = 2 (PLL_DIV_SEL = 1) The desired stepsize at RF is 2.56 MHz, so: • fPFD = 2.56 MHz • fVCO, stepsize = PLL_DIV × fPFD = 5.12 MHz Using the reference frequency along with the required fPFD gives: • RDIV = 24 • NINT = 703 NINT ≥ 75; therefore, select the 8/9 prescaler. fN = 3599.36 MHz/(2 × 8) = 224.96 MHz < 375 MHz This example shows that Integer mode operation gives sufficient resolution for the required stepsize. 9.4.3 Integer and Fractional Mode Selection The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO) frequency is an integer multiple of fPFD, then select integer mode otherwise select fractional mode. In Integer mode, the feedback divider ratio is an integer, and the fraction is zero. Thus, bits corresponding to the fractional control in integer mode are don’t care and fractional divider functionality is disabled. 40 Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 In Fractional mode, the accuracy of the final frequency is set by 25-bit resolution. The RF stepsize is fPFD/225 which is less than 1 Hz for fPFD up to 33 MHz. The appropriate fractional control bits in the serial register must be programmed. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK, and ISOURCE_TRIM values according to the chosen frequency band. 9.4.4 Selecting the VCO and VCO Frequency Control To achieve a broad frequency tuning range, the TRF3722 integrates multiple VCOs. Each VCO tank uses a bank of coarse tuning capacitor to bring VCO frequency within a few MHz of the desired value. For a given LO frequency an appropriate VCO and capacitor array must be selected. The device integrates logic that automatically selects an appropriate VCO and capacitor array, such that in closed loop V(TUNE) is approximately equal to the open loop calibration reference voltage set by VCO_CAL_REF. An on-chip temperature sensor automatically adjusts this reference voltage so that proper lock can be maintained over the temperature range. The calibration logic is driven by a CAL_CLK signal which is scaled version of the reference frequency according to CAL_CLK_SEL. For optimum accuracy It is recommended to limit the CAL_CLK frequency to 600 kHz. When VCO_SEL_MODE is '0', the device automatically selects the VCO and the capacitor array. When VCO_SEL_MODE is '1', the VCO selected by VCO_SEL is used and the logic automatically selects the capacitor array. The VCO and capacitor array settings resulting from the calibration can be read from Register 0 - read back register. Automatic calibration can be disabled by setting CAL_BYPASS to '1'. In this manual calibration mode, the VCO is selected through register bits VCO_SEL, while the capacitor array is selected through register bits VCO_TRIM. Calibration modes are summarized in Table 3. Table 3. VCO Calibration Modes CAL_BYPASS VCO_SEL_MODE MAX CYCLES CAL_CLK 0 0 46 0 1 34 VCO_SEL Automatic 1 don't care N/A VCO_SEL VCO_TRIM Copyright © 2014, Texas Instruments Incorporated VCO CAPACITOR ARRAY Automatic 41 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 9.5 Register Maps Table 4. Serial interface Register Summary Bit Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register Address Register Address Register Address Register Address Register Address Register Address Bit5 PWD_PLL RSV Bit6 PWD_CP Bit0 Bit1 Bit2 Bit3 Bit4 RSV IB_MOD_GM Bit7 PWD_VCO Bit8 PWD_VCO_MUX Bit9 PWD _DIV124 Bit10 PWD_PRESC IB_MOD_LO VCO_TRIM Bit11 RDIV RSV VCO_BIAS Bit12 PWD_OUTBUF NINT Bit13 PWD_LO_DIV EN_LOCKDET Bit14 PWD_TX_DIV VCO_TEST_MODE Bit15 PWD_MOD Bit16 EN_EXTVCO VCOBUF_BIAS CAL_BYPASS VCOMUX_BIAS Bit17 NFRAC Bit18 RSV Bit19 REF_INV RSV MUX_CTRL EN_ISOURCE OUTBUF_BIAS ISOURCE_SINKB LD_ANA_PREC Bit20 NEG_VCO RSV Bit21 ISOURCE_TRIM PLL_DIV_SEL CP_TRISTATE Bit22 Bit23 VCO_CAL_IB ICP PRSC_SEL SPEEDUP LO_DIV_SEL Bit24 LD_DIG_PREC VCO_CAL_REF RSV Bit25 LO_DIV_BIAS Bit26 ICPDOUBLE MOD_ORD VCO_SEL VCO_AMPL_CTRL Bit27 TX_DIV_SEL Bit28 VCO_SEL_MODE DITH_SEL CAL_CLK_SEL VCO_VB_CTRL Bit29 CAL_ACC DEL_SD_CLK Bit30 TX_DIV_BIAS RSV RSV Bit31 42 RSV EN_CAL EN_FRAC_MODE EN_LD_ISOURCE GAIN_CTRL Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 9.5.1 Serial interface Register Definition Table 5. Register 1 Register 1 Bit Name Reset Value Bit0 ADDR<0> 1 Bit1 ADDR<1> 0 Bit2 ADDR<2> 0 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 RDIV<0> 1 Bit6 RDIV<1> 0 Bit7 RDIV<2> 0 Bit8 RDIV<3> 0 Bit9 RDIV<4> 0 Bit10 RDIV<5> 0 Bit11 RDIV<6> 0 Bit12 RDIV<7> 0 Bit13 RDIV<8> 0 Bit14 RDIV<9> 0 Bit15 RDIV<10> 0 Bit16 RDIV<11> 0 Bit17 RDIV<12> 0 Bit18 RSV 0 Reserved Bit19 REF_INV 0 Invert Reference Clock Polarity; 1 = use falling edge Bit20 NEG_VCO 1 VCO polarity control; 1 = negative slope (negative Kv) Bit21 ICP<0> 0 Bit22 ICP<1> 1 Bit23 ICP<2> 0 Bit24 ICP<3> 1 Bit25 ICP<4> 0 Bit26 ICPDOUBLE 0 Bit27 CAL_CLK_SEL<0> 0 Bit28 CAL_CLK_SEL<1> 0 Bit29 CAL_CLK_SEL<2> 0 Bit30 CAL_CLK_SEL<3> 1 Bit31 RSV 0 Copyright © 2014, Texas Instruments Incorporated Description Register Address Bits 13-bit Reference Divider Value (Rmin = 1, Rmax = 8191) Program charge pump DC current: [00000] = 1.94 mA [11111] = 0.47 mA [01010] = 0.97 mA 1 = Set ICP to double the current Multiplication or division factor to create VCO calibration clock from the PFD frequency: [0000] = Fastest ( Rdiv / 128) [1111] = Slowest (Rdiv x 128), [1000] = Default (1x Rdiv) Reserved 43 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn CAL_CLK_SEL[3..0]: Set the frequency divider value used to derive the VCO calibration clock from the reference frequency. Table 6. CAL_CLK_SEL Scaling Factor Setting CAL_CLK_SEL Scaling Factor CAL_CLK_SEL Scaling Factor 1111 1/128 0111 NA 1110 1/64 0110 2 1101 1/32 0101 4 1100 1/16 0100 8 1011 1/8 0011 16 1010 1/4 0010 32 1001 1/2 0001 64 1000 1 0000 128 ICP[4..0]: Set the charge pump current. Table 7. Charge Pump Current Set-Point 44 ICP[4..0] Current (mA) ICP[4..0] Current (mA) 00 000 1.94 10 000 0.75 00 001 1.76 10 001 0.72 00 010 1.62 10 010 0.69 00 011 1.49 10 011 0.67 00 100 1.38 10 100 0.65 00 101 1.29 10 101 0.63 00 110 1.21 10 110 0.61 00 111 1.14 10 111 0.59 01 000 1.08 11 000 0.57 01 001 1.02 11 001 0.55 01 010 0.97 11 010 0.54 01 011 0.92 11 011 0.52 01 100 0.88 11 100 0.51 01 101 0.84 11 101 0.50 01 110 0.81 11 110 0.48 01 111 0.78 11 111 0.47 Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 Table 8. Register 2 Register 2 Bit Name Reset Value Bit0 ADDR<0> 0 Bit1 ADDR<1> 1 Bit2 ADDR<2> 0 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 NINT<0> 0 Bit6 NINT<1> 0 Bit7 NINT<2> 0 Bit8 NINT<3> 0 Bit9 NINT<4> 0 Bit10 NINT<5> 0 Bit11 NINT<6> 0 Bit12 NINT<7> 1 Bit13 NINT<8> 0 Bit14 NINT<9> 0 Bit15 NINT<10> 0 Bit16 NINT<11> 0 Bit17 NINT<12> 0 Bit18 NINT<13> 0 Bit19 NINT<14> 0 Bit20 NINT<15> 0 Bit21 PLL_DIV_SEL<0> 1 Bit22 PLL_DIV_SEL<1> 0 Select division ratio of divider in front of prescaler [00] = 1X, [01] = div2, [10] = div4 Bit23 PRSC_SEL 1 Select precaler modulus: [0] = 4/5, [1] =8/9 Bit24 RSV 0 Bit25 RSV 0 Bit26 VCO_SEL<0> 0 Bit27 VCO_SEL<1> 1 Selects between the four integrated VCOs [00] = lowest frequency, [11] = highest frequency Bit28 VCO_SEL_MODE 0 Single VCO auto-calibration mode: [1] = active Bit29 CAL_ACC<0> 0 Bit30 CAL_ACC<1> 0 Error count during the cap array calibration [00] = 0, [01] = 1/32, [10] = 1/64, [11] =1/128) Bit31 EN_CAL 0 Initiate VCO auto-calibration, resets automatically Copyright © 2014, Texas Instruments Incorporated Description Register Address Bits PLL N-Divider Value Reserved 45 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Table 9. Register 3 46 Register 3 Bit Name Reset Value Bit0 ADDR<0> 1 Bit1 ADDR<1> 1 Bit2 ADDR<2> 0 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 NFRAC<0> 0 Bit6 NFRAC<1> 0 Bit7 NFRAC<2> 0 Bit8 NFRAC<3> 0 Bit9 NFRAC<4> 0 Bit10 NFRAC<5> 0 Bit11 NFRAC<6> 0 Bit12 NFRAC<7> 0 Bit13 NFRAC<8> 0 Bit14 NFRAC<9> 0 Bit15 NFRAC<10> 0 Bit16 NFRAC<11> 0 Bit17 NFRAC<12> 0 Bit18 NFRAC<13> 0 Bit19 NFRAC<14> 0 Bit20 NFRAC<15> 0 Bit21 NFRAC<16> 0 Bit22 NFRAC<17> 0 Bit23 NFRAC<18> 0 Bit24 NFRAC<19> 0 Bit25 NFRAC<20> 0 Bit26 NFRAC<21> 0 Bit27 NFRAC<22> 0 Bit28 NFRAC<23> 0 Bit29 NFRAC<24> 0 Bit30 RSV 0 Bit31 RSV 0 Description Register Address Bits Fractional PLL N-Divider 0 to 0.99999 in fractional mode Reserved Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 Table 10. Register 4 Register 4 Bit Name Reset Value Bit0 ADDR<0> 0 Bit1 ADDR<1> 0 Bit2 ADDR<2> 1 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 PWD_PLL 0 Power -down all PLL blocks: (1 = off) Bit6 PWD_CP 0 Power-down Charge Pump: (1=off) Bit7 PWD_VCO 0 Power-down VCO: (1=off) Bit8 PWD_VCO_MUX 0 Power-down VCO Mux blocks: (1=off) Bit9 PWD _DIV124 0 Power-down the div 1,2,4 in the PLL f/b path: (1=off) Bit10 PWD_PRESC 0 Power-down Prescaler: (1=off) Bit11 RSV 1 Reserved Bit12 PWD_OUTBUF 1 Power-down Ouptut Buffer: (1=off) Bit13 PWD_LO_DIV 1 Power-down LO divider block: (1=off) Bit14 PWD_TX_DIV 1 Power-down TX divider block: (1=off) Bit15 PWD_MOD 1 Power-down modulator block: (1=off) Bit16 EN_EXTVCO 0 Enable external VCO input buffer: (1 = enabled) Bit17 RSV 0 Reserved Bit18 EN_ISOURCE 0 Enable offset current at CP output (frac-n mode only). Bit19 LD_ANA_PREC<0> 0 Bit20 LD_ANA_PREC<1> 0 Control precision of Analog Lock Detector: [00] = H/H (High), [01] = L/L (Low), [10] = H/L , [11] = L/L Bit21 CP_TRISTATE<0> 0 Bit22 CP_TRISTATE<1> 0 Set the charge pump output in Tristate mode: [00] = Off, [01] = Down, [10] = Up, [11] = Tristate Bit23 SPEEDUP 0 Enable fast turn on/off time of bias blocks. Bit24 LD_DIG_PREC 0 Lock detector precision (increases sampling time if set to 1) Bit25 MOD_ORD<0> 1 Bit26 MOD_ORD<1> 0 Bit27 MOD_ORD<2> 1 Bit28 DITH_SEL 0 Dither Mode: [0] = pseudo-random, [1] = constant Bit29 DEL_SD_CLK<0> 0 Bit30 DEL_SD_CLK<1> 1 DS modulator clock delay. Frac-n mode only. [00] = Min delay, [11] = max delay Bit31 EN_FRAC_MODE 0 Enable Frac-n mode when set to 1 Copyright © 2014, Texas Instruments Incorporated Description Register Address Bits Modulator order (1-4). Not used in integer mode (defaul 3rd order + dither) 47 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Table 11. Register 5 48 Register 5 Bit Name Reset Value Bit0 ADDR<0> 1 Description Bit1 ADDR<1> 0 Bit2 ADDR<2> 1 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 RSV 0 Bit6 IB_MOD_GM<0> 0 Bit7 IB_MOD_GM<1> 1 Bit8 IB_MOD_LO<0> 0 Bit9 IB_MOD_LO<1> 1 Bit10 VCO_BIAS<0> 0 Bit11 VCO_BIAS<1> 0 Bit12 VCO_BIAS<2> 0 Bit13 VCO_BIAS<3> 1 Bit14 VCOBUF_BIAS<0> 0 Bit15 VCOBUF_BIAS<1> 1 Bit16 VCOMUX_BIAS<0> 0 Bit17 VCOMUX_BIAS<1> 1 Bit18 OUTBUF_BIAS<0> 0 Bit19 OUTBUF_BIAS<1> 1 Bit20 RSV 0 Bit21 RSV 1 Bit22 VCO_CAL_IB 0 Bit23 VCO_CAL_REF<0> 0 Bit24 VCO_CAL_REF<1> 0 Bit25 VCO_CAL_REF<2> 1 Bit26 VCO_AMPL_CTRL<0> 0 Bit27 VCO_AMPL_CTRL<1> 1 Bit28 VCO_VB_CTRL<0> 0 Bit29 VCO_VB_CTRL<1> 1 Adjusts the VCO core bias voltage: [00] = 1.2 V, [01] = 1.35 V, [10] = 1.5 V, [11] = 1.65 V Bit30 RSV 0 Reserved Bit31 EN_LD_MON_ISOURCE 1 Enable monitoring of LD to turn on Isource; recommend [0] = Isource ctrl Register Address Bits Reserved Adjust modulator bias current gm Adjust modulator BB and LO bias current Adjust VCO bias reference current Adjust VCO buffer reference current Adjust VCO Mux reference current Adjust output buffer current Reserved Bias current for CAL reference voltage: [0] = PTAT, [1] = Constant VCO calibration reference voltage adjustment [000] = 0.9 V, [111] = 1.4 V [011] = recommended = 1.11 V Adjusts the signal level at the VCO_MUX input: [00] =max, [11] = min Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 Table 12. Register 6 Register 6 Bit Name Reset Value Bit0 ADDR<0> 0 Bit1 ADDR<1> 1 Bit2 ADDR<2> 1 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 RSV 0 Bit6 RSV 0 Bit7 VCO_TRIM<0> 0 Bit8 VCO_TRIM<1> 0 Bit9 VCO_TRIM<2> 0 Bit10 VCO_TRIM<3> 0 Bit11 VCO_TRIM<4> 0 Bit12 VCO_TRIM<5> 1 Bit13 EN_LOCKDET 0 Enable monitor of lock detector output for autocal mode Bit14 VCO_TEST_MODE 0 Counter mode, measure max and min freq for each VCO Bit15 CAL_BYPASS 0 Bypass auto-cal; sets VCO_SEL and VCO_TRIM from Serial interface Bit16 MUX_CTRL<0> 1 Bit17 MUX_CTRL<1> 0 Bit18 MUX_CTRL<2> 0 Bit19 ISOURCE_SINKB 0 Bit20 ISOURCE_TRIM<0> 0 Bit21 ISOURCE_TRIM<1> 0 Bit22 ISOURCE_TRIM<2> 1 Bit23 LO_DIV_SEL<0> 0 Bit24 LO_DIV_SEL<1> 0 Bit25 LO_DIV_BIAS<0> 0 Bit26 LO_DIV_BIAS<1> 1 Adjust LO divider bias current: [00] = 25 uA, [01] = 37.5 uA, [10] = 50 uA, [11] = 62.5 uA Bit27 TX_DIV_SEL<0> 0 Adjust TX path divider. Bit28 TX_DIV_SEL<1> 1 [00] = Div/1, [01] = Div/2, [10] = Div/4. [11] = Div/8 Bit29 TX_DIV_BIAS<0> 0 Bit30 TX_DIV_BIAS<1> 1 Adjust TX divider bias current: [00] = 25 uA, [01] = 37.5 uA, [10] = 50 uA, [11] = 62.5 uA Bit31 GAIN_CTRL 0 Modulator gain control: [0] = Default, [1] = High Gain Copyright © 2014, Texas Instruments Incorporated Description Register Address Bits Reserved VCO capacitor array control bits; used in manual cal mode Select signal for test output: [001] = LD, [010] = NDIV, [100] = RDIV, [110] = A_counter Offset current polarity Adjust Isource bias current in frac-n mode. Adjust LO path divider: [00] = Div/1, [01] = Div/2, [10] = Div/4. [11] = Div/8 49 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Table 13. READBACK Mode Summary Serial interface Map Bit Register 0 RDBK Register Address Register Address Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 CHIP_ID Bit6 Bit7 Bit8 Bit9 NU Bit10 Bit11 Bit12 R_SAT_ERR Bit13 Bit14 Bit15 N/C Bit16 VCO_TRIM Bit17 Bit18 Bit19 Bit20 Bit21 Bit22 COUNT VCO_SEL Bit23 Bit24 Bit25 Bit26 Bit27 MUX_COUNT Bit28 Bit29 RB_REG Bit30 Bit31 50 MUX_COUNT RB_ENABLE Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 Table 14. Register 0 (Readback Only) Register 0 Bit Name Reset Value Bit0 ADDR<0> 0 Bit1 ADDR<1> 0 Bit2 ADDR<2> 0 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 CHIP_ID<0> 1 Bit6 CHIP_ID<1> 0 Bit7 NU x Bit8 NU x Bit9 NU x Bit10 NU x Bit11 NU x Bit12 R_SAT_ERR x Bit13 COUNT<0>/NU x Bit14 COUNT<1>/NU x Bit15 COUNT<2>/VCO_TRIM<0> x Bit16 COUNT<3>/VCO_TRIM<1> x Bit17 COUNT<4>/VCO_TRIM<2> x Bit18 COUNT<5>/VCO_TRIM<3> x Bit19 COUNT<6>/VCO_TRIM<4> x Bit20 COUNT<7>/VCO_TRIM<5> x Bit21 COUNT<8>/VCO_SEL<0> x Bit22 COUNT<9>/VCO_SEL<1> x Bit23 COUNT<10>/VCO_SEL<2> x Bit24 COUNT<11> x Bit25 COUNT<12> x Bit26 COUNT<13> x Bit27 COUNT<14> x Bit28 COUNT<15> x Bit29 COUNT<16> x Bit30 COUNT<17> x Bit31 MUX_COUNT x Copyright © 2014, Texas Instruments Incorporated Description Register Address Bits Chip ID Not Used R-div saturation error for cal VCO frequency counter high when MUX_COUNT = 0 and VCO_TEST_MODE = 1 VCO frequency counter low when MUX_COUNT = 1 and VCO_TEST_MODE = 1 Autocal results for VCO_TRIM and VCO_SEL when VCO_TEST_MODE = 0 [0] = max freq count, [1] = min freq count 51 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Table 15. Register RDBK (Write Register for Readback) 52 RDBK Bit Name Reset Value Bit0 ADDR<0> 0 Bit1 ADDR<1> 0 Bit2 ADDR<2> 0 Bit3 ADDR<3> 1 Bit4 ADDR<4> 0 Bit5 N/C 0 Bit6 N/C 0 Bit7 N/C 0 Bit8 N/C 0 Bit9 N/C 0 Bit10 N/C 0 Bit11 N/C 0 Bit12 N/C 0 Bit13 N/C 0 Bit14 N/C 0 Bit15 N/C 0 Bit16 N/C 0 Bit17 N/C 0 Bit18 N/C 0 Bit19 N/C 0 Bit20 N/C 0 Bit21 N/C 0 Bit22 N/C 0 Bit23 N/C 0 Bit24 N/C 0 Bit25 N/C 0 Bit26 N/C 0 Bit27 MUX_COUNT 0 Bit28 RB_REG<0> x Bit29 RB_REG<1> x Bit30 RB_REG<2> x Bit31 RB_ENABLE 1 Description Register Address Bits [0] = max freq count, [1] = min freq count Three LSBs of the address for the register that is being read: [001] = Register 1 [110] = Register 6 Puts device in Readback mode Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 9.5.1.1 BIAS SETTINGS Optimum TRF7322 bias settings used in the performance measurements are shown in Table 16. Table 16. Register Settings With Optimized Bias Set Used in the Performance Measurement. REGISTER BITS TYPICAL OPERATING MODE [256MHz-2GHz], INT MODE TYPICAL OPERATING MODE [2GHz - 3GHz], INT MODE TYPICAL OPERATING MODE [3GHz 4.1GHz], INT MODE LOW POWER MODE, INT MODE FRACTIONAL MODE REGISTER 1 RDIV x x x x x REGISTER 1 REF_INV 0 0 0 0 0 REGISTER 1 NEG_VCO 1 1 1 1 1 REGISTER 1 ICP 0 0 0 0 0 REGISTER 1 ICPDOUBLE 0 0 0 0 0 REGISTER 1 CAL_CLK_SEL 13 13 13 13 15 REGISTER 2 NINT x x x x x REGISTER 2 PLL_DIV_SEL x x x x x REGISTER 2 PRSC_SEL x x x x x REGISTER 2 VCO_SEL x x x x x REGISTER 2 VCO_SEL_MODE x x x x x REGISTER 2 CAL_ACC 0 0 0 0 0 REGISTER 2 EN_CAL 1 1 1 1 1 REGISTER 3 NFRAC 0 0 0 0 x REGISTER 4 PWD_PLL 0 0 0 0 0 REGISTER 4 PWD_CP 0 0 0 0 0 REGISTER 4 PWD_VCO 0 0 0 0 0 REGISTER 4 PWD_VCO_MUX 0 0 0 0 0 REGISTER 4 PWD _DIV124 0 0 0 0 0 REGISTER 4 PWD_PRESC 0 0 0 0 0 REGISTER 4 PWD_OUTBUF 0 0 0 1 0 REGISTER 4 PWD_LO_DIV 0 0 0 1 0 REGISTER 4 PWD_TX_DIV 0 0 0 0 0 REGISTER 4 PWD_MOD 0 0 0 0 0 REGISTER 4 EN_EXTVCO 0 0 0 0 0 REGISTER 4 EN_ISOURCE 0 0 0 0 1 REGISTER 4 LD_ANA_PREC 0 0 0 0 3 REGISTER 4 CP_TRISTATE 0 0 0 0 0 REGISTER 4 SPEEDUP 0 0 0 0 0 REGISTER 4 LD_DIG_PREC 0 0 0 0 0 REGISTER 4 MOD_ORD 5 5 5 5 4 REGISTER 4 DITH_SEL 0 0 0 0 0 REGISTER 4 DEL_SD_CLK 2 2 2 2 0 REGISTER 4 EN_FRAC_MODE 0 0 0 0 1 REGISTER 5 IB_MOD_GM 3 3 2 0 3 REGISTER 5 IB_MOD_LO 0 1 0 0 0 REGISTER 5 VCO_BIAS 15 15 15 15 15 REGISTER 5 VCOBUF_BIAS 2 2 2 2 2 REGISTER 5 OUTBUF_BIAS 2 2 2 0 2 REGISTER 5 VCOMUX_BIAS 2 2 2 2 2 REGISTER 5 VCO_CAL_IB 0 0 0 0 0 REGISTER 5 VCO_CAL_REF 3 3 3 3 3 REGISTER 5 VCO_AMPL_CTRL 0 0 0 0 0 REGISTER 5 VCO_VB_CTRL 3 3 3 3 3 REGISTER 5 EN_LD_ISOURCE 0 0 0 0 0 Copyright © 2014, Texas Instruments Incorporated 53 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn Table 16. Register Settings With Optimized Bias Set Used in the Performance Measurement. (continued) REGISTER 54 BITS TYPICAL OPERATING MODE [256MHz-2GHz], INT MODE TYPICAL OPERATING MODE [2GHz - 3GHz], INT MODE TYPICAL OPERATING MODE [3GHz 4.1GHz], INT MODE LOW POWER MODE, INT MODE FRACTIONAL MODE REGISTER 6 VCO_TRIM x x x x x REGISTER 6 EN_LOCKDET 0 0 0 0 0 REGISTER 6 VCO_TEST_MODE 0 0 0 0 0 REGISTER 6 CAL_BYPASS 0 0 0 0 0 REGISTER 6 MUX_CTRL 1 1 1 1 5 REGISTER 6 ISOURCE_SINKB 0 0 0 0 0 REGISTER 6 ISOURCE_TRIM 4 4 4 4 7 REGISTER 6 LO_DIV_SEL x x x x x REGISTER 6 LO_DIV_BIAS 2 2 2 0 2 REGISTER 6 TX_DIV_SEL x x x x x REGISTER 6 TX_DIV_BIAS 1 1 1 0 1 REGISTER 6 GAIN_CTRL 0 0 0 0 0 Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 10 Applications and Implementation 10.1 Application Information Figure 135 illustrates a typical application schematic for the TRF3722. EXT VCO BBI N IN C11 R15 4.7pF 5V or 3.3V Supply VCC_TNK VCC_PLL FB19 BBI P IN VCC_VCO R16 49.9 49.9 FB11 1K 1K VCC_DIG FB20 C40 1.0uF C31 4.7pF C47 0.1nF C41 1.0uF C32 4.7pF C48 0.1nF 1K VCC_MOD4 VCC_LO1 FB18 VCC_LO2 1 VTUNE R41 200 1K C62 1.0uF LO OUTN C39 1.0uF C12 1K C29 4.7pF C46 0.1nF 47pF VCC_MOD2 R22 49.9 1K VCC_MOD3 VCC_PLL CP OUT FB23 VCC_LO_OUT C27 10uF 1K C42 1.0uF C55 4.7pF C56 0.1nF 1K LE DATA CLOCK READ BACK R26 49.9 VCC_MOD4 FB24 C7 1K 47pF LO OUTP VCC_VCO FB10 REFERENCE GND LO_OUTN LO_OUTP GND CP_OUT VCC_PLL GND REFIN GND LE DATA CLK PWRPAD U1 TRF3722 NC4 VCC_MOD4 GND VCC_MOD3 GND GND RFOUT GND VCC_MOD2 GND VCC_MOD1 NC3 24 23 22 21 20 19 18 17 16 15 14 13 C64 0.1nF C63 4.7pF C52 1.0uF RF OUT C18 4.7pF VCC_MOD2 C54 0.1nF C53 4.7pF C38 1.0uF 1 2 3 4 5 6 7 8 9 10 11 12 VCC_MOD1 FB17 C44 1.0uF 37 38 39 40 41 42 43 44 45 46 47 48 49 VCC_MOD3 PD RDBK LD VCC_DIG GND VCC_LO1 GND BBQ_N NC1 BBQ_P GND NC2 FB22 NC7 VCC_LO2 VTUNE VCC_VCO VCC_TK EXT_VCO GND BBI_N NC6 BBI_P GND NC5 36 35 34 33 32 31 30 29 28 27 26 25 VCC_LO2 FB21 3.3V Supply 2 PD VCC_MOD1 1K VCC_LO_OUT FB16 LD C60 1.0uF VCC_DIG 1K VCC_LO1 C25 10uF C43 1.0uF C37 1.0uF C28 4.7pF C45 0.1nF R13 49.9 BBQ N IN R12 49.9 BBQ P IN Figure 135. TRF3722 Application Schematic 10.1.1 Design Requirements Table 17 lists the pin termination requirements and interfacing for the circuit. Table 17. Termination Requirements and Interfacing PIN NAME 47 DATA 4WI data input: digital input, high impedance DESCRIPTION 2 RDBK Readback output; digital output pins can source or sink up to 8 mA of current 3 LD 8,10,27,29 BBI_P, BBI_N, BBQ_P, BBQ_N Lock detector digital output, as configured by MUX_CTRL In-phase and quadrature baseband differential baseband signals. Typical 0.25V common mode is needed Modulator RF output: must be ac-coupled and can drive 50 Ω load 18 RFOUT 31 EXT_VCO External local oscillator input: high impedance, normally ac-coupled. If unused terminate to 50 ohms load 38,39 LO_OUTP, LO_OUTN Local oscillator output: open-collector output. A pull-up resistor is LO_OUT required, normally ac-coupled. 44 REFIN 46 LE 48 CLK Serial interface clock input: digital input, high impedance 47 DATA Serial interface data input: digital input, high impedance Copyright © 2014, Texas Instruments Incorporated Reference clock input: high impedance, normally ac-coupled Serial interface latch enable: digital input, high impedance 55 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 10.1.2 Detailed Design Procedures, DAC to Modulator Interface Network Digital-to-analog converter (DAC) can interface directly with the TRF3722 modulator. The common-mode voltage of the DAC and the modulator baseband inputs should be properly maintained. With the proper interface network, the common-mode voltage of the DAC can be translated to the proper common-mode voltage of the modulator. The TRF3722 common-mode voltage is typically 0.25 V, and is ideally suited to interface with the DAC3482/3484 (DAC348x) and DAC38J8x family. The interface network is shown in Figure 136. 50 W 50 W DAC348x / DAC38J8X 50 W 50 W 50 W 50 W 50 W ~ 0/90 50 W S TRF3722 Figure 136. DAC348x Interface with the TRF3722 Modulator The DAC348x requires a load resistance of 25 Ω per branch to maintain its optimum voltage swing of 1-VPP differential with a 20-mA max current setting. The load of the DAC is separated into two parallel 50-Ω resistors placed on the input and output side of the low-pass filter. This configuration provides the proper resistive load to the DAC while also providing a convenient 50-Ω source and load termination for the filter. 56 Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 10.1.3 Application Curves, DAC34H84 with TRF3722 Modulator Performance The cascaded combination of the DAC34H84 and TRF3722 modulator yields excellent system parameters suitable for high-performance applications. Figure 137 and Figure 138 shows 152.9 MHz IF adjacent channel power ratio (ACPR) performance. • Mode integer • PFD: 3.2 MHz • Reference: 153.6 MHz • LO = 1689.6 MHz • IF = 152.9 MHz • RF= 1842.5 MHz Figure 137. 152.9 MHz IF, DAC34H84 + TRF3722 20 MHz LTE ACPR Figure 138. 152.9 MHz IF, 6 Carrier MC-GSM DAC34H84 + TRF3722 ACPR Performance 11 Power Supply Recommendations The TRF3722 is powered by supplying a nominal 3.3 V and 5 V. It can also be powered using only 3.3V supply. Proper RF bypassing should be placed close to each power supply pin. Ground pin connections should have at least one ground via close to each ground pin to minimize ground inductance. The PowerPAD™ must be tied to ground, preferably with the recommended ground via pattern to provide a good thermal conduction path to the alternate side of the board and to provide a good RF ground for the device. (Refer to Layout Guidelines section for additional information.) Copyright © 2014, Texas Instruments Incorporated 57 TRF3722 ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 www.ti.com.cn 12 Layout 12.1 Layout Guidelines Layout of the application board significantly impacts the analog performance of the TRF3722 device. Noise and high-speed signals should be prevented from leaking onto power-supply terminals or analog signals. The TRF3722 device is fitted with a ground slug on the back of the package that must be soldered to the printed circuit board (PCB) ground with adequate ground vias to ensure a good thermal and electrical connection. The ground pins of the device can be directly tied to the ground slug pad for a low-inductance path to ground. Additional ground vias may be added if space allows. Follow these recommendations: • Place supply decoupling capacitors physically close to the device, on the same side of the board. Isolate supply terminals with a ferrite bead. • Maintain a continuous ground plane in the vicinity of the device and as return paths for all high-speed signal lines. Place reference plane vias or decoupling capacitors near any signal line reference transition. • Power planes should not overlap each other or high-speed signal lines. • Isolate REFIN routing from loop filter lines, control lines, and other high-speed lines. 12.2 Layout Example RF &DC Bypass VCC Capacitors Baseband Terminations VCC 25 NC 26 GND 27 BBI_P 28 NC 29 BBI_N 30 GND 31 EXT_VCO 32 VCC_TK 33 VCC_VCO 34 VTUNE 35 VCC_LO2 36 NC PLL Loop Filter 24 NC GND 37 LO Out LO_OUTN 38 23 LO_OUTP 39 22 GND VCC_MOD4 VCC 21 VCC_MOD3 GND 40 VCC CP_OUT 41 20 GND VCC_PLL 42 19 GND 17 GND REFIN 44 DC Blocking Capacitor RF Out RF Out Capacitor VCC 16 VCC_MOD2 GND 45 15 GND LE 46 14 VCC_MOD1 DATA 47 RF &DC Bypass Capacitors 25 NC 13 NC 12 GND 11 BBQ_P 10 9 6 VCC_LO1 NC 5 GND 8 4 VCC_DIG BBQ_N 3 LD 7 2 GND 1 PD RDBK CLK 48 Notes: 1.Ensure all components are connected to a common RF/DC ground plane with plenty of vias 2. Ensure a low impedance VCC plane is connected to all VCC terminals Note: Ensure good RF microstrip or stripline traces are used to connect the external components to the REFIN, RF and LO output pins 18 RFOUT GND 43 REFIN RF &DC Bypass Capacitors VCC RF &DC Bypass Capacitors Baseband Terminations Figure 139. Layout 58 Copyright © 2014, Texas Instruments Incorporated TRF3722 www.ti.com.cn ZHCSCN0A – MAY 2014 – REVISED JUNE 2014 13 器件和文档支持 13.1 Trademarks PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. 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LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. 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