Adv. Radio Sci., 7, 145–150, 2009
www.adv-radio-sci.net/7/145/2009/
© Author(s) 2009. This work is distributed under
the Creative Commons Attribution 3.0 License.
Advances in
Radio Science
CMOS low noise amplifiers for 1.575 GHz GPS applications
M. Isikhan and A. Richter
IMMS gGmbH, Erfurt, Germany
Abstract. This paper presents Low Noise Amplifier (LNA)
versions designed for 1.575 GHz L1 Band Global Positioning System (GPS) applications. A 0.35 µm standard CMOS
process is used for implementation of these design versions.
Different versions are designed to compare the results, analyze some effects and optimize some critical performance
criteria. On-chip inductors with different quality factors and
a slight topology change are utilized to achieve this variety. It
is proven through both on-wafer and on-PCB measurements
that the LNA versions operate at a supply voltage range varying from 2.1 V to 3.6 V drawing a current of 10 mA and
achieve a gain of 13 dB to 17 dB with a Noise Figure (NF) of
1.5 dB. Input referred 1 dB compression point (ICP) is measured as −5.5 dBm and −10 dBm for different versions.
1
Introduction
The demand on current GPS applications forces the design of
high performance, low cost L1 frequency band (1.575 GHz
center frequency) receivers. Galileo/GPS combined system
is under development and this will allow the realization of
much higher precision applications (Alvarado et al., 2007).
On the other hand, the Assisted GPS (A-GPS) concept necessitates the integration of GPS receiver into the mobile
phone requiring improvement in receiver sensitivity, linearity
and power consumption (Bokinge et al., 2006; van Diggelen,
2002). The demand is more intensive on highly integrated,
compact solutions. Therefore, the GPS receiver building
blocks should be convenient for SoC or possibly SiP implementation with a small amount of off-chip circuit components as possible. The target is to design an LNA with an
optimum layout to be integrated in a receiver chip. The input
and output of LNA is optimized for 50  terminations making it suitable for integration into heterodyne receiver structures with external Image Reject Filter. A block diagram of
a possible application is depicted in Fig. 1.
Correspondence to: M. Isikhan
(murat.isikhan@imms.de)
LNA is a critical building block on the received signal
path. Important parameters of the performance of a receiver
such as Noise Figure (NF), input impedance matching, reverse isolation, stability and linearity performance are mainly
determined by the LNA (Razavi, 1998). The circuit topology
and component selections to improve LNA performance in
one criterion do not usually work in favor of all other performance criteria. Thus, a compromise is to be done during
the decision for circuit topology and components. One of the
performance criteria may take the priority depending on the
application needs. Different versions are designed for this
purpose through utilizing different Q on-chip inductors and
a slight topology change. A highly integrated solution implemented in a standard CMOS technology with lower mask
costs is a critical design target.
Different versions of LNA are designed and fabricated
with a 0.35 µm standard CMOS technology and measurements are performed on-wafer and on-PCB. The design procedure and experimental results with comparisons are presented in this paper.
2
LNA circuit design
As mentioned in the introduction part, the NF of LNA has
the most critical effect on the overall NF of the system. In
order to have an overall NF of less than 2 dB for high precision GPS applications, the LNA NF should be kept well
below 1.5 dB. 1.2 dB NF for the impedance-matched LNA
in package could relax the noise requirements of cascaded
components. A summary of the requirements are given in
Table 1.
Different topologies are considered to achieve the performance targets. The LNA should provide sufficient gain at
a bandwidth of 20.46 MHz for GPS L1 band applications.
An amplifier topology with an inductive-capacitive load can
achieve this requirement. Furthermore such a load selection
keeps the NF at a low level. An ideal LNA should provide
isolation of the signals at the input and output very well. The
parasitic signals at the output of the LNA should not couple to the LNA input, possibly resulting in parasitic signal
Published by Copernicus Publications on behalf of the URSI Landesausschuss in der Bundesrepublik Deutschland e.V.
topology
withimplemented
cascode n-MOS
grated
solution
in a transisstandard C
(A-GPS) concept necessitates the integration of an
GPSamplifier
th
tors, inductive
capacitive
andmask
a source
receiver into the mobile phone requiring improvement
technology
withload
lower
costsdegenerais a critical og
d
tion inductor
is selected for core circuit of LNA. This
target.
in receiver sensitivity, linearity and power consumpin
146
M. Isikhan and A. Richter:
CMOS
low noise amplifiers
for 2.
1.575 GHz GPS applications
circuit
is
depicted
Figure
Differentinversions
of LNA are designed and fabri
tion [2] [3]. The demand is more intensive on highly
po
with
a
0.35
µm
standard
CMOS
technology
and
integrated,
compact
solutions.
Therefore,
the
GPS
anm
Table 1. Target requirements.
urements are performed on-wafer and on-PCB.ac
receiver building blocks should be convenient for SoC
voltage
2.1 V
. . . 3.6aVsmall amount
design procedure and experimental results withpe
or possibly Supply
SiP implementation
with
Supply current
10 mA
parisons are presented in this paper.
of off-chip circuit
components1.575
as possible.
The target
co
Center frequency
GHz
is to design Input/output
an LNA impedance
with an optimum
layout
to
be
inre
50 
S11,
S22
<−10
dB
C
tegrated in a receiver chip. The input and output of
S21
>15 dB
co
LNA is optimized
for 50 Ω <−25
terminations
making it
2
LNA Circuit Design
S12
dB
NF
<1.5
dB
pa
suitable for integration into heterodyne receiver strucICP
−10 dBm
pi
tures with external Image Reject Filter. A block diaAs mentioned in the introduction part, the NF of
gram of a possible application is depicted in Figure 1.
has the most critical effect on the overall NF o
system. In order to have an overall NF of less
2 dB for high precision GPS applications, the
NF should be kept well below 1.5 dB. 1.2 dB N
the impedance-matched LNA in package could
the noise requirements of cascaded component
summary of the requirements are given in Table 1
Table 1: Target Requirements
F
Supply Voltage
2.1 V … 3.6 V
T
Supply
10 mA
Fig. 2. Simplified
coreCurrent
circuit of LNA.
Figure
2:
Simplified
core
circuit
of
LNA
Fig. 1. Integration
of LNA in aof
GPS
receiver.
Figure
1: Integration
LNA
in a GPS Receiver
Center Frequency
1.575 GHz de
of
Thegminductive
source degeneration
proves good
results
Input/Output
Impedance
50 Ω
is its transconductance.
LNA is a critical building block on the received signal
w
from the antenna. This performance specifi- when inputS11,S22
impedance
is considered.
< -10 dBIt
1
gmatching
path.transmissions
Important
parameters
of
the
performance
of
a
m Ls
of
cation can be optimized through minimizing S12 parameter
Zin = j wLs +
+
(1)
provides
creating
a resistive
the
Cgs part in addition>to15
gs
S21 j wC
dBrereceiver
as Noise
Figure
impedance
of the such
LNA. This
attenuation
in the(NF),
reverse input
signal path,
in
an
seen
gate
of impedance
the inputexactly
n-MOS
transisother words
reverseisolation,
isolation is stability
very criticaland
for the
overall active
It ispart
a hard
task at
to the
fix the
input
50
dB
S12
<to -25
matching,
reverse
linearity
perreceiver performance as well. In addition to this fact, a low
using only a degeneration inductor. Trying to increase the
NF
< 1.5 dB
formance
are mainly determined by the LNA [4]. The
S12 value provides the stable operation of an LNA. As well
transconductance through increasing the width of the trancircuit
topology
andisolation
component
selections
to very
improve
as providing
reverse
and stability
which are
sistor doesICP
not help to improve the resistive part-10
of dBm
incritical, good isolation of input and output stage of the LNA
brings the advantage of treating input and output impedance
matching separately, performing some changes at the input
stage of LNA for better impedance matching does not disturb
the impedance seen at the output drastically. Using a cascode amplifier topology provides adequate reverse isolation
and stability. The inductive degeneration topology provides
the amplifier to achieve real input impedance. This is critical
for input impedance matching with 50 . Regarding these
considerations, an amplifier topology with cascode n-MOS
transistors, inductive capacitive load and a source degeneration inductor is selected for core circuit of LNA. This circuit
is depicted in Fig. 2.
The inductive source degeneration proves good results
when input impedance matching is considered. It provides
creating a resistive part in addition to the reactive part seen
at the gate of the input n-MOS transistor. This fact can be
mathematically expressed with the following Eq. (1) where
Cgs is the gate-source capacitance of input transistor M1 and
Adv. Radio Sci., 7, 145–150, 2009
put impedance. In addition, the possibility of increasing
transconductance through increasing the current is also limited since there is a maximum limit for the current consumption. Increasing the value of Ls helps to increase the resistive part of impedance, however, when small signal analysis
is considered, it is obvious that increasing the source degeneration inductance results in lower gain. Due to technology
and design limitations, the real part is lower than required
50 . There is also a capacitive part of input impedance. To
balance this and achieve a good input matching, an inductor
should be placed on the signal path prior to the gate of input
transistor. The Noise Figure considerations indicate that an
inductor on the signal path should have a high quality factor in order to contribute less to the NF. On-chip inductors
do not have a high enough quality factor for this application
in the circuit with the given technology. Due to these facts,
the inductor used for matching (Lmatch ) is implemented as a
high Q off-chip component. The bond wire inductance, effect of package and PCB parasitic circuit elements should
www.adv-radio-sci.net/7/145/2009/
Cmatch is also utilized. The circuit showing the off-chip
components placed on the input signal path and the
parasitic inductive effects of package and PCB are deM. Isikhan
and A.3.Richter: CMOS low noise amplifiers for 1.575 GHz GPS applications
picted
in Figure
147
LNA at the input transistor side is
4.
sults
. It
e reoise
nsis-
Fig. 3. Input impedance matching and parasitics of package and
circuit
the LNA
at the matching
input transistor
side is
Figure
3: Input
impedance
and parasitics
PCB. for
shown in Figure 4. of package and PCB
The main noise sources of a LNA with such inductive
degeneration topology are the intrinsic thermal noise
of input transistor M1, the gate resistance associated
with it (Rg) and the resistance dependent to the Q of
off-chip inductance for matching and the bond wire
equivalent
circuit of LNA
and conductor on PCB (Rm). The noise equivalent
is a good input matching, the LNA
Fig. 5. Contribution of noise sources in LNA circuit.
a voltage
forcircuit
noise
calculaFig.amplifier
4. Noise equivalent
of LNA.
Figure
4: Noise
equivalent
circuit of LNA
Figure 5: Contribution of noise sources in LNA
e factor
F can be taken into considAs long as there is a good input matching, the LNA sistor. γ is a bias dependent factor
circuit
and gd0 is zero bias drain
e noisecan
[5]
be
treated
as a voltage
amplifier
for noise
calculabeconsiderations
modeled
accurate
and given
taken
intoin
account
for a good
inconductance (Bokinge et al., 2006; Shaeffer and Lee, 1997).
Figure 5: Contribution of noise sources in LNA
put impedance
matching
at the
desired
range.
To
tions
and
its
noise
factor
F factor
can
be frequency
taken
into
considOptimum
values
zero the
bias drain
conductance,
gate
g equation
(2)
for
the
noise
F;
The
load
inductor
Ldforand
source
degeneration
incircuit
compensate
inductive
and to fixgiven
the resistive
inductor should
eration
[5]. theThe
noiseimpedance
considerations
in [5] resistance and the resistance of matching
part exactly to 50 , a matching capacitor Cmatch is also
utiductor
are
implemented
assource
on-chip
to
beThe
for a better
performance.
Gate inductors
width inS achieved
2 for the noise factor
state
the following equation (2)
F; L
load inductor
Ldnoise
and the
degeneration
lized.
The
circuit
showing
the
off-chip
components
placed
n-MOS transistor and the inductance Lmatch are decided
R g on the input signal path and
w0theparasitic inductive
haveof a of
more
solution.as on-chip
For such
an impleductoracompact
L
are implemented
inductors
to
effects
2
(2)
through
setS of simulations to optimize noise parameters.


+ γpackage
⋅ Rs and
⋅RgPCB
⋅
R
have
moreresults
compact
For
implein Fig. 3.  w0  mentation,
gdepicted
m d 0 are
simulation
for
thesolution.
sources ofshould
noisesuch
in the
thea inductor
modeling
beanLNA
completed
(2) The
 inductive

= 1main
+ noise
+ sources
+
γ
⋅
R
⋅
g
⋅
Rs F The
w
s
d
0
of
a
LNA
with
such
dementation,
the
inductor
modeling
should
be
completed
circuit
are
shown
in
the
diagram
above.
The
contribution
of
s T 
Rs Rare
before
necessary
simulations.
The
inductor
values
 wnoise
T  of
generation topology
the intrinsic thermal
input the
input
transistor
thermal
noise
and
noise
due
to
resistances
on
before the necessary simulations. The inductor values
transistor M1, the gate resistance associated with it (Rand
signal
path
befactors
compared.
g ) and their
should
known
andquality
theircanquality
factors
should be
be known
and and
the the
the
resistance
dependent
to
the
Q
of
off-chip
inductance
for
The
noise
model
for
on-chip
components
and
the
estiThis
assumption
is
valid
as
long
as
the
resonance
of
is valid matching
as long
as the resonance of
parasitic
extractions
shouldbebeperformed.
performed. TheThe
load load
extractions
should
and the bond wire and conductor on PCBparasitic
(Rm ).
mated
series resistance
for off-chip
discrete matching inducamplifier
with
the
input
circuit
is
achieved
and
w
is
inductor
resonates
with
two
capacitances
and
maxi0
The noise equivalent
circuit forand
the LNA
the input transistorresonates
are used for thiswith
simulation.
be concluded that and
use input circuit
is achieved
wat0 is
inductor
twoIt can
capacitances
mizes
the
gain
at
a
resonant
frequency.
The
outputmaxitor
side
is
shown
in
Fig.
4.
ing
an
on-chip
inductor
instead
would
have
contributed
much
the resonant frequency. The resonant frequency
mizes
gain
atseen
a NF.
resonant
frequency.
The
outpu
impedance
at this frequency
is ideally only
resisAs The
long
there
is
input
matching,
LNA
can the
more
on the overall
should
be asfixed
ata good
the desired
centerthefrequency,
quency.
resonant
frequency
be treated as a voltage amplifier for noise calculations and its
The and
load 50
inductor
and the
source degeneration
in- The
tive
for Ladfrequency
good
matching
the output.
1.575desired
GHz. The n-MOSfrequency,
transition frequency
is
impedance
seen
atΩthis
isatideally
only
resisat the
noise factor F cancenter
be taken into consideration (Shaeffer and
ductor
LS are implemented
as on-chip
to have factor
a
much inductors
higher quality
capacitors,
C2 & C3 have
wLee,
equal
g m / C gs . given
Rs is intheShaeffer
1997).isThe
noisetoconsiderations
compact
For matching
such an implementation,
the
intiveandreandmore
50
Ω fortosolution.
athegood
atthe
theoverall
output.
T which
he n-MOS
transition
frequency
is source
compared
inductor.
Therefore,
Q of The
Lee (1997) state the following Eq. (2) for the noise factor F ;
ductor modeling should be completed before the necessary
sistance which is 50 Ω, Rm is the resistance duecapacitors,
to off&The
Cinductor
much
higher
quality
the C
load
mainly
determined
bytheir
the Q
of the
inductor.factor
2 is
3 have
simulations.
values
and
quality
factors
al to gchip
/
C
.
R
is
the
source
re
s
inductor,
bond
wire
and
wiring
on
application
2
m
gsRm Rg
Utilization
ofanda the
higher
Q extractions
inductor should
will
a Q of
should
known
parasitic
be
perw0
compared
tobethe
inductor.
Therefore,
thegenerate
overall
F =1+
+ resistance
+ γ · Rs ·associated
gd0 ·
(2)of formed.
board.
Rg Ris the
with
the
gate
sharper
resonance
characteristic
and
as
a
result
a
The
load
inductor
resonates
with
two
capacitances
Rs
wT
50 Ω, R
thes resistance
m isn-MOS
the
loadand
is
mainly
determined
by
the
Q
of
the
inductor
input
transistor. γdue
is a to
biasoffdependent
factor
maximizes
the
gain
at
a
resonant
frequency.
The
outsharper gain (S21) characteristics at the frequency
put
impedance
seen
at with
this frequency
is ideally only
resistive
Thisand
assumption
is valid
as long
as the resonance ofUtilization
ampliond wire
wiring
on
application
range
a high
maximum
value
of S21.
ofof ainterest
higher
Q
inductor
will
generate
a
drain
conductance
[5].resonant
and
d 0 is
and 50  for a good matching at the output. The capacitors,
fier g
with
thezero
inputbias
circuit
is achieved
and w0[2]
is the
On
the other hand
an inductor with acompared
low as
Q at
the opresistance
associated
thedrain
gate
ofbe fixedsharper
characteristic
Cresonance
higher quality factorand
toathe result a
frequency.
The resonant
should
at gate
the
2 and C3 have much
Optimum
values
forwith
zerofrequency
bias
conductance,
eration
bandwidth
will
cause
a
smoother
S21
characdesired
frequency,
1.575 GHz.
The
n-MOS transition
Therefore, the overall Q of the load is mainly densistor. resistance
γ iscenter
a and
bias
thedependent
resistance
offactor
matching
inductor
sharper inductor.
gain
(S21)
characteristics
at ofthe
frequency
teristic,by
providing
a inductor.
higher available
termined
the Q of the
Utilization bandwidth
a higher but
frequency is wT which is equal to gm /Cgs . Rs is the source
should be achieved for a better noise performance.
inductor
willwith
generate
sharper
resonance
characteristic
resistance which is 50 , Rm is the resistance due to off-chip
a decreased
value
of maximum
S21.
The
process
range ofQwith
interest
a ahigh
maximum
value
of S21
ias drain
conductance
[2]transistor
[5].
Gate
width
of wire
n-MOS
and theboard.
inductance
and
as
a
result
a
sharper
gain
(S21)
characteristics
at
the
freinductor,
bond
and wiring
on application
Rg is
variations
should
be
taken
into
account
during
On
the other
hand
an inductor
with a value
lowofQS21.
at the
the opLmatch
are decided
through
a set
ofofsimulations
totranopquency
range
of
interest
with
a
high
maximum
the resistance
associated
with the
gate
input n-MOS
simulations for deciding component values. A gain
for zerotimize
biasnoise
drain
conductance,
gate
parameters. The simulation results
for bandwidth will cause a smoother S21 characeration
characteristic with a high maximum value and a
he resistance
matching
inductor
the
sourcesof
of noise
in the LNA
circuit are shown in
www.adv-radio-sci.net/7/145/2009/
Radio
Sci., 7,
145–150,
2009
bandwidth fitting
theAdv.
requirement
can
bebandwidth
fixed
at the bu
teristic, providing
a higher
available
The contribution of input tranved fortheafollowing
better diagram.
noise performance.
center
frequency
of
1.575
GHz.
However,
the
process
withona decreased value of maximum S21. The process
sistor thermal noise and noise due to resistances
variations may alter the component values and shift
-MOS signal
transistor
and
the
inductance
path can be compared.
148
M. Isikhan and A. Richter: CMOS low noise amplifiers for 1.575 GHz GPS applications
Figure 6: Quality factors of 7 nH inductors Ld
Figure 7: IC photo of one LNA version
Fig. 6. Quality factors of 7 nH inductors Ld .
The set of investigations are performed on three difA third version of LNA for this investigation is also
ferent LNA versions with different load inductors and
designed. The high Q inductor is used as load induca slight topology difference. The comparison of S21
On the other hand an inductor with a low Q at the operation
tor. The source degeneration inductor Ls is not imcurves are shown in Figure 8
bandwidth will cause a smoother S21 characteristic, providplemented
on-chip. bandwidth
The gain
increasedvalue
by
ing
a higher available
butcan
withbe
a decreased
than 3S21.
dB by
the source
degeneraofmore
maximum
Theeliminating
process variations
should
be taken
tion
inductor.
For
this
purpose,
the
source
of input
into account during the simulations for deciding component
transistor
is directly
connected
the maximum
ground ofvalue
the
values.
A gain
characteristic
with atohigh
chip.
The
bond
wire
inductance
acts
as
a
degeneration
and a bandwidth fitting the requirement can be fixed at the
inductor
in thisof
condition.
perfect modeling
of variasuch
center
frequency
1.575 GHz.A However,
the process
tions
may alter
the component
the resonant
inductance
realized
by the values
bond and
wireshift
effects
in the Figure
Fig. 7. IC photo
of one
LNA version.
7: IC
photo
of one LNA version
frequency.
absence
of
a perfect L
package
modeling
may
ity factors
of 7isThenH
inductors
package
difficult.
However,
it
provides
the presd
cause
more
seriouspart
problem.
Designing
a higher bandwidth
ence aof
resistive
of input
impedance.
Different
The
set of investigations are performed on three dif
LNA
with
a
decreased
maximum
gain
provides
more
difficult. However, it provides the presence of resistive part
matching
inductor
and
capacitor
should
be
used
onflexthe
f LNA for
this
investigation
is
also
ibility
against
these
problems.
It
is
decided
to
investigate
ferent
LNA
versions
with different
loadandinductors
and
of input
impedance. Different
matching inductor
capacapplication board compared to the first two versions.
the optimum
Q
of the available
on-chip
inductors to have an
gh Q inductor
is
used
as
load
inducitor
should
be
used
on
the
application
board
compared
to
the
It is difficult to predetermine these values through
a slight
topology difference. The comparison of S21
optimized S21 response. Two different 7 nH inductors
with
first two versions. It is difficult to predetermine these values
simulations
unless there
isisa not
very
realistic
model for
degeneration
different inductor
quality factors L
ares used
for thisimpurpose. Two
difthrough
simulations
unless there
curves
shown
in Figure
8 is a very realistic model for
package
effects.
Thiswith
configuration
can beare
utilized
to are
versions
of LNA
the same topology
designed.
p. Theferent
gain
can
be
increased
by
package effects. This configuration can be utilized to maxmaximize
thevalues
gain despite
having
complicated
The
capacitor
to resonate
withathe
inductor areinput
also
imize the gain despite having a complicated input matching
matching
and possibly
stability
problems.
Small sigy eliminating
the
source
degeneraslightly
different
for
the two
versions
as well to achieve
resand possibly stability problems. Small signal analysis on the
nal analysis
on the frequency
circuit indicates
that removing
Ls
onance
at
the
desired
and
to
obtain
good
output
circuit indicates that removing Ls results in a worse reverse
r this purpose,
the
source
of input
results in(S22
a worse
reverse isolation
stability
matching
characteristic).
The Q ofand
twohence
7 nH inductors
isolation and hence stability problems.
tly connected
thecanground
ofFig.the
used
for thisto
design
be viewed in
6.
problems.
Figure 8: S21 comparison of three design versions
A third version of LNA for this investigation is also de-
ire inductance
acts as a degeneration
signed. The high Q inductor is used as load inductor. The
degeneration
inductor Ls isof
not such
implemented on-chip.
ndition.source
modeling
3A perfect
Results
The gain can be increased by more than 3 dB by eliminatd by the
bond
effects
in For
thethis
ing the
sourcewire
degeneration
inductor.
purpose, the
The LNA
is encapsulated
in a SOIC16
Ceramic
Packsource
of
input
transistor
is
directly
connected
to
the ground
lt. However,
it
provides
the
presage. Measurements
are performed
on-wafer and on
of the chip. The bond wire inductance acts as a degeneration
application
board. Measurements
are performed for
part of input
impedance.
Different
inductor in
this condition. A perfect
modeling of such inthe
three
design
versions
with
different
and de-is
ductance realized by the bond wire effects in load
the package
and capacitor
should
be
used
on
the
generation inductor implementations. The chip microphotograph
of thetwo
designversions.
version with high Q oncompared
to the
Adv.
Sci.,first
7,
145–150,
2009
chipRadio
inductor
and
on–chip
degeneration inductor is
predetermine
shown in these
Figure 7.values through
there is a very realistic model for
The figure shows the comparison of on-wafer meas3 Results
urements on the three versions. Version 2 with a high
Q load inductor has a sharper response compared to
The LNA is encapsulated in a SOIC16 Ceramic Package.
first version as expected. In addition, the third version
Measurements are performed on-wafer and on application
which
no on-chip
degeneration
inductor
has
board. includes
Measurements
are performed
for the three
design
veran
upwards
shifted
response
as
expected.
The
output
sions with different load and degeneration inductor implematching
andThe
noise
measurements
on-wafer
fits
mentations.
chipfigure
microphotograph
of the
design version
to the simulated results well.
www.adv-radio-sci.net/7/145/2009/
The S-parameter and NF measurements on the application PCB for Version 2 and Version 3 are shown in
figures 9, 10, 11 and 12.
d
is also
d inducnot imased by
generaof input
d of the
neration
of such
s in the
he presDifferent
d on the
ersions.
through
odel for
lized to
ed input
mall sigving Ls
stability
c Packand on
med for
and dehip mih Q onuctor is
The set of investigations are performed on three different LNA versions with different load inductors and
a slight topology difference. The comparison of S21
Figure
S11,
of packaged
packaged LNA
LNA ververM. Isikhan and A. Richter: CMOS low noise amplifiers for 1.575 GHz
GPS9:
applications
149
Figure
9:
S11, S12
S12 and
and S22
S22 of
curves are shown in Figure 8
sion
2
sion 2
Figure 8: S21 comparison of three design versions
Fig. 8. S21 comparison of three design versions.
The figure shows the comparison of on-wafer measurements on the three versions. Version 2 with a high
Q load inductor has a sharper response compared to
first version as expected. In addition, the third version
which includes no on-chip degeneration inductor has
an upwards shifted response as expected. The output
matching and noise figure measurements on-wafer fits
to the simulated results well.
Figure 10: S11, S12 and S22 of packaged LNA version 33
sion
Figure
10:S12
S11,
S22 of LNA
packaged
verFig.
10. S11,
andS12
S22and
of packaged
version LNA
3.
The S-parameter and NF measurements on the application PCB for Version 2 and Version 3 are shown in
figures 9, 10, 11 and 12.
Figure 9: S11, S12 and S22 of packaged LNA version 2
Fig. 9. S11, S12 and S22 of packaged LNA version 2.
with high Q on-chip inductor and on-chip degeneration inductor is shown in Fig. 7.
The set of investigations are performed on three different LNA versions with different load inductors and a slight
topology difference. The comparison of S21 curves are
shown in Fig. 8.
The figure shows the comparison of on-wafer measurements on the three versions. Version 2 with a high Q load
inductor has a sharper response compared to first version as
expected. In addition, the third version which includes no onchip degeneration inductor has an upwards shifted response
www.adv-radio-sci.net/7/145/2009/
Figure
of packaged
packaged LNA
LNA ververFigure 11:
11: S21
S21 Comparison
Comparison of
Figure 12: NF Comparison
of2packaged
LNA versions
and 3
sions 2 and 3
Fig. 11. S21 Comparison of packaged
2 and 3.
sions 2 LNA
and versions
3
expected.
The output
matching
andinput
noiseand
figure
measureAasgood
impedance
matching
at the
output
is
ments
on-wafer
fits
to
the
simulated
results
well.
achieved for both versions with S11 and S22 less than
and NF
measurements
on the
-10 The
dB S-parameter
at the frequency
range
of interest.
Theapplication
values
PCB for version 2 and version 3 are shown in Figs. 9, 10, 11
of off-chip components are optimized to have a good
and 12.
input matching and noise figure. Although the onA good impedance matching at the input and output is
wafer
measurements
fit the simulated
well,
achieved
for both versions
with S11 results
and S22
lessthe
than
measurement
on
the
application
board
does
not
−10 dB at the frequency range of interest. The valuesfitoftooffthe
results
due to incomplete
modeling
of
chipsimulation
components
are optimized
to have a good
input matchpackage
parasitics.
reverse
isolation
(S12)
ing and and
noisePCB
figure.
AlthoughAthe
on-wafer
measurements
better
25 dBresults
and 20
dB the
andmeasurement
S21 of 13.5ondBthetoapfit thethan
simulated
well,
plication
board
does not range
fit to the
due to
17
dB at the
frequency
of simulation
interest is results
achieved.
The NF is higher than expected 1.3 dB from the simulations. However the later
measAdv.narrowband
Radio Sci., 7,noise
145–150,
2009
urements prove better results with a NF of 1.5 dB for
both versions. Input referred 1 dB Compression Point
(ICP) is measured as -5.5 dBm whereas the input re-
Figure 11
Figure
A good
good im
i
A
achieved
achieved
-10 dB
dB at
a
-10
of off-ch
off-ch
of
input
ma
input ma
wafer
me
wafer me
measurem
measurem
the simul
simu
the
package
package a
better tha
tha
better
17
dB
at
17 dB at
The
NF
The NF ii
lations.
lations.
urements
urements
both vers
vers
both
(ICP)
is
(ICP) is
ferred th
th
ferred
3.3
dBm
3.3 dBm
measured
measured
results in
in
results
the
devic
the devic
ply volta
volta
ply
only negl
neg
only
issues
are
issues are
operation
operation
the other
other
the
at
a
highe
at a highe
band
of ii
band of
modeling
modeling
for this
this aa
for
rate
mod
rate mod
be
integr
be integr
elements
elements
ramic su
su
ramic
LNA
IC.
LNA IC.
an accur
accur
an
such
app
such app
circuit
co
circuit co
NA ver-
NA ver-
150
M. Isikhan and A. Richter: CMOS low noise amplifiers for 1.575 GHz GPS applications
A better performance for this application can be provided
with more accurate modeling of package and PCB. The LNA
IC can be integrated into a SiP environment. The matching
elements can be implemented as components on a ceramic
substrate and can be packaged together with LNA IC. A good
performance can be achieved with an accurate 3-D substrate
and package modeling for such application. Utilizing bond
wire inductance as a circuit component in the design is a very
strong motivation for these investigations since it obligates a
prefect 3-D modeling for more realistic simulations.
4
Figure 12: NF Comparison of packaged LNA versions 2 and 3
Fig. 12. NF Comparison of packaged LNA versions 2 and 3.
A good impedance matching at the input and output is
incomplete
modeling
of package
A reachieved for
both versions
withand
S11PCB
and parasitics.
S22 less than
verse isolation (S12) better than 25 dB and 20 dB and S21
-10 dB at the frequency range of interest. The values
of 13.5 dB to 17 dB at the frequency range of interest is
of off-chip components are optimized to have a good
achieved. The NF is higher than expected 1.3 dB from the
input matching and noise figure. Although the onsimulations. However the later narrowband noise measurewaferprove
measurements
fit the
results
ments
better results
withsimulated
a NF of 1.5
dB forwell,
boththe
vermeasurement
on
the
application
board
does
not
fitmeato
sions. Input referred 1 dB Compression Point (ICP) is
the simulation
results
duethe
to input
incomplete
of
sured
as −5.5 dBm
whereas
referredmodeling
third Intercept
package
and
PCB
parasitics.
A
reverse
isolation
(S12)
Point (IIP3) is measured as 3.3 dBm for version 2. ICP and
better
25 dB
andmeasured
20 dB and
13.5
dB toreIIP3
forthan
version
3 are
−10S21
dBmofand
1 dBm,
17 dB at the
frequency
range of
interest
achieved.
spectively.
These
results indicate
a very
goodislinearity
perThe NF isofhigher
than expected
1.3 dB from
simuformance
the device.
The measurements
arethe
performed
for
supply However
voltage range
varying
from 2.1 Vnoise
to 3.6
V and
lations.
the later
narrowband
measonly
negligible
changes
observed.
urements
prove
better are
results
with aWhen
NF ofstability
1.5 dBissues
for
are
considered,
can be
concluded
a stable operation
both
versions. itInput
referred
1 dBthat
Compression
Point
for
version
1 and version
2 isdBm
achieved.
On the
the input
other hand
(ICP)
is measured
as -5.5
whereas
reversion
3
has
some
stability
problems
at
a
frequency
range
ferred third Intercept Point (IIP3) is measured as
of3.3
200
MHz
to the
bandfor
of interest.
dBm
forclose
version
2. frequency
ICP and IIP3
Version 3This
are is
again
due
to
the
incomplete
modeling
of
parasitic
effects.
measured -10 dBm and 1 dBm respectively. These
results indicate a very good linearity performance of
the device. The measurements are performed for supply voltage range varying from 2.1 V to 3.6 V and
only negligible changes are observed. When stability
issues are considered, it can be concluded that a stable
operation for version 1 and version 2 is achieved. On
the other hand version 3 has some stability problems
at a higher frequency range compared to the frequency
band of interest. This is again due to the incomplete
modeling of parasitic effects. A better performance
for this application can be provided with more accurate modeling of package and PCB. The LNA IC can
be integrated into a SiP environment. The matching
elements can be implemented as components on a ceramic substrate and can be packaged together with
Adv. Radio Sci., 7, 145–150, 2009
LNA IC. A good performance can be achieved with
an accurate 3D substrate and package modeling for
such application. Utilizing bond wire inductance as a
Conclusion
Three 1.575 GHz low noise amplifier versions implemented
with a 0.35 µm CMOS technology were presented. The experimental results indicate 17 dB gain and 1.5 dB noise figure. A high linearity with an IIP3 of 1 dBm is achieved. Further investigations to integrate this IC to a SiP environment
are in progress. The performance can be improved with a SiP
solution.
Acknowledgements. The presented work was partly funded by
Thuringia TMWTA under No. B 509-03006. We also thank
Björn Bieske and Uwe Baumann for their support with measurements.
References
Alvarado, U., Rodrı́guez, N., Mendizábal, J., Berenguer, R., and
Bistué, G.: A Dual-Gain ESD-protected LNA with Integrated
Antenna Sensor for a Combined Galileo and GPS front-end, Silicon Monolithic Integrated Circuits in RF Systems Topical Meeting on 10–12 January, pp. 99–102, 2007.
Bokinge, B., Einerman, W., Emericks, A., Grewing, C., Pettersson,
O., Theil, D., and van Waasen, S.: A High Performance CMOS
LNA for System-on-Chip GPS, Proceedings of Asia-Pacific Microwave Conference 2006.
van Diggelen, F.: Indoor GPS Theory and Implementation, IEEE
Position Location and Navigation Symposium, Digest of Technical Papers, pp. 240, 2002.
Razavi, B.: RF Microelectronics, Prentice Hall, ISBN 0-13887571-5, pp. 166–170, 1998.
Shaeffer, D. K. and Lee, T. H.: A 1.5-V, 1.5-GHz CMOS Low Noise
Amplifier, IEEE Journal of Solid State Circuits, 32(5), 745–759,
May 1997.
www.adv-radio-sci.net/7/145/2009/