A 60-GHz 26.3-dB Gain 5.3-dB NF Low-Noise Amplifier in 65-nm CMOS Using QFactor Enhanced Inductors
Fanyi Meng1, Kaixue Ma1,2, Kiat Seng Yeo1, Shanshan Xu1, Chirn Chye Boon1, and Wei Meng Lim1
1
School of Electrical and Electronics, Nanyang Technological University, Singapore 639798 (email:
meng0031@e.ntu.edu.sg).
2
University of Electronic Science and Technology of China (UESTC), Chengdu, China (e-mail: kxma@ieee.org).
Abstract
In this paper, a 60-GHz high gain low-noise amplifier is designed and verified experimentally. Firstly, inductors
with asymmetrical ground plane are introduced and studied by using EM simulation, obtains an improvement of
quality-factor. Then, a three-stage cascade low-noise amplifier using the proposed inductors is designed. Fabricated in
Global Foundries 65-nm CMOS process, the low-noise amplifier features a peak gain of 26.3 dB with 21.8 mW DC
power consumption, a noise figure of 5.3 dB, an average output P1dB of -4 dBm, and a core size of 0.15 mm2. In the
comparison with prior arts, the proposed design achieves the highest gain and figure-of-merit.
1. Introduction
Recently, phased-arrays on silicon RFICs are drawing much attention for 60-GHz short-range and wireless
personal area network (WPAN) supported by IEEE 802.11ad standard [1], [2]. For phased-array systems, to achieve
better sensitivity and dynamic range, the receiver front-end has to be developed with low noise figure (NF).
Fig. 1. Simplified block diagram of an N-element phased-array receiver front-end with passive phase shifters.
As illustrated in Fig. 1, the phased-array receiver front-end uses passive phase shifters for phase control in each
of the multiple elements. At 60-GHz frequency, these phase shifters normally have very high insertion loss (~18 dB in
[3]), whereas another 3 dB can be easily contributed by the power combining networks [2]. However, the reported lownoise amplifier (LNA) peak gain is only ~20 dB [4]-[7]. Thus, NF in the front-end is degraded; for instance, the NF
degradation is ~2.1 dB, if a LNA with peak gain of 20 dB and NF of 6 dB is used at the edge of its 3-dB bandwidth in
Fig. 1. Further, this degradation becomes crucial and must be treated wisely if the temperature and process variations
are considered. Therefore, one of the most promising solutions is to develop high gain LNA.
In this paper, a 60-GHz high gain LNA by using inductors with asymmetrical ground is proposed and verified.
Firstly, the method by shifting the ground plane of inductors to be asymmetrical is investigated with the 1.5-turns
inductor, which demonstrates a quality-factor (Q-factor) improvement. Then, the Q-factor enhanced inductors are
employed in the design of the 60-GHz LNA for better gain with no trade-offs. The measured results agree well with
simulated ones, and reveal the state-of-the-art performance with the best figure-of-merit (FoM) compared to prior 60GHz LNA designs [4]-[7].
2. INDUCTORS WITH ASYMMETRICAL GROUND
Spiral inductors are widely used in the matching networks of the 60-GHz LNA designs [4]-[7] for two reasons: 1)
The Q-factor (~15-18) is higher than that of transmission lines (~10-12) in deep-submicron CMOS technology; 2) The
978-1-4673-5225-3/14/$31.00 ©2014 IEEE
area occupation is typically smaller.
Fig. 2. Top view of the conventional 1.5-turns inductor and the proposed inductor with asymmetrical ground.
In Fig. 2, the 1.5-turns inductor (left) is firstly designed and optimized by using the full-wave EM simulator
ANSYS HFSS V.15, for the inductance requirements with the highest Q-factor by controlling the outer-diameter, trace
width, trace spacing, and size of surrounding ground plane [8], [9]. In the traditional inductor, the ground plane is
symmetrical along XX’ axis, whereas the inductor itself is asymmetrical due to the 1.5-turns nature, with stronger EM
field as well as return current at the top side. Thus, it is expected that the symmetry of field distribution can be retained
and inductor Q-factor can be improved, by shifting the ground plane towards the top.
18.5
155
Q-factor @ Offset = 0
Q-factor @ Offset = 2μm
L @ Offset = 0
L @ Offset = 2μm
150
17.5
145
17.0
140
16.5
135
16.0
55
56
57
58
59
60
61
62
63
64
Inductance (pH)
Quality-Factor
18.0
130
65
Frequency (GHz)
Fig. 3. Performance comparison of the inductors in Fig. 2 (Offset = 2 µm).
In Fig. 3, the effect of asymmetrical ground is studied by using EM simulation. It is observed that after shifting
the ground plane by 2 µm, the inductor is enhanced by 0.55 in Q-factor, with 1% higher in inductance at 60-GHz
frequency.
Fig. 4. Schematic of the proposed LNA (biasing circuits omitted).
Fig. 5. Micrograph of chip die.
3. Circuit Design
The proposed 60-GHz LNA is designed and implemented based on GlobalFoundries 65-nm 1P9M Lower-Power
CMOS technology, where a top metal of 3.3-μm thickness and high Q-factor inter-digital capacitors are available.
Fig. 4 shows the schematic of the proposed circuit. The LNA is in three-stage cascode topology for the stability
consideration, while the matching networks are realized majorly by spiral inductors on the thick metal layer and interdigital capacitors, and minimized length of transmission lines for interconnections only. The input and output are
designed to match to 50 Ω. Further, only small inductors (<150 pH) are used as they have better Q-factors. The circuit
design is completed by HFSS for components and full chip EM simulation, and Cadence for co-simulation. In Fig. 5,
the micrograph of fabricated LNA is shown. The circuit has a core chip area of 0.26 mm × 0.57 mm.
4. Experimental Results
The probe-based measurements are performed using Agilent N5247A PNA-X network analyzer and Cascade
Elite 300 probe station. The three gate biasing voltages are at 0.83V, 0.8V and 0.81V respectively, while supply voltage
VDD is 1.8 V.
10
30
Simulated |S21|
Measured |S21|
9
-3
8
-4
15
-20
Measured |S11|
Measured |S22|
56
57
58
59
60
61
62
63
64
-30
65
Noise Figure (dB)
-10
7
-5
6
-6
5
-7
4
55
56
57
58
59
60
61
62
63
64
Pout-1dB (dBm)
20
|S11| and |S22| (dB)
|S21| (dB)
-2
0
25
10
55
10
-8
65
Frequency (GHz)
Frequency (GHz)
Fig. 6. The simulated and measured S-parameters.
Fig. 7. The simulated NF and measured output P1dB.
In Fig. 6, the simulated and measured power gain are compared, which agree very well with <1 dB discrepancy
from 55 to 65 GHz. The measured gain has a peak value of 26.3 dB at 59.7 GHz with 3-dB bandwidth of 56.8 to 62.8
GHz. The input and output return losses are better than 10 dB from 57 to 64 GHz.
In Fig. 7, the noise figure and output P1dB performance are illustrated. The measurement of NF is still
undergoing. The simulated noise figure is <5.5 dB across the 3-dB bandwidth, with minimum value of 5.3 dB at 58.7
GHz. The measured output P1dB is -4 dBm in average.
The performance summary of the proposed LNA, and a comparison with other state-of-the-art CMOS LNAs in
the 60-GHz band, are shown in Table I. The LNA described in this paper achieves the highest power gain and the best
FoM of 23.7.
5. Conclusion
In this paper, a 60-GHz high gain LNA by using inductors with asymmterical ground plane, has been introduced
and demonstrated. The dedicated LNA achieves a peak power gain of 26.3 dB at 59.7 GHz, a 3-dB bandwidth from
56.8 to 62.8 GHz, an average output P1dB of -4 dBm, NF of 5.3 dB (simulated), and a compact size of 0.15 mm2. The
remarkable performance provides solutions to the NF degradation in phased-array receiver front-end. It is noted that the
proposed Q-factor enhanced inductors with asymmetrical ground are also applicable for performance improvements in
other millimeter-wave circuits, with no degradation in power consumptions and area occupations.
TABLE I
PERFORMANCE COMPARISON OF STATE-OF-THE-ART 60-GHZ LNAS
Ref.
ISSCC '08 [7]
MWCL '11 [6]
TMTT '13 [4]
TMTT '13 [5]
This Work
CMOS 65-nm
Tech.
CMOS 65-nm
CMOS 65-nm
CMOS 90-nm
CMOS 65-nm
Center Freq. [GHz]
59.3
61.2
58.5
58
59
59.8
Peak Gain [dB]
19.3
18.9
16.5
17.5
22
26.3
3-dB BW [GHz]
7.7
12
4.5
7
12
6
|S11| [dB]
-12
9.3
-20
-15
-10
-10
|S22| [dB]
-
13.9
-
-
-10
-12
NF [dB]
6.1
6.06
6.6
5.3
4.8
5.3*
Pout-1dB [dBm]
-2.1
-4.4
-
-
-
4
DC Power [mW]
35
45
27.9
18
26
21.8
0.21
0.25
0.37
0.51
0.63
0.15
5.1
3.9
3.9
10.1
14.1
23.7
2
Area [mm ]
-1
FoM** [GHz×mW ]
* Simulation
** FoM ⎡⎣GHz × mW −1 ⎤⎦ =
Gain [ abs ] × f c [ GHz ]
( NF [abs] - 1) × P [ mW ]
[4]
DC
6. References
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