SPECCTRAQuest ™ Simulation and
Analysis Reference
Product Version 14.2
January 2002
 1998-2000 Cadence Design Systems, Inc. All rights reserved.
Printed in the United States of America.
Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA
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Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
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SPECCTRAQuest Simulation and Analysis Reference
Contents
1
Introduction to Transmission Line Simulation
. . . . . . . . . . . . . . . . . 15
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About the SPECCTRAQuest and Allegro/APD Simulator . . . . . . . . . . . . . . . . . . . . .
Models and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interconnect Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crosstalk Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing-Driven Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMI Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMI Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Analysis Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Waveforms and VI Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conductor Cross Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground Bounce Movies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common Simulation Dialog Box Command Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Transmission Line Simulation Setup
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Simulation Setup Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Directory Structure for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Up the Simulation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Analysis Initialization Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General System Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Allegro Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Model Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Devices Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BondWires Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RefDesPins Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Removing a Model Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auditing Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SigNoise Setup Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Audit Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation Message Window and Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Developing Model Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Introduction to Model Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Analysis Library Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Library Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding and Removing Libraries in a Search List . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reordering the libraries in a Search List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying the Working Device and Interconnect Libraries . . . . . . . . . . . . . . . . . . . .
Advanced Library Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Device Library Indexes to a Search List . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Merging Device Model Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protecting Device Model Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Dmlcheck to Check Device Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Integrity Model Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Cadence Default Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Developing Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Introduction to Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Cadence Sample Model Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Available Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Model Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Model Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Model Setup in Concept or Third-Party Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Advanced Model Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Editing IBIS Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
IBIS Device Model Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Edit Pins Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Assign Power/Ground Pins Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Assign Signal Pins Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Guidelines for Specifying Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Specifying Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Adding and Changing Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Adding or Editing Buffer Delay Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
More About Buffer Delays for an IBIS Device Model . . . . . . . . . . . . . . . . . . . . . . . . . 97
Editing IBIS IOCell Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
General Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Input Section Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Output Section Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Delay Measurement Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Editing V/I Curve Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Editing V/T Curve Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Editing ESpice Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Editing PackageModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Editing Cable Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Editing Analog Output Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Analog Output Model Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Editing and Regenerating Interconnect Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Managing Models in a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Model Dump/Refresh Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
About Model Status Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Model Audit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
The dmlcheck Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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Translating Models to DML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Translating ESpice files to Generic Spice Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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Analyzing for Signal Integrity and EMI . . . . . . . . . . . . . . . . . . . . . . . . 129
Simulation Preferences and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DeviceModels Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
InterconnectModels Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Units Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMI Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About Setting Preferences and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating for Signal Integrity and EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interactive Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Batch Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crosstalk Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMI Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analyzing to Generate Text Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Standard Report Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Custom Report Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Report Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflection Summary Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ringing Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Net EMI Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parasitics Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSN Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDF Wire Delay Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Segment Crosstalk Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crosstalk Summary Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crosstalk Detailed Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Analyzing to Generate Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying the Simulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common Tab Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Tab Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Displaying and Interpreting Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conductor Cross Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crosstalk False Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crosstalk Timing Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Crosstalk Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Crosstalk Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Ignore Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Attaching and Editing Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8
EMI and Power Plane Modeling
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Power Plane Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
The EMWave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
9
Multi-Board Designs (Systems) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
System-Level Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What is a system configuration? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What is a DesignLink? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
What is a cable model? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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242
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Modeling Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Working with System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Establishing a new System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Choosing among existing System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . .
Modifying an existing System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Constraints at the System-Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System-Level Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
244
245
245
249
250
251
252
A
Modeling in the Interconnect Description Language . . . . . . . . 253
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDL Interconnect Line Segment Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RLGC Matrix Values in Interconnect Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example Line Segment Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDL Via Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example Via Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDL Shape Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example Shape Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B
DML Syntax
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About DML files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cadence Sample Device Model Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DML Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ModelTypeCategory Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tokens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter of aToken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sub-parameters of PackageModel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example of PackageModel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sub-parameters of Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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The Cadence Default Model Library. . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIG_LIB Library Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEFAULT_LIB Library Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Library Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Library Location and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
288
288
289
289
290
D
SPECCTRAQuest Standard Signal Integrity Libraries . . . . . . 291
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Installing and Licensing the Model Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Digital Logic SI Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Memory SI Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The FPGA SI Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Microprocessor SI Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
292
292
292
295
296
298
298
E
Model Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IBIS to DML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Translating EBD files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Translating Series_switch Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing VI and VT Curve Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IBIS to DML Translation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Warning and Error Messages from the Ibis2signoise Utility . . . . . . . . . . . . . . . . . . .
QUAD to DML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing VI and VT Curve Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Warning and Error Messages from quad2signoise . . . . . . . . . . . . . . . . . . . . . . . . .
Translating ESpice Files to Generic Spice Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spc2spc Translation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Computations and Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pre-Analysis Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Up Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modeling Unrouted Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Integrity Simulations and Computations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The tlsim Simulator and Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflection Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Segment-Based Crosstalk Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crosstalk Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing-Driven Crosstalk Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simultaneous Switching Noise (SSN) Simulations . . . . . . . . . . . . . . . . . . . . . . . . . .
Comprehensive Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Computations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Distortion Computations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simultaneous Switching Noise Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . .
324
324
324
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326
326
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328
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329
333
335
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Cadence Espice Language Reference. . . . . . . . . . . . . . . . . . . . . . . . 337
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About the Input Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Numeric Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Datapoint Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Statement Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Espice Syntax Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Path to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameters and Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subcircuit Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Supported Circuit Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Passive Elements: Resistor, Capacitor, Inductor, Mutual Inductor . . . . . . . . . . . . . .
Single Lossless Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Voltage Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed AC Voltage Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWL Voltage Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sinusoidal Voltage Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exponential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controlled Source Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expression Driven Controlled Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table Driven Controlled Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-linear Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-linear Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Datapoints Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-embedded Datapoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples of Controlled Source Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timecoeff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Threshold Controlled Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Types of Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rational Function Controlled Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IBIS Behavioral Model Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Behavioral Model Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Terminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charge Storage Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Behavior models: 11 terminal model . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Behavior Models: Modifying Switching Function . . . . . . . . . . . . . . . . . . . . . . . . . . .
Behavior Models: Prescaling VI and TV curves . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VI and TV prescaling at the model level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VT curves and Switching: a discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Conductor Transmission Line Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples of Multi-Conductor Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lumped RLGC with L=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
END Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
January 2002
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SUBCKT Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ENDS Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PARAM Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NODE_PARAM Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cycle Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TimeWindowMeasurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbitrary voltage crossings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NODE_PARM_DIFFERENTIAL Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRINT Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying derived names in node param statement . . . . . . . . . . . . . . . . . . . . . . . .
Inheriting node parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Espice Models for use with SPECCTRAquest . . . . . . . . . . . . . . . . . . . . . . . .
Espice Packaged Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How to use Sources and Other Functions in SigXplorer using Espice Devices . . . .
IO Buffer Model using an Espice Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
January 2002
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Introduction to Transmission Line
Simulation
■
“Overview” on page 16
■
“Models and Simulation” on page 17
■
“Crosstalk Analysis” on page 19
■
“EMI Analysis” on page 21
■
“Analysis Results” on page 22
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Introduction to Transmission Line Simulation
Overview
Transmission line simulation helps you to resolve the high speed interconnect problems that
often accompany higher density designs, shorter cycle times, higher clock frequencies,
shorter rise and fall times, and decreasing ratios of rise time to propagation delay. You can
examine a design for delay, distortion, parasitic, crosstalk effects, and design rule violations
and review the results in both waveform and text report formats.
About the SPECCTRAQuest and Allegro/APD Simulator
SigNoise (tlsim) is the transmission line simulator employed by SPECCTRAQuest. When you
analyze a design for signal integrity, SigNoise develops models of your design and simulates
the behavior of one or more extended nets. An extended net (or Xnet) is a set of connected
and coupled nets. The following figure shows an example.
Figure 1-1 An Extended Net
Net 1
Net 2
Extended Net
There are two different ways in which you can use transmission line simulation. You can
screen entire designs or large groups of nets for problem areas. Based on the results these
initial analyses, you can then analyze specific individual signals or small groups of signals in
order to troubleshoot signal integrity issues.
You can use SigNoise throughout the development of a design:
■
During critical component placement.
■
After component placement and before you route any connections.
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After you route the critical nets.
■
After you route the entire design.
Models and Simulation
During analysis, SigNoise develops simulation circuits using models of the devices and
interconnect in your design. Prior to analysis, you must associate device models with the
components in your design and point the SigNoise to the device model libraries (where the
device models are stored).
The simulation circuits are created on an as-needed basis by the SigNoise in the Interconnect
Description Language (IDL) and stored in the Interconnect Model Library that you specify.
The stored models are used later to avoid repeated field solution of the same physical
interconnect configuration. You may examine the interconnect models and modify them. See
Appendix A, “Modeling in the Interconnect Description Language” for information on IDL.
You can select device models for assignment from the Default Model Library, the Standard
Digital Device Model Library, or from another device model library that you have developed
and made available in the Library Browser. From the Library Browser, you can also create
IBIS device models from IO Buffer Information Sheet (IBIS) standard data, or edit existing
models to accurately characterize devices, and save these new models to a device model
library. For information about the Default Model Library,See Appendix C, “The Cadence
Default Model Library.” For information about the Standard Digital Device Model Library is
described in Appendix D, “SPECCTRAQuest Standard Signal Integrity Libraries.”
Device Models
The different types of device models let you choose between varying levels of detail to more
accurately model and simulate your design. The following device models are available:
■
IBIS device models that behaviorally model active devices.
IBIS device models list all the pins on a device, associate individual pins with IOCell
models, and define power and ground pins. They also list the package parasitics
associated with each pin and which power or ground bus each signal pin references. This
information is used for Simultaneous Switching Noise (SSN) analysis. Additionally, IBIS
device models can also define differential pair matings.
■
IBIS IOCell models that describe the behavior of an IO buffer (that is, drivers and
receivers).
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IOCell models represent individual drivers and receivers for specific pins on a device.
They contain behavioral information about an IO buffer, such as its voltage thresholds
and VI curves. You can assign default IOCell models so that any pin that doesn’t have a
component with a SIGNAL_MODEL property associated with it will match up with these
defaults according to its pin use. You can also determine whether or not SigNoise will use
default IOCell models.
■
Package models that are matrices of resistance, inductance, conductance, and
capacitance values for each conductor and between conductors in a package.
Package models can optionally contain within them Spice sub circuits for more detailed
package modeling.
■
Espice models that contain within them a Spice description of a device. Espice device
models are used for passive devices such as resistors.
ESpice models represent simple Spice sub circuits and represent discrete components
such as resistors and capacitors. For example, a 50 ohm resistor may be represented as
follows:
.subckt resistor50 1 2
R1 1 2 50
.ends resistor50
ESpice models can be created automatically by the software, based on device data
setup for discrete components.
■
System Configurations that describe a connection between multiple printed circuit
boards (PCBs).
System Configuration models are used in system-level simulation.
■
Cable models that describe the parasitics between multiple PCBs.
You use Cable models in multi-board systems where the Cable models typically
represent cables and connectors.
Interconnect Models
During simulation, SigNoise automatically creates the interconnect models by field solving
geometries and stores them in the interconnect model library that you specify. SigNoise
writes the models for interconnect in the Interconnect Design Language (IDL). You can also
use IDL to model passive devices as you would simple Spice subcircuits.
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Introduction to Transmission Line Simulation
You do not have to route designs prior to simulation. The unrouted interconnect modeling
information (a percent Manhattan distance between pins and user-defined assumptions for
the characteristic impedance and propagation velocity) allows you to run pre-route
simulations from the rats nest information. Using the results of these simulations, you can
evaluate items such as reflections, termination, and delays.
For routed connections, you can simulate using actual routed interconnect models In these
cases, the unrouted interconnect modeling information is ignored.
Simulations
After the interconnect parasitics are derived and the appropriate device models are retrieved
and plugged in, SigNoise builds the simulation circuit based on the type of simulation you
require. You can distinguish the different simulation types by what is included in the circuit,
and how stimulus is applied. The following types of simulation are available:
■
Reflection
■
Comprehensive
■
Crosstalk
■
SSN
■
EMI Single Net
Batch Simulation
In addition to performing signal integrity analysis interactively from the user interface, you can
also use SigNoise in batch mode. See Chapter 5, “Standard Report Generation” for more
information.
Crosstalk Analysis
You can choose between two modes of crosstalk analysis: estimated and simulated.
■
Estimated (segment-based) analysis lets you quickly scan your design to identify
problem nets and key aggressors using table-driven, closed--form algorithms.
■
Simulated (detailed) analysis uses additional full multi-line, true domain simulations for
additional accuracy and to produce waveforms.
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Introduction to Transmission Line Simulation
Timing-Driven Analysis
SigNoise lets you perform timing driven crosstalk analysis using crosstalk timing windows.
Timing driven crosstalk analysis can both minimize crosstalk false alarms and reduce the
overall pessimism of crosstalk results, thus helping you to increase the density of your
designs. You can manually assign values to the crosstalk timing properties or interactively
define or collect transition time data from a Verilog-XL or NC-Verilog simulation and use this
data to specify when a net can act as a crosstalk aggressor to victim nets and when a victim
net is vulnerable to crosstalk interference from neighboring aggressor nets.
Both the Crosstalk Estimator and the Crosstalk Simulator can be timing-driven, which greatly
increases real-world accuracy and helps eliminate pessimistic crosstalk false alarms.
Crosstalk timing windows use crosstalk timing properties to determine when nets are active
and sensitive, and only considers the aggressor nets that have an active time overlap with the
victim nets sensitive time as crosstalk contributors.
Multi-board Simulation
Simulation of a design that is made up of more than one printed circuit board (PCB) is also
possible. When a net extends to more than one PCB, SigNoise can analyze and report the
behavior of a signal as it propagates from a driver on one PCB to a receiver on another.
Timing Properties
You can apply the following crosstalk timing properties to nets:
■
XTALK_ACTIVE_TIME
■
XTALK_SENSITIVE_TIME
■
XTALK_IGNORE_NETS
You can extract XTALK_ACTIVE_TIME property values from a Verilog-XL or NC-Verilog logic
simulation and import them into the design database for use by SigNoise. See Crosstalk
Timing Windows for more information.
You can assign the XTALK_SENSITIVE_TIME property to specific receiver pins for even
greater accuracy to indicate times when that pin is susceptible to crosstalk and when it is not.
You can use the XTALK_IGNORE_NETS property to tell a net or a group of nets to disregard
other nets or group of nets as a source of crosstalk. (When you want to disregard crosstalk
between bits on a synchronous bus, for example.)
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A Simple Example
In Crosstalk simulations, you can use the XTALK_ACTIVE_TIME,
XTALK_SENSITIVE_TIME, and XTALK_IGNORE_NETS crosstalk properties to determine
how to stimulate multi-line circuits for crosstalk analysis. For example, assume a victim net
being analyzed for crosstalk had 2 aggressor nets, and they had the following properties:
■
victim net - XTALK_SENSITIVE_TIME = 5-10
■
neighbor #1 - XTALK_ACTIVE_TIME = 7 - 15
■
neighbor #2 - XTALK_ACTIVE_TIME = 20-25
Neighbor #2 would not be stimulated in the circuit, since its active time does not overlap with
the victim net's sensitive time. In this case, stimulating both aggressor nets together would be
overly pessimistic, and not indicative of real-world behavior.
EMI Analysis
EMI Simulation
SigNoise provides EMI single net simulations which allow you to compute differential mode
radiated electric field emissions from traces. Simulation results include a graphical display of
the emission spectrum and a text report summarizing emission details and compliance
results.
Using SPECCTRAQuest EMControl
You can use SigNoise in conjunction with EMControl to perform EMI analysis. Some of the
signal routing and signal quality rules provided with EMControl employ SigNoise simulations
and SigNoise device models during analysis for EMI. Using EMControl enables design
engineers to begin evaluating their designs for EMI early in the design process and with
increasing accuracy throughout design development.
Before running EMC rule-checking, you need to perform the following SigNoise setup tasks:
■
Specify any analysis preferences. If necessary, SigNoise will create a new simulation
case directory.
■
Specify which device and interconnect model libraries SigNoise should use.
■
Assign the device models to components.
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In addition when you initialize the EMControl run directory, you need to point EMControl to
this SigNoise run directory. See the EMControl documentation for more information.
Analysis Results
SigNoise provides its analysis results in the form of:
■
Nine types of standard analysis text reports
■
Custom designed text reports
■
Waveforms and accompanying data
■
Conductor Cross Section diagrams
■
Ground Bounce Movies
Standard Analysis Reports
Descriptions for the different types of standard analysis text reports generated by SigNoise
are provided in the following table.
Table 1-1 Standard Analysis Reports
Report Type
Description
Reflection Summary
Gives delay and distortion data in a concise, summary format.
Delay
Gives propagation delays, switch delays (rising and falling
edge), settle delays (rising and falling edge), and reports a pass
or fail status for first incident rise and fall and monotonic rise and
fall heuristics for selected nets.
Ringing
Gives overshoot and noise margin values for selected nets.
Single Net EMI
Gives essential EMI data for the net in a concise, single-line
format.
Parasitics
Gives total self capacitance, impedance range, and transmission
line propagation delays for selected nets.
SSN report
Gives noise levels induced on a component’s power and ground
busses when drivers on that bus switch simultaneously.
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Table 1-1 Standard Analysis Reports
Report Type
Description
Segment Crosstalk
Gives estimated peak and total crosstalk for selected nets.
Crosstalk values are derived from closed form algorithms using
tables produced from time domain simulation.
Crosstalk Summary
Gives peak and total crosstalk for selected nets in a concise,
summary format. Crosstalk values are derived from multi-line
simulations.
Crosstalk Detailed
Gives total crosstalk on selected nets for all cases. Crosstalk
values are derived from multi-line simulations.
Custom Reports
You can define and then generate text reports with a specific format that you define using the
Custom Report tab in the Report Generator dialog box.
Waveforms and VI Curves
The waveform data shows the waveform of a signal on a driver-receiver pair.
SPECCTRAQuest contains a waveform display tool called SigWave. SigWave can display
waveforms for all pins in a simulation circuit as well as the VI curves for IOCell models.
Conductor Cross Sections
SigNoise generates models for the interconnect in your design. The field solver generates the
parasitic values in the model. The SigXsect window shows you a three-dimensional view of
the interconnect and its parasitic values.
Ground Bounce Movies
When you use power and ground plane design features of the Power Plane Builder to perform
SSN simulation with the Do Plane Modeling feature enabled, SigNoise produces a three
dimensional animated movie depicting the ground bounce generated during the simulation.
You can use the EMWave window to view the movie as well as a static view of the RF hot
spots that occurred.
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Common Simulation Dialog Box Command Buttons
The following table describes the common command buttons found on most simulation dialog
boxes within the SPECCTRAQuest and Allegro/APD environments.
.
Table 1-2 Common Simulation Dialog Box Command Butons
OK
Saves all changes and closes the dialog box.
Apply
Saves all changes but does not close the dialog box.
Cancel
Closes the dialog box without saving any changes.
File
Contains options for saving form messages to a file and closing the form.
Close
Closes the form.
Help
Displays online help that describes the dialog box or form. Both reference
information and related procedures are displayed.
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Transmission Line Simulation Setup
■
“Simulation Setup Options” on page 26
■
“Run Directory Structure for Simulation” on page 27
■
“Setting Up the Simulation Environment” on page 32
■
“Environment Variables” on page 38
■
“Model Assignment” on page 42
■
“Auditing Simulation Setup” on page 51
■
“Simulation Message Window and Log File” on page 54
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Simulation Setup Options
To set up for simulation:
➤
Select any of the menu options shown in the following figure from the main menu of either
the SPECCTRAQuest Floorplanner or Allegro/APD
The following table describes each of the SI/EMI Sim menu options.
.
Table 2-1 SI/EMI Simulation Menu Option Descriptions
Menu Option
Action
Initialize
Displays the Signal Analysis Initialization dialog box. See
“User Directed Initialization” on page 33. For procedural
information, see the SigNoise online help.
Library
Displays the Signal Analysis Library Browser for working with
libraries and models. See Chapter 3, “Signal Analysis Library
Browser.” For procedural information, see the SigNoise online
help.
Model
Displays the Signal Model Assignment dialog box for
assigning models to components. See “Model Assignment” on
page 42. For procedural information, see the SigNoise online
help.
Model Dump / Refresh
Displays the Model Dump/Refresh dialog box for dumping
signal integrity models (stored) in the current design to a
library or refreshing models in the current design with
changes made to their source files in the library. See
Chapter 4, “Managing Models in a Design.” For procedural
information, see the SigNoise online help.
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Table 2-1 SI/EMI Simulation Menu Option Descriptions
Menu Option
Action
Preferences
Displays the SigNoise Preferences dialog box for specifying
the analysis parameters. For details, see Chapter 5,
“Simulation Preferences and Parameters.” For procedural
information, see the SigNoise online help.
Audit
Displays a menu of verification commands. See “Auditing
Simulation Setup” on page 51 and “Using Dmlcheck to Check
Device Libraries” on page 65. For procedural information, see
the SigNoise online help.
Probe
Displays the Signal Analysis dialog box for detailed analysis.
For details, see Chapter 5, “Signal Analysis dialog box.” For
procedural information, see the SigNoise online help.
Xtalk Table
Displays the Signal Analysis Crosstalk Table dialog box to
specify either the reading of an external crosstalk table or the
generation of an internal table for use by SigNoise. See
Chapter 6, “Crosstalk Timing Windows,” for more information.
For procedural information, see the SigNoise online help.
Run Directory Structure for Simulation
Creation Scheme
SigNoise is the SPECCTRAQuest simulation engine. It creates the run directory structure
required for simulation when it is needed. In most cases, the parent directory of the SigNoise
run directory structure is the directory from where you start your design software. Your start
directory contains a log file (signoise.log) which contains information about libraries
which are currently loaded as well as a run directory (signoise.run).
Your current working directory is always tracked by SigNoise. If you open a design in a
different directory, SigNoise switches focus to the new directory, adjusts settings accordingly,
and uses the local signoise.run directory (if one exists). Otherwise, a new run directory
structure is created there and a message issued announcing the action.
Note: You can use the SIGNAL_RUN_DIRECTORY environment variable to establish a
default run directory. See “Environment Variables” on page 38 for more information.
The following figure depicts the files and sub-directories that are contained within a typical
working directory.
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Figure 2-1 Working Directory Structure
Working Directory
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signoise.run Directory
The following figure depicts the files and sub-directories that are contained within the
signoise.run directory:
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Figure 2-2 Simulation Run Directory Structure
signoise.run Directory
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case# Directories
case# Directory
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sim# Directories
signoise.run Directory Contents
■
signoise.cfg - Contains the configuration information that is general and common to all
simulations. For example, information on whether a System Configuration model is active
and the name of the current device model library is included here.
■
cases.cfg - Contains a listing of the case directories and the descriptive text string
associated with each case.
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Case# Directory Contents
SigNoise creates a new case directory whenever one is required. You also have the option to
create case directories manually and to determine characteristics of the cases that SigNoise
creates. See “Case Management” on page 36 for more information.
■
case.cfg - Contains the configuration information that is specific to that particular case.
This information includes, for example, the text string describing the case and the stimuli
to be applied when a simulation for this case is run.
■
projstat.dat - Lists timestamp data for each .brd file in the system as well as each .dml
loaded. Use this information to determine when these files have been modified.
■
sigsimcntl.dat - Lists each simulation which has been run, regardless of whether or not
waveforms or circuits have been saved. Also listed are the parameters that went into
each simulation (sim1, sim2, and so on). The names of previous simulations, whose data
is used by SigNoise for computing results are found using this file. This file is autosaved
after every fifty simulations and when SigNoise quits.
■
sigsimres.dat - Lists each measured pin in each simulation that has been run. Each line
contains all the measured data for that pin. This file is autosaved after every fifty
simulations and when SigNoise quits.
■
sim# Directories - The sim1, sim2, and so on subdirectories are created only when
Save Circuit Files is on. They contain all input and output files for a specific simulation,
except for the .sim waveform files that get saved to the waveforms directory.
■
waveforms - If you elect to save circuit files (in either the Report Generator or the
WaveForm Simulation dialog boxes), SigNoise saves Spice files in the simulation
directories. If you elect to save waveforms (in the Report Generator), SigNoise saves the
waveform files corresponding to SigNoise runs (sim1.sim, sim2.sim, and so on) in the
waveforms directory.
When you perform an EMI emissions simulation, SigNoise saves both the time voltage
waveform files corresponding to SigNoise runs (sim4.sim, sim5.sim, and so on) and the
files containing the emission spectrum in the frequency domain (sim4_emi_db.sim,
sim5_emi_db.sim, and so on) in the waveforms directory.
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Figure 2-3 Simulation Run Directory Structure (cont.)
sim# Directory
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sim# Directory Contents
■
comp_rlgc.inc - Describes the package parasitic values of package model RLGC
matrices.
■
comps.spc - Describes component sub circuits, and power and ground values of the
simulation. It also contains package parasitics when package model contains spice
subcircuits.
■
cycle.msm - Lists the simulation results for each node to be measured. It conhtains
delay and distortion data.
■
delay.dl - Lists the delay simulation results.
■
distortion.dst - Lists the distortion simulation results.
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ibis_models.inc - Describes the parameter values of IbisIOCell model definitions.
■
interconn.spc - Describes sub circuits of interconnect model definitions.
■
main.spc - This is the main Spice file calling the other Spice sub circuits.
■
ntl_rlgc.inc - Describes the parameter values of trace model RLGC matrixes.
■
stimulus.spc - This Spice file describes the stimulus input.
■
tlsim.log - The log file for the Cadence proprietary Spice simulator.
Setting Up the Simulation Environment
Initialization
You do not have to perform any manual initialization tasks before you simulate. When started,
SigNoise will take the following initialization actions.
Automatic Initialization for Signal Integrity or EMI Simulation
When you initiate a signal integrity or EMI simulation from SPECCTRAQuest Floorplanner,
SPECCTRAQuest SigXplorer or Allegro/APD, SigNoise performs the following tasks:
■
Assume single board analysis mode.
■
Open or write the signoise.log file in the start directory.
■
Use or create the signoise.run directory structure.
■
Run the most recently used case.
■
Use the system configuration last used in the current case.
Each case runs in its own sub-directory (within the signoise.run directory). On the first
run SigNoise creates the case1 sub-directory containing the current (active) case.
Subsequently, new, consecutively numbered case sub-directories are created as needed.
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User Directed Initialization
To initialize SigNoise manually:
➤
Select the option shown in the following figure from the main menu of either the
SPECCTRAQuest Floorplanner or Allegro/APD .
The Signal Analysis Initialization dialog box is displayed as shown in the following figure.
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Figure 2-4 Signal Analysis Initialization Dialog Box
Using this dialog box you can:
■
Elect to perform signal integrity analysis on a single board or to analyze a multi-board
system using a System Configuration model.
■
Perform case management tasks:
❑
Change the current case.
❑
Create a new case or delete an existing case.
❑
Edit the comments associated with a case.
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Dialog Box Fields and Buttons
The following tables describe the data fields and command buttons in the different areas of
the Signal Analysis Initialization dialog box.
Table 2-2 System Configuration Setup Area
Option
Function
System Configuration
Current simulator operation mode. Choices are:
“Single Board System” (default)
The name of a multi-board system
Table 2-3 Case Setup Area
Option
Function
Current Case
Name of the current case under analysis.
Case list box
Lists available cases with descriptions. The current case is
highlighted.
Case update check
box
Indicates whether you want to be notified about case updates
whenever the project changes.
Table 2-4 Command Buttons
Button
Function
New DesignLink
Displays the System Configuration Editor dialog box to create a
new system configuration.
Edit DesignLink
Displays the System Configuration Editor dialog box to modify the
current system configuration.
Browse
Displays a File Browser to search and select a system
configuration (.scf) file.
New Case
Creates a new case.
Set Desc. . .
Displays the dialog box shown in Figure 2-5 for adding or editing
a case description.
Remove Case
Deletes a selected case.
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Figure 2-5 The Set Case Description Dialog Box
Signal Analysis Initialization Usage Notes
Single Board and Multi-Board Setup
By default when you perform a simulation operation, SigNoise runs in single board mode on
the current design. From the Initialization dialog box you can select to operate SigNoise in
multi-board mode. Multi-board mode enables you to analyze a system of more than one
printed circuit board using a System Configuration model.
Case Management
Setup and analysis data are partitioned into cases with one case being operated on at a time.
You can use the initialization dialog box to manually create and delete cases, and to switch
from the current case to another existing case. When you change to a different case using
the initialization dialog box, upon confirmation (OK), all other dialog boxes are updated to
reflect the case data file (case.cgf) for the new current case.
When you initiate an operation which would change the case data file, case.cfg, in a way that
could invalidate simulation data in the current case directory, you are notified of the change
by the display of the Update Case dialog box.
You can choose to:
■
Create and name a new case based on a copy of the configuration information in the
existing case.cfg file, plus the proposed change.
Make the new case the current case and begin working there. The new case includes no
existing simulation data.
■
Add the proposed change to the current case, clear all existing simulation data from the
case, and continue work there.
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Add the proposed change to the configuration of the current case and continue working
there.
All existing simulation details are retained. Do this only when you are certain that new
simulation data, based on the modified configuration information, will be compatible with
existing simulation data.
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Environment Variables
SigNoise references local environment variables that you can set to customize your
simulation environment. Some of the system variables are standard while others apply only
to SigNoise.
General System Variables
General system variables can be set in either your local .cshrc file (UNIX platforms) or in
the System Properties dialog box (Windows NT platform).
Setting Variables on UNIX Platforms
The variables in the following table can be set by adding its command line as an entry in your
local.cshrc file.
Table 2-5 General System Variables on UNIX Platforms
Variable
Name
Purpose
Command Line
EDITOR
Sets the default text
editor.
setenv EDITOR ‘xterm -e /usr/ucb/vi’
PRINTER
Sets the default
printer to be used
when a print
command is given.
setenv PRINTER printer_name
Note: If the EDITOR variable is not set, SigNoise will run xterm vi when you text edit a file.
You may omit the xterm for editors that open a new window of their own.
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Setting Variables on the Windows NT Platform
You can set the variables that are described in the following table by adding an entry within
the User Variables section of the System Properties dialog box.
Table 2-6 General System Variables on the Windows NT Platform
Variable
Name
Purpose
Value
EDITOR
Sets the default text
editor.
editor_application_name
PRINTER
Sets the default
printer to be used
when a print
command is given.
printer_name
Allegro Environment Variables
The Allegro environment variables for both the UNIX and Windows NT platforms are set in
your local env file. They apply to Allegro, the Transmission Line Simulator, and other analysis
tools which reference them. You are not required to set these environment variables, but
certain tasks will be easier if you do. Setting these environment variables is optional.
To create a local env file:
1. Make a pcbenv directory under your home directory.
2. Copy the <install_dir>/share/pcb/text/env_local.txt fileto your pcbenv
directory and name it env . Using a copy of this file will force the Cadence global env file
to be read first.
3. Edit this file to add your environment variable settings, aliases, and so on to the end of
the file.
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Setting Variables
You can set the variables in the following table by adding its command line as an entry in your
local env file.
Table 2-7 Allegro User Environment Variables
Variable Name
Function
TOPOLOGY_
TEMPLATE_PATH
Sets the path where topology set TOPOLOGY_TEMPLATE_PATH =
templates are stored.
/home/sig6/newboard/tops
Sets the path to various items set SIGNOISEPATH = ~/cds/
used by SigNoise, such as
tools/pcb/text
the default libraries.
Useful when trying to
set DISPLAY_NOHILITEFONT
highlight a trace on a fully
routed board. The highlight is
a solid color.
Sets all net-to-net results
set LOG_NET_XTALK
from the Crosstalk Estimator
to be logged in the Allegro
message window and the
signoise.log file.
SIGNOISEPATH
DISPLAY_
NOHILITEFONT
LOG_NET_XTALK
SIGSUPPRESS
Command Line Syntax
Suppresses display of the
set SIGSUPPRESS
specified types of messages [list_of_message_types]
in SigNoise’s Message Log
window. Follow the variable
name with a spaceseparated list of message
types to suppress.
These can be warning and/
or error messages. Case is
not significant.
SIGNAL_RUN_
DIRECTORY
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Sets SigNoise to use an
setenv SIGNAL_RUN_DIRECTORY
existing run directory,
/home/sig7/projects/
signoise.run. When the signoise.run
design software is started,
SigNoise will use this run
directory.
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Table 2-7 Allegro User Environment Variables
Variable Name
Function
Command Line Syntax
SIGNAL_DEVLIBS Sets the default device
libraries that appears in the
library search list.
SIGNAL_ICNLIBS
setenv SIGNAL_DEVLIBS /home/
sig6/new.dml /home/sig5/
std.dml
Sets the interconnect model setenv SIGNAL_ICNLIBS /home/
libraries that appears in the sig6/intrconn1 /home/sig5/
library search list.
intrconn2
SIG_MAPFILE_OR Specifies that the original
GPATH
model path be used in the
device model assignment
map file when it is saved.
setenv SIG_MAPFILE_ORGPATH 1
Note: The SIGNAL_DEVLIBS and SIGNAL_ICNLIBS variables do not apply to SigNoise run
directories created before the variables were set. Also, if you specify a directory, rather than
a file, SigNoise will include all libraries (*.dml*) in that directory within the library search list.
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Model Assignment
SigNoise uses device models, IOCell (or buffer) models, and trace models to create complete
simulation circuits for nets in your design. You can assign device models to discrete devices
automatically.
Before performing simulations, you should use Analysis – SI/EMI SIm – Audit command
options to verify that each component has a model assigned to it. When necessary, as
reported in the SigNoise Setup Report, you are required to manually assign device models.
SigNoise will generate and assign trace models for the bond wires or you can manually
assign trace models to bond wires yourself.
To assign device and interconnect models to design objects:
➤
Select the option shown in the following figure from the main menu of either the
SPECCTRAQuest Floorplanner or Allegro/APD .
The Signal Model Assignment dialog box is displayed as shown in the following figure.
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Figure 2-6 Signal Model Assignment - Devices Tab
Using this dialog box you can perform the following tasks.
■
Have SigNoise automatically assign models to capacitors and resistors.
■
Manually assign models to components and bond wires.
■
Disassociate models from design objects.
■
Save model assignments to a Model Assignment mapping file or load an existing
mapping file.
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Devices Tab
Using the Devices tab on the Signal Model Assignment dialog box, you can assign device
models to components in the design either manually or automatically. See Figure 2-6 on
page 43.
Tab Options and Buttons
The following tables describe the command options and buttons in the different areas of the
Devices tab.
Table 2-8 Devices Tab Options
Option
Function
DevType/RefDes
Tree of device types for components. Expands to display reference
designators for components of that type.
Signal Model
The model name currently assigned to a device type or reference
designator.
Source Library
The library containing the signal model.
Signal Model
The model name currently selected for assignment.
Table 2-9 Devices Tab Buttons
Button
Function
Create Model
Displays the Create Model dialog box for the selected component.
Prompts for the creation of an Espice device model or an IBIS
device model for the component.
Find Model
Displays a Model Browser for device model matching.
Edit Model
Invokes an appropriate model editor enabling model modification.
Save
Saves model assignments to a model assignment data file which
maps device types to appropriate models.
Load
Loads a model assignment data file.
Include ORIGINAL
Path in Map File
When checked (ON), specifies that the original model path be used
in the map file when saved. The default is unchecked (OFF).
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Table 2-9 Devices Tab Buttons
Button
Function
Auto Setup
Start automatic model assignment for all components with no
previous assignment.
Clear All Model
Assignments
Removes all model assignments in the design.
Preferences
Displays the Analysis Preferences dialog box.
OK
Closes the dialog box and stores your model assignments in the
design database. Generates a Signal Model Assignment Changes
report.
Devices Tab Usage Notes
■
Use Preferences at anytime while using the Signal Model Assignment dialog box to
display the SigNoise Preferences dialog box. Through this dialog box, you can change
the characteristics of the default device and interconnect models.
■
Use Auto Setup to automatically assign device models to simple components such as
capacitors and resistors using the device type prefix as a reference. In order for
automatic model assignment to succeed, components must have reasonable value
property data in the design database.
■
For manual model assignments, either assign a single device model to all components
having the same device file or assign individual device models to individual components
specified by reference designator. When you specify a model you can enter a model
name in the Signal Model field, or select a model in the Model Browser.
Use Find Model to display a set of models appropriate for the selected DevType or
RefDes.
■
You can also use Create Model to invoke a model editor and create a model from
scratch. Depending on the value property data associated with the component, either the
Create ESpice Device Model dialog box or the Create IBIS Device Model dialog box is
invoked.
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BondWires Tab
Use the BondWires Tab to assign trace models to individual bond wire connections in the
design or to modify trace models. Bond wires are connect lines (clines) on wirebond layers.
When the Model Browser is open along with the Signal Model Assignment dialog box, the
name of a trace model selected in the Model Browser also displays in the Signal Model field.
Figure 2-7 Signal Model Assignment - BondWires Tab
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Tab Fields and Buttons
The following tables describe the command options and buttons in the different areas of the
BondWires tab.
Table 2-10 BondWires Tab Options
Option
Function
Die Pad, Pkg Pin,
Net
A tree displaying the die pad, package pin, and net for a bond wire.
Signal Model
The trace model currently assigned to a bond wire.
Signal Model
The model selected for assignment.
Table 2-11 BondWires Tab Buttons
Button
Function
Find Model
Displays the Model Browser to find trace models.
Edit Model
Invokes an appropriate model editor enabling trace model
modification.
Assign Current
Signal Model to
bond wire Picks
Click to assign the signal model named in the Signal Model: type-in
field to the selected bond wires.
All
Assign the signal model named in the Signal Model type-in field to
all bond wires.
Preferences
Displays the Analysis Preferences dialog box.
BondWires Tab Usage Notes
■
With a cline segment selected in the design, use View Geometry to invoke the sigXsect
window to display the cross-section geometry for the cline at the exact point selected.
■
To manually assign trace models, select a net or cline in the design then use Create
Models to create an appropriate interconnect model or use Find Model to view and
select existing trace models in the selected interconnect library.
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RefDesPins Tab
Use the RefDesPins tab to assign IOCell models and programmable buffer models to
individual pins identified by reference designator. You can also modify existing models during
assignment. When the model Browser is open along with the Signal Model Assignment dialog
box, the name of the model selected in the Model Browser also displays in the Signal Model
field.
Figure 2-8 Signal Model Assignment - RefDesPinsTab
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Tab Fields and Buttons
The following tables describe the command options and buttons in the different areas of the
RefDesPins tab.
Table 2-12 RefDesPins Tab Options and Buttons
Option
Function
Refdes
A tree of reference designators for components in the design.
Expand to display pin numbers and pinuse.
Signal Model
The IOCell models assigned to the pins.
Device Class FIlter A list of available device classes to limit the display of reference
designators in the list box.
Signal Model
The model name selected for assignment.
Table 2-13 RefDesPins Tab Buttons
Button
Function
Prog. Buffers
Displays a list of the Programmable Buffer models available in the
library for the selected pin. The number to the right indicates the
number of available models for the selected pin.
Create Model
Creates the model.
Find Model
Displays the Model Browser to find IOCell or Programmable Buffer
models.
Edit Model
Invokes an appropriate model editor to enable IOCell or
Programmable Buffer model modification.
Display All /
Display IBIS
Buffers Only
Toggles between the display of all pins in the design (by component)
or only pins which have programmable buffers.
Preferences
Displays the Analysis Preferences dialog box.
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RefDesPinsTab Usage Notes
■
If necessary, use the Preferences button to modify default data values.
■
To assign an existing IBIS Device model, you can enter a model name in the Signal
Model field, or select a model in the Model Browser. Use the Find Model button to
display models appropriate for the selected reference designator.
■
To activate the Prog. Buffers command button, first select a Programmable Buffer
model from the working library.
Removing a Model Assignment
To remove a device model assignment from a component, net, or cline, first select the net,
cline, or component in the list box and then enter a blank character in the Signal Model typein field.
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Auditing Simulation Setup
SigNoise Setup Report
The SigNoise setup report presents information discovered during a design or net audit
process.
To check your design setup:
➤
Select the option shown in the following figure from the main menu of either the
SPECCTRAQuest Floorplanner or Allegro/APD.
As your design and it’s libraries are being checked, the simulator displays a progress meter
is displayed followed by the display of the SigNoise setup report.
The following figure shows the SigNoise setup report window with a sample report. Use this
window to view and save the setup report as needed.
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Figure 2-9 Simulator Setup Report Window
The report data areas are described in the following table.
Table 2-14 Simulator Setup Report Data
Area
Data Description
Errors
A list of setup faults that must be resolved to avoid serious
problems.
Warnings
A list of setup faults that, if resolved, will enhance accuracy.
Information
Information about the design, including existing setup data.
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Design Audit Checks
To find serious setup problems (Errors), SigNoise checks for the following situations:
■
Zero thickness layers in the layerstack
■
Unplaced components
■
Nets with POWER or GROUND pins, but no VOLTAGE property
■
Nets with POWER or GROUND pins or VOLTAGE property, but no shape or
VOLTAGE_SOURCE pin
■
No VOLTAGE property on any net
■
Nets with no drivers or receivers, and no pins attached to a component with an
ESpiceDevice SIGNAL_MODEL reference
■
C-lines with a SIGNAL_MODEL reference that do not exist in any open interconnect
library
■
No working interconnect library
■
Active system configuration reference is not loaded or its DesignLink model does not
exist in any open device library
■
Default IOCells that do not exist in any open device library
■
Components with a SIGNAL_MODEL reference that do not exist in any open device
library
■
Model versions
■
Referenced device models that do not pass dmlcheck (Audit Report will list problem
models, but actual errors will appear in SigNoise log window)
■
Pin signal_model parameters in IBISDevice pinmap do not match Allegro pinuse
■
Allegro component pins not found in IBISDevice pinmap (other than NC pins)
■
Components with Allegro TERMINATOR_PACK property not assigned an ESpiceDevice
SIGNAL_MODEL property
■
Shapes on PLANE layers with no VOLTAGE property on a net.
■
Layers with improper material for a given layer type.
■
Nets with improper differential pair connections like non-inverting driver that is driving an
inverting receiver.
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Nets with Allegro DIFFERENTIAL_PAIR property and no differential pair signal models
on pins, or vice versa.
■
DISCRETE components with the wrong PINUSE property.
To find setup problems that might hinder accuracy (Warnings), SigNoise checks for the
following situations:
■
Default settings in the layerstack
■
Wirebond layers that do not have the SIGNAL_MODEL property attached to clines
■
Components that have no SIGNAL_MODEL property
■
Nets with DC VOLTAGE property
■
Default IOCELL models that are not set.
■
PLANE layers that have no name assigned.
SigNoise reports the following design information:
■
Layerstack information
■
Number of nets and components
■
Assigned models, including the library file
Simulation Message Window and Log File
Warning and error messages generated during simulation are displayed in the SigNoise
Errors/Warnings window. The window opens when the first message is generated and the
display list expands for each subsequent message. When you perform the next simulation
action, all existing messages are cleared and the window is closed.
The Signoise Errors/Warnings window displays warnings below error messages. As the
simulator generates new messages, they are added to the top of each list. Duplicate
messages are filtered out of the list. The associated signoise.log file logs all informational
messages, warnings, and errors.
Note: You can suppress the display of SigNoise Errors/Warnings window by setting the
SIGSUPPRESS environment variable. See “Environment Variables” on page 38 for more
information.
The SigNoise Errors/Warnings window with a sample list of warnings is shown in the following
figure.
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Figure 2-10 The SigNoise Errors/Warnings Window
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Developing Model Libraries
■
“Introduction to Model Libraries” on page 58
■
“Signal Analysis Library Browser” on page 58
■
“Basic Library Management” on page 62
■
“Advanced Library Management” on page 63
■
“Signal Integrity Model Libraries” on page 67
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Developing Model Libraries
Introduction to Model Libraries
When analyzing a design, SPECCTRAQuest builds simulation circuits using the device
models that have been stored in your design (.brd file). These resident device models are
associated with devices in your design. During simulation, SigNoise automatically constructs
the required interconnect models. The actual source files for these device and interconnect
models are stored and organized in either device model libraries (DML’s) or interconnect
model libraries (IML’s) that are external from the design database.
Signal Analysis Library Browser
You can use the Signal Analysis Library browser to create and manage your libraries of
device and interconnect models and to access the Model Browser dialog box. You can also
use it to specify which device and interconnect libraries you want SigNoise to access, as well
as the order of library access.
To display the Signal Analysis Library Browser dialog box:
➤
Select the option shown in the following figure from the main menu of either the
SPECCTRAQuest Floorplanner or Allegro/APD .
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.
The Library Browser is divided into two parts.The top half contains the device library search
list and the buttons and fields you use to manipulate device models and device model
libraries.
The bottom half contains the interconnect library search list and the buttons and fields you
use to manipulate interconnect models and interconnect model libraries. You can use the
buttons along the bottom of the dialog box (for example, Translate) with both parts of the
dialog box.
Note: You can specify default device and interconnect model libraries using Allegro
environment variables. See Chapter 2, “Allegro Environment Variables.”
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Developing Model Libraries
Using the Library Browser you can perform the following tasks.
■
Add an existing device or interconnect model library to a library search list.
■
Create a new library and add it to a library search list.
■
Reorder the libraries in a library search list.
■
Remove libraries from a library search list.
■
Specify the working device and interconnect model libraries; the only libraries to which
newly created models can be added.
■
Create an index for a device model library.
■
Merge two or more device model libraries.
■
Translate models to a DML from other formats.
■
Display the Model Browser.
Browser Command Buttons
The following tables describe the function of the command buttons found on the Library
Browser dialog box.
Table 3-1 Device Library Files Area
Button
Function
Browse Models
Displays the Model Browser.
Remove Library
Removes selected device libraries from the device library search list.
Move Up
Raises the selected device library one position up in the device
library search list.
Move Down
Lowers the selected device library one position down in the device
library search list.
Set Working
Sets the working (or active) library for device models.
Note: Before you edit or add new models, make the target library the
working library.
Make Index
Creates an index file for all of the .dml files present in the library list.
Note: The working library is excluded.
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Table 3-1 Device Library Files Area
Button
Function
MergeDML
Merges all device model libraries present in the library list
into a single library.
Add Existing
Library
Adds the selected device library or device index to the device library
search list. Choices are:
Local Library
Standard Cadence Library
Optional Cadence Library
Create New
Library
Displays a file browser where you can specify the name of the device
library to be created and added to the device library search list.
Table 3-2 Interconnect Library Files Area
Button
Function
Browse Models
Displays the Model Browser.
Remove Library
Removes selected interconnect model libraries from the device
library search list.
Move Up
Raises the selected interconnect library one position up in the device
library search list.
Move Down
Lowers the selected interconnect library one position down in the
device library search list.
Set Working
Sets the working (or active) library for interconnect models.
Note: Before you edit or add new models, make the target library the
working library.
Add Existing
Library
Adds a selected interconnect library to the interconnect library search
list.
Create New
Library
Displays a file browser where you can specify the name of the
interconnect library to be created and added to the interconnect
library search list.
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Table 3-3 Common Buttons (Device and Interconnect)
Button
Function
Translate
Accesses a list of translator programs to convert various simulation
formats to .dml or .iml files. Choices are:
ibis2signoise
quad2signoise
Apply
Apply the library changes without closing the browser.
OK
Apply the library changes and close the browser.
Basic Library Management
Adding and Removing Libraries in a Search List
Device and Interconnect models cannot be accessed unless their libraries are first added to
the library search list. Conversely, if a library is no longer in use, it can be removed from the
search list thereby improving overall library access performance.
Reordering the libraries in a Search List
Libraries are searched starting at the top of the list. In cases where a model is included in two
or more libraries, you can use the search order to determine which library SigNoise searches
first. SigNoise uses the first model found.
Specifying the Working Device and Interconnect Libraries
SigNoise adds models to the working libraries only. If you want to add a model to a library that
is not the working library, you must first make it the working library before you start the
process. You can have one working device model library and one working interconnect model
library active at one time.
Important
The name of the working library for device or interconnect models appears in the
Working: field above the library search list.
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Advanced Library Management
Adding Device Library Indexes to a Search List
To improve access performance with large device model libraries, you can add a library index
(in place of the library file) to the Device Library search list. An index is a .ndx file that
contains pointers to the device models in the DML. The index requires fewer resources
because only models required for analyses are loaded from the index into memory, as
opposed to loading the entire library. This utility performs the same checks as dmlcheck, to
ensure that the indexed models are syntactically correct. Only models that pass dmlcheck
will be indexed.
Note: Index files are read-only. For this reason, you cannot index any library currently
designated as the working library to which SigNoise automatically writes any edits.
Use the mkdeviceindex utility to create a library index for one or more device model library
files. You can access the mkdeviceindex utility from the Library Browser (Make Index
button) or the command line.
To access the mkdeviceindex utility from the command line, enter the following
command.
mkdeviceindex [-d] [-o <index_filename>] <library_filename>...
Table 3-4 Mkdeviceindex Arguments
Argument
Function
-d
Checks model dependencies. For example, an IBIS Device model
will be indexed only when all required IOCell and PackageModel
models are present and pass the checks.
-o
Names the device model library index.
index_filename
Names the device model library index for the IBIS input file you
want to translate.
library_filename Names one or more device model libraries.
Note: You can also specify directories which are hierarchically
searched for *.dml files.
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Merging Device Model Libraries
The mergedml utility enables you to combine one or more model libraries into a single library.
You can access the mergedml utility from the Library Browser (Merge DML button) or the
command line.
To access the mergedml utility from the command line, enter the following command.
mergedml <library_filename>... -o name
Table 3-5 Mergedml Arguments
Argument
Function
library_filename Names one or more device model libraries to be combined.
Names the merged output library.
-o
Protecting Device Model Libraries
Use the dmlcrypt program to produce encrypted versions of DML files to protect model data.
Models in encrypted files may be used for simulation, but they may not be viewed in plain text,
cloned or altered. The program requires the name of an existing DML file and the name of a
new encrypted DML file to write. For example:
dmlcrypt devices.dml devices_e.dml
An encrypted copy of devices.dml will be saved as devices_e.dml.
Caution
Once a file is encrypted there is no way to convert it back to plain text, so
be careful to retain a copy of the original plain text DML file.
For further protection, add a SPICE comment to your ESPiceDevice, MacroModels or
PackageModels as follows:
*|protect_simulation_files: comps.spc ibis_models.inc
Doing so will cause these simulation files to be removed at simulation ensuring that no plain
text copy of your data remains.
An encrypted DML file can be recognized by the characters at the beginning:
FILE_FMT=SYENCRYPT2
&<qpBi#48tk]OzP):^"7)[C ...
The remainder of the file contains undecipherable binary characters.
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Using Dmlcheck to Check Device Libraries
Use the dmlcheck utility to check the syntax of one or more library files.
You can access the dmlcheck utility from the SPECCTRAQuest Floorplanner or Allegro/
APD main menu or the command line.
To access dmlcheck from within the SPECCTRAQuest Floorplanner or Allegro/APD ,select
one of the options shown in the following figure.
The Open File dialog box appears from which you can select either a single or a list of device
model libraries to be checked. Once this selection is made, dmlcheck will scan the library
file(s) for any syntax errors. When the check is complete, a dmlcheck log report with
messages indicating the syntactical condition of the file(s) is displayed.
A sample log report is shown in the following figure.
Figure 3-1 Sample Log Report
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To access dmlcheck from the command line, enter the dmlcheck command with the
following arguments:
dmlcheck [options] <library_filename>...
Table 3-6 Dmlcheck Options
Option
Description
-bufferdelay
Calculates the buffer delay for the pins of each IbisDevice
checked. The dmlcheck -o option is required for BufferDelay
calculation, so that the results will be saved.
-curvedir directory
The -bufferdelay option can also be used with
quad2signoise and ibis2signoise. Progress
messages will be printed while calculations take place.
Creates the specified directory into which each VI and VT
curve creates a SigWave waveform file.
-o extension
Writes the library data, as transformed by dmlcheck, to
fnj.extension for each input file fnj.
-version
Displays the version of the software in the output.
library_filename
Specifies one or more device model libraries to be checked.
Command Line Examples
The following example checks a group of library files. The dmlcheck utility will print any
warnings.
dmlcheck *.dml
The following example checks a group of files. The dmlcheck utility will print any warnings,
and write converted (curve) data into files with the extension .new.
dmlcheck -o new *.dml
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Signal Integrity Model Libraries
The Cadence Default Library
The models in the Cadence Default Library fall into three categories:
■
DIG_LIB Library Models
Standard digital logic families containing 217 unique parts in a format directly compatible
with the SigNoise simulator with their corresponding IBIS files. These models have been
made from spice files from Signetics (except for one device).
■
DEFAULT_LIB Library Models
Default set of IOCell models for gtl, pci, and asic types. You can use these IOCell models
to select the right buffer for a given application.
■
PACKAGES Library Models
Library Structure
The Cadence Default Library is in the install directory. The path to the standard install
directory is:
/cds/share/pcb/signal/SignalPartLib
The directory contains the following sub-directories corresponding to the three categories:
■
DIG_LIB
Contains subdirectories corresponding to four digital logic families. Each digital logic
family subdirectory contains files for IBIS Device models and IOCell models (.dml files).
There is one device model in each file. The corresponding IBIS files (.ibs files) also
exist. There is one DIGlib_assump.txt file giving the test setups used to validate
each family.
■
DEFAULT_LIB
Contains signoise .dml files and their corresponding .ibs files. The corresponding
assumption.txt file lists the assumptions, approximations and validation test setup
used.
■
PACKAGES
Note: In the directory above the SignalPartLib directory, SigNoise uses the device
model index file cds_partlib.ndx to quickly load groups of models.
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The DIG_LIB Library Models
The digital device model library supports models for parts from four types of digital logic
families (or technologies). A part’s digital logic family refers to the different processes and
implementations used in the manufacture of the parts used in integrated circuits. For
example, you can use bipolar transistor-transistor-logic, CMOS, bipolar emitter coupled logic,
or a combination of several technologies.
Each technology has different input and output parameters. The library includes the digital
logic families in the following table
.
Table 3-7 Digital Device Model Library
Technology Description
ABT
Advanced BiCMOS Technology for bus interfaces with high drive, lower
power consumption and fast propagation
ALS
Advanced Low Power Schottky for low power consumption in non-speed
critical circuits
ALVC
Advanced Low Voltage CMOS for low power consumption
FTTL
Fast Transistor-Transistor Logic for speed critical circuits
The DEFAULT_LIB Library Models
The following table describes the default set of library models
Table 3-8 Default Library Models
Technology
Number of
Description
IOCell Models
GTL
01
IOCell models derived from Texas gtl spice files.
PCI
04
Compatible IOCell models for both 3v and 5v derived
from Intel pci spice files.
ASIC
22
IOCell models for different current capability both for 3v
and 5v; with and without slew made from suitable
approximations for the ASIC CMOS technology.
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The PACKAGES Library Models
The default package models include:
■
20dip
■
14soic
■
16soic
■
20soic
■
16ssop
■
20ssop
■
28plcc
■
44plcc
For a complete list of models, refer to the share/pcb/signal/cds_partlib.ndx file.
You can search this file using the UNIX grep command or the Windows NT Find command.
For additional information on using the Cadence Default Library, see Appendix C, “The
Cadence Default Model Library.”
Standard Libraries
There are four separately licensable signal integrity model libraries available for use with
SigNoise. They contain Simulator-compatible models for over 9,800 unique parts.
The digital logic SI library
The memory SI library
The FPGA SI library
The microprocessor SI library
These libraries are available for purchase and require a separate license. They are available
for Unix and Windows NT. For additional information on setting up and using these libraries,
see Appendix D, “SPECCTRAQuest Standard Signal Integrity Libraries.”
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4
Developing Simulation Models
■
“Introduction to Simulation Models” on page 72
■
“Basic Model Development” on page 74
■
“The Model Browser” on page 74
■
“Creating Models and Adding Them to a Working Library” on page 76
■
“Model Setup in Concept or Third-Party Libraries” on page 78
■
“Advanced Model Development” on page 79
■
“Editing IBIS Device Models” on page 79
■
“Editing IBIS IOCell Models” on page 99
■
“Editing ESpice Device Models” on page 112
■
“Editing PackageModels” on page 112
■
“Editing Cable Models” on page 113
■
“Editing Analog Output Models” on page 113
■
“Editing and Regenerating Interconnect Models” on page 116
■
“Model Audit” on page 123
■
“Managing Models in a Design” on page 117
■
“Translating Models to DML” on page 126
■
“Translating ESpice files to Generic Spice Formats” on page 127
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Introduction to Simulation Models
You can use there are two basic categories of models used to build circuits for simulation:
■
Device models
■
Interconnect models
Device models are developed in advance of simulation, and you use them to characterize
manufactured components such as ICs, discrete components, and connectors. They are
stored in files with a .dml extension. A device model library consists of a .dml file that
contains one or more device models.
Interconnect models are extracted directly from the physical design database and
synthesized on demand. Interconnect models cover such items as traces and vias, and are
stored in files with an .iml extension.
The Cadence Sample Model Libraries
The simulation models are stored in device and interconnect model libraries. The Cadence
sample device model libraries are in the install directory. The path is as follows:
/install_dir/share/pcb/signal/cds_*.dml
Look at this file for details of the format and syntax of device models as well as the structure
of a device model library. The libraries contains\ commented examples of the different types
of device models.
Available Models
The following tables describe the available device and interconnect models, including their
contents and how they are used.
Table 4-1 Available Device Models
Model Type
Use and Relationship
IbisDevice
Assigned to ICs and connectors with the SIGNAL_MODEL property.
(An IbisDevice model for a connector has package parasitics but no
IOCell models.)
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Table 4-1 Available Device Models
Model Type
Use and Relationship
IbisIOCell
Referenced from an IBISDevice model. Used to model driver and
receiver buffers at the pin level. The different types of IOCell models
are:
IbisOutput -- Driver model.
IbisOutput_OpenPullUp -- Driver model with no pullup transistor.
IbisOutput_OpenPullDown -- Driver model with no pulldown
transistor.
IbisInput -- Receiver model.
IbisIO -- Bidirectional buffer model, which can drive or receive.
IbisIO_OpenPullUp -- Bidirectional buffer model with no pullup
transistor.
IbisIO_OpenPullDown -- Bidirectional buffer model with no pulldown
transistor.
AnalogOutput -- Models the behavior of an analog device pin.
IbisTerminator -- Models termination internal to the device pin.
PackageModel
Referenced from an IbisDevice model. Models the package parasitics
of the entire component package, can be an RLGC matrix model or
Spice sub-circuits.
ESpiceDevice
Assigned to discrete parts like resistors and capacitors with the
SIGNAL_MODEL property. Contains Spice sub circuits.
System
Configuration
Used to specify system-level connectivity, like multi-board or advanced
package-on-board scenarios.
Note: System configurations created prior to release 14.0 of
SPECCTRAQuest appear as DesignLink models.
Cable
Referenced from a system configuration. Models cables
interconnecting multiple boards. Can be a RLGC model or Spice subcircuits.
BoardModel
Referenced from a system configuration. Models entire boards for
situations in which the physical Allegro database is not available.
Contains Spice sub circuits.
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Table 4-2 Available Interconnect Models
Model Type
Use and Relationship
Trace
Geometry-based model that represents a single transmission line with
no coupling. Can have frequency-dependent loss.
MultiTrace
Geometry-based model representing multiple, coupled lossey
transmission lines. Can have frequency-dependent loss.
Shape
Models a copper shape encountered in a physical design.
Via
Models the parasitics of a via providing z-axis connectivity between
traces.
Use the Model Browser to create, display, manage, and edit the models in your libraries. The
Model Browser dialog box fuctions and basic model development tasks are discussed in the
following section. See Advanced Model Development on page 79 for information on using the
model editors and on performing more complex model development tasks.
Basic Model Development
The Model Browser
Basic model development tasks are handled through the use of the Model Browser.
To display the Model Browser from the SPECCTRAQuest Floorplanner or Allegro/APD:
1. Select Analyse>SI/EMI Sim>Library to display the Signal Analysis Library Browser.
2. Click Browse Models in the Library Browser dialog box.
For details, see Chapter 3, “Signal Analysis Library Browser.”
The Model Browser dialog box is displayed as shown in the following figure.
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Figure 4-1 Model Browser dialog box
Using the Model Browser you can perform the following basic model development tasks:
■
List the models in a library.
■
Create a device model with default values or clone an existing device model and add the
newly created model to the working library.
■
Delete a model from the working library.
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Displaying a List of Models
Filter fields at the top of the Model Browser control which models are displayed in the Model
Browser list box. You can specify which models are listed in the model search list by library,
by model type, or by characters in the model name.
The following table describes the Model Browser fields used to control the model list display.
Table 4-3 Model List Display Area
Option
Display
Function
Show Models
Currently selected device or
model library.
Changes the current device or library
(click arrow).
Model Type
Filter
Current model filter setting.
Changes the model filter to display only
models of a particular type (click arrow).
Model Name
Pattern
Current model name pattern
setting.
Changes the model name pattern string
to display only models whose name is
included in the specified character string
(edit type-in box).
Note: Use * for a wildcard selection.
ModelName
Name of the device model.
ModelType
Type of the device model.
Creating Models and Adding Them to a Working Library
You can add a device or interconnect model to the working device or interconnect model
library in either of two ways:
■
By copying (or cloning) an existing model.
■
By creating a new model with default values.
You must first create a device model and add it to the working library before you can edit it to
characterize a particular device.
To display a pop-up menu of models to add:
➤
Click Add Model in the Library area of the Model Browser dialog box.
A pop-up menu of options is displayed as shown in the following figure.
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Figure 4-2 Adding a Model
The following table describes the Add Model menu options.
Table 4-4 Model List Display Area
Option
Action
Clone Selection
Copies the selected model from the list box and adds the clone to the
working library. You specify the name the clone.
EspiceDevice
Displays the Create ESpice Device Model dialog box.
IBISDevice
Displays the Create IBIS Device Model dialog box.
PackageModel
thru BoardModel
Opens an empty file that you must edit to create the specified model,
which then is added to the working library.
Note: When a new device model is added to the working library, the library check program
(dmlcheck) verifies the validity of the entry.
Deleting a Model
Use Delete Model to remove the model previously selected from the model list box.
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Model Setup in Concept or Third-Party Libraries
You specify the model setup for components in Concept libraries. When SigNoise finds that
a component has no SIGNAL_MODEL property, it checks to see if it has a SIGNAL_MODEL
property on the device definition. You can attach SIGNAL_MODEL properties to device
definitions by setting the SIGNAL_MODEL property in one of the following:
■
the chips_prt file for that device
■
the phys_prt.dat file for your schematic
■
the Allegro device file (if you are using netin)
The value of the SIGNAL_MODEL property must be the name of an IBISDevice or
ESpiceDevice model. Furthermore, SigNoise validates all model assignments based on the
PINUSE property.
The SIGNAL_MODEL property assigned to components using the Signal Model Assignment
dialog box (instances) will override those in the device definition, if they exist.
SigNoise uses the following precedence to determine which model gets assigned to a device:
1. An instance-specific SIGNAL_MODEL assignment made in the Signal Model
Assignment dialog box (stored in the .brd file)
2. A SIGNAL_MODEL property on the component definition (Concept’s PPT file)
3. A VOLT_TEMP_MODEL property on the component definition (Concept’s PPT file)
4. A DEFAULT_SIGNAL_MODEL property on the component definition (Concept’s PPT
file)
A common use of the DEFAULT_SIGNAL_MODEL property is to establish a model name for
the device before the actual model is developed. SigNoise will warn you when a part with a
SIGNAL_MODEL property does not have an associated model; however, with the
DEFAULT_MODEL_NAME property attached to a part, SigNoise will not report an error when
a model is not yet available.
You could use the DEFAULT_MODEL_NAME property as a placeholder for a to-be-procured
library of models or for implementing model names based on your internal model naming
conventions.
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Advanced Model Development
Editing IBIS Device Models
You can edit any existing IBIS device model (except Cadence default models) that has been
created and added to a library. If you create the model by cloning (copying) an existing model,
you need to edit the cloned model so that it characterizes the device you are modeling. If you
create the model from scratch, it contains default values that you may want to edit. See
“Introduction to Simulation Models” on page 72 for information on creating device models and
adding them to a library. See the SigNoise online help for detailed procedures.
IBIS device models are modified using the IBIS Device Model Editor.
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Figure 4-3 The Model Browser
To display the IBIS Device Model editor, double-click on the model name or perform the
following steps:
1. Select an IBIS device model from the Model Browser list box.
If necessary, see “To display the Model Browser from the SPECCTRAQuest
Floorplanner or Allegro/APD:” on page 74for assistance.
2. Click Edit.
The IBIS Device Model Editor dialog box is displayed as shown in the following figure.
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IBIS Device Model Editor
The IBIS Device Model Editor dialog box contains three tabs that you can use to perform the
following tasks.
■
Edit information for the pins associated with the IBIS device model.
■
Group power and ground pins and assign them to power and ground buses.
■
Group signal pins and assign IOCell models and IOCell supply buses.
Figure 4-4 IBIS Device Model Editor - Edit Pins Tab
Edit Pins Tab
Use this tabbed page of the IBIS Device Model Editor to:
■
Specify package model parasitics for the device.
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■
Specify estimated pin parasitics for the device in terms of minimum, typical, and
maximum values for resistance, capacitance, and inductance for the package.
■
Add or modify pin data including individual pin parasitics and buffer delays.
■
Measure buffer delays.
■
Add, edit, or display buffer delay information.
■
Set wire numbers.
Tab Options and Buttons
The following tables describe the command options and buttons in the different areas of the
Edit Pins tab.
.
Table 4-5 Model Info Area
Option
Function
Model Name
Name of the IBIS device model.
Manufacturer
Name of the model manufacturer (not used by SigNoise).
Package Model
Name of a package model associated with the IBIS device model.
Table 4-6 Estimated Pin Parasitics Area
Option
Function
Resistance
Minimum, typical, and maximum values for resistance.
Capacitance
Minimum, typical, and maximum values for capacitance.
Inductance
Minimum, typical, and maximum values for inductance.
Note: See Guidelines on Specifying Parasitic Values for additional information. These values
are used for pins that have no individual pin parasitics (when the IBIS Device model has no
assigned PackageModel)
.
Table 4-7 IBIS Pin Data Area
Option
Function
Pin
The pin number.
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Table 4-7 IBIS Pin Data Area
Option
Function
Signal
The signal associated with the pin.
IOCell
The associated IOCell model.
Resistance
The resistance, if you are using individual pin parasitics.
Capacitance
The capacitance, if you are using individual pin parasitics.
Inductance
The inductance, if you are using individual pin parasitics.
DiffPair Mate
The inverse pin, if the pin is part of a differential pair.
Wire
The wire number, which determines which wire of the PackageModel
is used for this pin.
Use the IBIS Pin Data area to view and edit the data, including buffer delays, for each pin
associated with the IBIS device model. Pins are listed by wire number order. Pins with no wire
number are listed in alphanumeric order.
When you select a pin in the list box, the IBIS Device Pin Data dialog box appears displaying
data for that pin. For details, see “Adding or Editing Data for a Pin” on page 92
.
Table 4-8 Edit Pins Command Buttons
Button
Function
Add Pin Data
Prompts for the name of a new pin to add, and displays the IBIS
Device Pin Data dialog box to add or modify data including buffer
delays for a new pin.
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Table 4-8 Edit Pins Command Buttons
Button
Function
Measure Delays
Measures buffer delays by simulating each pin with the proper test
load. On pins with a Model Selector assigned, budderdelays are
simulated for each selectable IOCELL. If you use a Package Model,
you must perform simulations for each driver pin. Otherwise, pins
with identical parasitics and IOCELL assignments will share
simulation data. A progress meter displays the status of the process
for buffer delay simulations, especially for complex parts. You can
click the Stop button to cancel the simulation.
Options:
Unmeasured Drivers - creates data for drivers not previously
processed.
All Drivers - creates data for all drivers, refreshes previously
processed data.
Set WireNumbers Sets the wire number for each pin based on a sort criteria.
Options:
Order by Pin Name - Pins are sorted by pin name. Wire numbers
are assigned numerically starting at one. Alphabetic and numeric
portions of names are separately considered so that, for example, A2
appears before A10 and B6.
Order by IOCell Name - Pins are sorted first by IOCell model
name. Second, pins with the same IOCell model assigned are sorted
by pin name. Wire numbers are then assigned numerically starting at
one.
Note: After the wire numbers have been set, the pin list is displayed
in wire number order.
DML Check
Runs the dmlcheck utility on the model being edited and displays the
result in a text window.
OK
Runs dmlcheck before saving the model data and displays the result
in a text window. If errors are detected, you will be asked whether to
save the model anyway. A No response leaves the IBIS Device Editor
open.
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Assign Power/Ground Pins Tab
Use this tab to group the power and ground pins of a device into named power and ground
buses.
Figure 4-5 IBIS Device Model Editor - Assign Power/Ground Pins Tab
Tab Areas and Buttons
The following tables describe the data fields and command buttons in the different areas of
the Assign Power/Ground Pins tabbed page. The Pinuse, NetName, and CD Voltage
columns show data only when you invoke the IBIS Device Editor by clicking the Edit Model
button in the Signal Model Assignment form to open a populated design.
Table 4-9 All Pins Area Options
Option
Function
Pin #
The pin number.
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Table 4-9 All Pins Area Options
Option
Function
Bus Name
Any power bus or ground bus currently assigned to the pin. This
column is blank for a pin that is not currently assigned to a bus.
Pinuse
The pinuse code. UNSPEC indicates that no pinuse is assigned.
(This information displays only when you have invoked the IBIS
Device Model Editor for a specific instance of a device selected in
the Model Assignment dialog box.)
Net Name
The name of any net connected to the pin. This column is blank
when you are editing a model selected from a library. This column
displays a net name when you are editing a model associated
with a device that exists in the active design. (This information
displays only when you have invoked the IBIS Device Model
Editor for a specific instance of a device selected in the Model
Assignment dialog box.)
DC Voltage
The value of the Voltage property on any net attached to the pin.
This column is blank when the net has no Voltage property or the
pin is not attached to a net. (This information displays only when
you have invoked the IBIS Device Model Editor for a specific
instance of a device selected in the Model Assignment dialog
box.)
Nets Shown for
Component
The RefDes for the device associated with the model being
edited. (This information displays only when you have invoked the
IBIS Device Model Editor for a specific instance of a device
selected in the Model Assignment dialog box.)
Table 4-10 All Pins Area Buttons
Button
Function
Auto Assignment
Assigns individual pins not currently assigned to a bus and having a
pinuse of power or ground or a DC voltage defined to individual
power or ground buses.
Sort By
(column buttons)
Selects one of the columns on which to sort the data.
Sort By:
Pins can be sorted by using pin#, BusName, PinUse, NetName, or
DC Voltage.
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Table 4-10 All Pins Area Buttons
Button
Function
Filters:
(pulldown menu)
Filters the information displayed in the column. Initially the field
contains an asterisk (*) so that all data is displayed.
Bus Name lists existing buses.
Pinuse lists existing pinuse codes.
Select All
Selects all pins currently displayed in the All Pins list box and
redisplays them in the Selected Pins list box.
Deselect All
Deselects all pins currently selected and clears the All Pins list box.
Deselect One
Deselects one pin in the All Pins list box.
Table 4-11 Selected Pins Area Options
Option
Function
Pin #
The pin number for pins selected from the All Pins list box.
Bus Name
The bus name for pins selected from the All Pins list box.
Bus Name
(entry field and
pulldown menu)
Enter the bus name to be assigned or select an existing bus name
from the menu.
Table 4-12 Selected Pins Area Command Buttons
Button
Function
Assign as Power
Bus
Assigns all pins listed in the Selected Pins list box to the power
bus named in the Bus Name field. The pins become power pins.
Assign as Ground
Bus
Assigns all pins listed in the Selected Pins list box to the ground
bus named in the Bus Name field. The pins become ground pins.
Deassign
Deassigns all pins listed in the Selected Pins list box from the
power or ground bus named in the Bus Name field and deletes
the bus name.
DML Check
Runs the dmlcheck utility on the model being edited and displays
the result in a text window.
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Table 4-12 Selected Pins Area Command Buttons
Button
Function
OK
Runs dmlcheck before saving the model data and displays the
result in text window. If errors are detected, you will be asked
whether to save the model anyway. A No response, leaves the
IBIS Device Editor open.
Assign Signal Pins Tab
Use this tab to group the signal pins of a device and assign a power or ground bus name or
an IOCell model to the group.
Figure 4-6 IBIS Device Model Editor - Assign Signal Pins Tab
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Tab Options and Buttons
The following tables describes the command options and buttons in the different areas of the
Assign Signal Pins tab.
.
Table 4-13 All Pins Area Options
Option
Function
Pin #
The pin number.
IOCell
Any IOCell model currently assigned to the pin.
Power Bus
Any power bus currently assigned to the pin. This column is blank for
a pin that is not currently assigned to a power bus.
Ground Bus
Any ground bus currently assigned to the pin. This column is blank for
a pin that is not currently assigned to a ground bus.
Pinuse
The pinuse code. UNSPEC indicates that no pinuse is assigned.
Net Name
The name of any net connected to the pin. This column is blank when
you are editing a model selected from a library. This column displays
a net name when you are editing a model associated with a device
that exists in the active design.
Nets Shown for
Component field
The RefDes for the device associated with the model being edited.
This occurs when you invoke the IBIS Device Model Editor for a
specific instance of a device selected in the Model Assignment dialog
box.
Sort By
(column buttons)
Selects one of the columns on which to sort the data.
Sort By
(pulldown menus)
Filters the information displayed in the column. Initially the field
contains an asterisk (*) so that all data is displayed.
The Power Bus menu lists existing power buses.
The Ground Bus menu lists existing ground buses.
The Pinuse menu lists existing pinuse codes.
Table 4-14 All Pins Area Buttons
Button
Function
Select All
Selects all pins currently displayed in the All Pins list box and redisplays them in the Selected Pins list box.
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Table 4-14 All Pins Area Buttons
Button
Function
Deselect All
Deselects all pins currently selected and clears the All Pins list box.
Deselect One
Deselects one pin in the All Pins list box.
Table 4-15 Select Pins Area Options
Option
Function
Assign/Deassign Assigns or deassigns the group of pins listed in the Selected Pins list
buttons
box to the IOCell model, power bus, or ground bus named in the
associated field.
Pin #
The pin number for pins selected from the All Pins list box.
IOCell
The IOCell model assigned for pins selected from the All Pins list
box.
Power Bus
The power bus name for pins selected from the All Pins list box.
Ground Bus
The ground bus name for pins selected from the All Pins list box.
IOCell
Browse
(field and button)
Enter the IOCell model name to be assigned to the group of pin or
click Browse to display the Model Browser and select an IOCell model
there.
Power Bus
(field and menu)
Enter the power bus name to be assigned to the group of pins or
select an existing power bus name from the menu.
Ground Bus
(field and menu)
Enter the ground bus name to be assigned to the group of pins or pick
an existing ground bus name from the pull down menu.
Table 4-16 Select Pins Area Buttons
Button
Function
DML Check
Runs the dmlcheck utility on the model being edited and displays the
result in a text window.
OK
Runs dmlcheck before saving the model data and displays the result
in text window. If errors are detected, you will be asked whether to
save the model anyway. A No response, leaves the IBIS Device Editor
open.
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Guidelines for Specifying Parasitic Values
Parasitic values for an IBIS device can be represented with differing levels of detail.
■
Estimated pin parasitics are the most general.
Estimated pin parasitic values are defined globally for the package. The same set of
resistance, inductance, and capacitance values is used for all pins on the device.
Estimated pin parasitics consist of minimum, typical, and maximum values for package
resistance, inductance, and capacitance. See Specifying Estimated Pin Parasitics for
instructions.
■
Individual pin parasitics are more specific.
Individual package resistance, inductance, and capacitance values are defined on a pinby-pin basis. When they are supplied, these individual pin parasitic values override
estimated pin parasitic values, if any exist. See Specifying Parasitic Values for Individual
Pins for instructions.
■
Package model parasitics are most specific.
A detailed RLGC that can specify mutual coupling is defined for the entire package.
Optionally, a package model can contain an arbitrary passive Spice circuit. When a
package model is present, it takes precedence over both estimated and individual pin
parasitic values, if any exist. See Specifying Package Model Parasitics for instructions.
Specifying Parasitics
To specify parasitics for an IBIS device, first select the Edit Pins tab of the IBIS Device Model
Editor dialog box.
Specifying Estimated Pin Parasitics
Use the Estimated Pin Parasitics area of the Edit Pins tab to enter minimum, typical, and
maximum values for resistance, capacitance, and inductance. Delete any listed package
model from the Package Model field in the Model Info section of the Edit Pins tab. See the
online help for the IBIS Device Model Editor for detailed instructions.
Specifying Package Model Parasitics
Use the Package Model area of the Edit Pins tab to specify a package model for the IBIS
device model. Select a package model name in the Model Browser or click the Package
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Model field and type the package model name. See the online help for the IBIS Device Model
Editor for detailed instructions. See the SigNoise online help for detailed instructions.
Note: SigNoise uses this specified package model in the simulation circuit model of the
layout and will ignore any values in the Estimated Pin Parasitics fields. Also, ensure that
you remeasure buffer delays after changing parasitics.
Adding and Changing Pin Definitions
The IBIS Device Model Editor contains a list box that displays the pins in the device and
describes the data defined for each. For example, the pin’s IOCell model and parasitics. From
the IBIS Device Model Editor, you can display the IBIS Device Pin Data dialog box to:
■
Add or edit data (including individual pin parasitics) for the pins in the IBIS device model .
■
Add or edit buffer delay information for the pins in the IBIS device model. See “Adding or
Editing Buffer Delay Data for a Pin” on page 95.
Adding or Editing Data for a Pin
To display the IBIS Device Pin Data dialog box with data for a specified pin.
➤
Click to select the pin in the IBIS Pin Data list box in the IBIS Device Model Editor.
To display data for a different pin.
➤
Click to select another pin in the IBIS Pin Data list box. The IBIS Device Pin Data dialog
box changes to display data for that pin.
To display the IBIS Device Pin Data dialog box and add data for a new pin.
➤
Click Add Pin Data on the Edit Pins tabbed page and specify the pin name.
See the online help for the IBIS Device Model Editor and the IBIS Device Pin Data dialog
boxes for detailed instructions.
The following figure shows the IBIS Device Pin Data dialog box.
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Figure 4-7 IBIS Device Pin Data dialog box
Dialog Box Options and Buttons
The following tables describe the command options and buttons in the different areas of the
IBIS Device Pin Data dialog box
.
Table 4-17 IBIS Pin Map Area Options
Option
Function
Pin
The pin whose data is displayed.
Signal
The signal associated with the pin. Pins with an NC signal are not
connected. You can ignore these pins in the IBIS Device Model
Editor.
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Table 4-17 IBIS Pin Map Area Options
Option
Function
Resistance
The Individual Pin Parasitic values for the pin (if you are not using a
package model).
Capacitance
Inductance
Wire Number
The wire number for the pin. (This can be the same as the pin
number if numeric.) Wire numbers specify the wire numbers for the
package model and are used only for IBIS device models that have a
package model.
IOCell
The IOCell model associated with the pin. Pins with an NC model are
not connected. You can ignore these pins in the IBIS Device Model
Editor.
If you want to view the voltage versus current (V/I) curves for an
IOCell model before you assign it to a pin as part of the IBIS device
model, open the model in the IOCell Editor and use the View VI
button.
Note: Whenever you have made changes to the IOCell models for a
device, regenerate the buffer delay values for the device using All
Drivers mode.
Power Bus
Name of the power bus.
Power Clamp Bus
Name of the power clamp bus.
Ground Bus
Name of the ground bus
Ground Clamp Bus
Name of the ground clamp bus.
Table 4-18 Diff Pair Data Area Options
Option
Function
Type
Identifies the pin listed in the Pin field as the Inverting or Non-inverting
pin of the differential pair.
When the Type field displays None, the pin identified in the Pin field is
not part of a differential pair.
Mate Pin
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The name of the differential pair mate pin to the pin identified in the
Pin field.
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Table 4-18 Diff Pair Data Area Options
Option
Function
Launch Delay
Minimum, typical and maximum launch delay values for the pin, if it is
an Output or IO pin.
Input High
Minimum, typical and maximum differential logic threshold values.
Input Low
Output High
Output Low
Table 4-19 IBIS Device Pin Data Buttons
Button
Function
Buffer Delays
Displays the Buffer Delays dialog box that enables you to change the
buffer delay information for a pin. This dialog box contains the data that
SigNoise uses to calculate buffer delay values for rising and falling
drivers (output buffers).
Adding or Editing Buffer Delay Information
Use the Buffer Delays dialog box to add or edit buffer delay information for the IOCell models
associated with the pins in an IBIS device model.
Note: Whenever any IOCell model data changes, it is important to recalculate buffer delay
values in all drivers mode using either the Measure Delays in the Buffer Delays dialog box
or Measure Delays — All Drivers from the IBIS Device Model Editor.
Adding or Editing Buffer Delay Data for a Pin
To display the Buffer Delays dialog box for a specific pin.
➤
Click Buffer Delays on the Ibis Device Pin Data dialog box.
The following figure shows the Buffer Delays dialog box.
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Figure 4-8 Buffer Delays dialog box
Dialog Box Fields and Buttons
The following tables describe the command options and buttons in the Buffer Delays dialog
box.
.
Table 4-20 Buffer Delays Options
Option
Function
Test Fixture for
IOCell
Displays the IOCell for the pin and its related values as entered into
the Delay Measurement tab of the IOCell Editor. If the pin has more
than one selectable IOCell, you can select the IOCell to display with
the popup menu. Buffer delays are measured using each IOCell, and
stored separately.
Resistor
Capacitor
Term Voltage
Ref Voltage
Rise Delay
Fall Delay
Fast, Typical, and Slow values for rise and fall delay measured from
IOCell delay measurement information. Use these fields to edit output
buffer delay values directly.
See the online help for the IBIS Device Pin Data and Buffer Delays dialog boxes for detailed
instructions.
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Table 4-21 Buffer Delays Buttons
Button
Function
Edit IOCell
Starts IOCell Editor for the associated IOCell model where you can
edit test fixture values (resistor, capacitor, term voltage, and ref
voltage) and other IOCell model information. Test fixture values specify
the loading conditions under which SigNoise measures buffer delays.
Test fixture values are associated with the IOCell model for a pin rather
than with the pin itself.
Measure Delays
Refreshes the delay values if the IOCell model information has
changed: slow, typical, and fast buffer delay values for rising and falling
drivers. SigNoise performs the buffer delay measurements for only one
pin. (You can also measure buffer delays from the IBIS Device Model
Editor.)
Note: Whenever you have made changes to the IOCell models for a
device, regenerate the buffer delay values for the device using all
drivers mode.
More About Buffer Delays for an IBIS Device Model
When buffer delay values exist for the pins on an IBIS device, they are used to compensate
the switch and settle delay values that appear in reports. The pin’s associated buffer delay
value (rise/fall or fast/typical/slow) is subtracted from the absolute switch and settle delay
waveform measurements to produce the compensated switch delay and settle delay values.
Note: If no buffer delay values exist for a particular driver pin, the reported absolute switch
and settle delay values are left uncompensated.
When measuring buffer delay values for a device, SigNoise performs only one simulation set
for each group of pins having the same IOCell model, pin parasitics, and test fixture. Because
of the complex nature of package models, SigNoise always simulates all pins for any device
having an assigned package model.
Measuring Buffer Delay Values
In the IBIS Device Model Editor, click left on Measure Delays to display the delay
measurement options: Unmeasured Drivers and All Drivers.
■
Use Measure Delays – Unmeasured Drivers to calculate all six measured delay
values: slow, typical, and fast buffer delays for all rising and falling drivers that currently
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have no buffer delay values. In unmeasured drivers mode, SigNoise will reuse existing
simulation results, even from other devices, in order to maximize performance.
■
Use Measure Delays – All Drivers to calculate all six measured delay values: slow,
typical, and fast buffer delays for every rising or falling driver. These new values override
any previous buffer delay values that exist in the model. The new values are saved in the
buffer delay section for each driver. In all drivers mode, all delay values are re-measured.
Existing simulation results are not used. Use all drivers mode to regenerate buffer delay
values for a device whenever any changes are made to the IOCell models for that device.
These new values override any previous buffer delay values that exist in the model. The new
values are saved for each driver.
Using Buffer Delay Compensation
There are several ways to use buffer delay compensation.
■
Generate Reflection or Delay reports, which have buffer delay compensated switch and
settle time values.
■
Run the a2sdf wire delay extract utility with the -s option to produce compensated
wire delays. For details, see Chapter 5, “SDF Wire Delay Report.”
■
Examine switch and settle delay values using the SigXP results spreadsheet.
■
Create and examine compensated delay values for a driver using the IBIS Device Model
Editor.
If buffer delay values exist for a pin on an IBIS device, the delay values are extracted from the
library data for the pin’s IOCell model and subtracted from the simulated times of threshold
crossing delays to produce compensated first switch and final settle delays.
When buffer delay values do not exist for an IOCell model, no buffer delay is subtracted and
buffer delay appears in reports as 0.0.
Measuring Compensated Buffer Delay Values from the IBIS Device Model Editor
You can use the IBIS Device Model Editor to simulate, measure, and edit buffer delay values
and associated data for drivers associated with a selected IBIS Device model. See the online
help for Measuring Buffer Delays for detailed instructions.
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Editing IBIS IOCell Models
You can edit any existing IOCell model that has been created and added to a library. If you
created the model by cloning (or copying) an existing model, you need to edit the cloned
model so that it characterizes the device you are modeling. If you created the model from
scratch, it will contain default values that you may want to edit. See “Introduction to Simulation
Models” on page 72 for general information on creating device models and adding them to a
library. See the SigNoise online help for detailed procedures.
Note: Whenever any changes are made to the IOCell models for a device, regenerate the
buffer delay values for a device using all drivers mode. See “Adding or Editing Buffer Delay
Data for a Pin” on page 95 for more information.
IBIS IOCell models are modified using the IBIS IOCell Editor. Using the IOCell Editor you can
modify:
■
General information about the model.
■
High and low logic thresholds for an input buffer.
■
Rise and fall times and high and low logic thresholds for an output buffer.
■
Delay measurement test fixture data for the model.
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Figure 4-9 The Model Browser
To display the IBIS IOCell editor, doubleclick on the IOCell name, or perform the following
steps:
1. Select an IBIS IOCell model from the Model Browser list box.
2. Click Edit.
The IBIS IOCell Editor dialog box is displayed as shown in the following figure.
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Figure 4-10 IOCell Editor - General Tab
General Tab
Use this tab of the IOCell Editor to perform the following tasks.
■
List the name, model type, and technology family of the IOCell model you are editing.
■
Access the V/I curve editors.
Tab Options and Buttons
The following tables describe the command options and buttons on the General tab.
Table 4-22 General Tab Options
Option
Function
Name
The name of the model.
Type
The type of model.
Technology
Displays a pop-up menu of technologies. Choices are CMOS, TTL,
and ECL.
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Table 4-22 General Tab Options
Option
Function
V/I Curves
Starts V/I curve editor for PowerClamp or GroundClamp.
Die Capacitance Minimum, typical, and maximum values for die capacitance.
Reference
Temperature
Minimum, typical, and maximum reference temperatures.
.
Table 4-23 General Tab Buttons
Button
Function
Power Clamp
Starts V/I Curve Editor for Power Clamp.
Ground Clamp
Starts V/I Curve Editor for Ground Clamp.
View VI
Displays the minimum, typical, or maximum VI curve.
General Tab Usage Notes
■
You can verify the minimum, typical, and maximum values for the die capacitance in the
IBIS data file, the die capacitance values are listed under c_comp.
■
The reference temperature is typically 50 degrees, with a minimum of 0 degrees and a
maximum of 100 degrees. The voltage and current values for the Power Clamp, Ground
Clamp, Pull Up, and Pull Down VI curves that you enter elsewhere in the IOCell editor
correspond to the reference temperature you enter here.
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Input Section Tab
Use this tab to enter high and low thresholds for voltage-in.
Figure 4-11 IOCell Editor - Input Section Tab
Tab Options and Buttons
The following tables describe the command options and buttons on the Input Section tab.
Table 4-24 Input Section Options
Option
Function
Logic Thresholds Minimum, typical, and maximum values for high and low input
thresholds.
Table 4-25 Input Section Buttons
Button
Function
View VI
Displays the minimum, typical, or maximum VI curve.
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Output Section Tab
Use this tab to enter minimum, typical, and maximum voltage and time delta values for rise
and fall slew rate. You can also access the VI and VT curve editors from this tab.
Figure 4-12 IOCell Editor - Output Section Tab
Tab Options and Buttons
The following tables describe the command options and buttons on the OutputSection tab.
Table 4-26 Output Section Options
Option
Function
Ramp (20%/
80%)
Minimum, typical, and maximum dV and dT values for rising and falling
slew rates.
V/I Curves
Starts the VI curve editor to examine Pull Up or Pull Down VI curves.
V/T Curves
Starts the VT curve editor to examine Rising Wave and Falling Wave
VT curves.
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Table 4-27 Output Section Command Buttons
Button
Function
View VI
Displays the minimum, typical, or maximum composite VI curves.
Output Section Tab Usage Notes
■
Use the Rise Slew dV and dT fields and the Fall Slew dV and dT fields to specify
minimum, typical, and maximum values for ramp rates associated with the IOCell model.
By IBIS convention, the ramp rate values (the dV/dT values or slew rates) are required
to be 20%/80% values. This implies that the rise time and the fall time are defined as the
time it takes the output buffer to go from 20% of its final value to 80% of its final value.
The dV value represents the difference between 20% and 80% of the actual voltage
swing. The dT value is the actual time taken for the 20%/80% voltage swing.
Ramp rate values must also be correctly categorized as minimum, typical, and maximum
slew rates. The minimum value is the slowest slew rate and the maximum value is the
fastest.
■
■
Use PullUp and PullDown to start a VI Curve Editor and enter high and low output
voltage and current data point values
❑
PullUp–High state V/I curve
❑
PullDown–Low state V/I curve
The View VI button displays the following curves in SigWave:
❑
Sum of Pullup, PowerClamp, and GroundClamp (hidden)
❑
Sum of Pulldown, PowerClamp, and GroundClamp (hidden)
❑
Pullup
❑
Pulldown
❑
PowerClamp
❑
GroundClamp
The Pullup and PowerClamp curves are offset on the voltage scale by the respective
Reference Voltage. For a 3.3V part, for example, 1.0V on the Pullup curve is
summed at 3.3V - 1.0V = 2.3V on the curve display. The composite sum curves
are initially hidden in SigWave.
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■
Use Rise Wave and Fall Wave to start a VT Curve Editor and enter high and low output
voltage and time data point values
❑
Rise Wave–Rising V/T curve
❑
Fall Wave–Falling V/I curve
Delay Measurement Tab
This tab contains the test fixture data SigNoise uses when measuring buffer delays for rising
and falling drivers (output buffers).
Figure 4-13 IOCell Editor - Delay Measurement Tab
Tab Options and Buttons
The following tables describe the command options and buttons on the Delay Measurement
tab.
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Table 4-28 Delay Measurement Options
Option
Function
Test Fixture
Test fixture values for resistance, capacitance, and termination voltage.
V Measure
Reference voltage.
Table 4-29 Delay Measurement Command Buttons
Button
Function
View VI
Displays the minimum, typical, or maximum VI curve.
Defining Test Fixture Information for Delay Measurement
Use the Resistor, Capacitor, Termination Voltage and Reference Voltage fields to
modify the delay measurement test fixture values.
The test fixture values specify the loading conditions under which SigNoise measures buffer
delays. Note that the test fixture circuit illustrated in the folowing figure includes the package
parasitics for the specific pin being measured.
Figure 4-14 Delay Measurement Test Fixture Circuit
Vterm
Rterm
Vout
Cterm
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Editing V/I Curve Data
Depending on the behavior for which you intend to edit VI curve data, access the VI curve
editor from either the General and Output Section tabs of the IOCell Editor dialog box .
To display a VI curve editor:
➤
➤
From the General tab of the IOCell Model Editor, click
❑
PowerClamp to edit the V/I curve for a diode clamping high
❑
GroundClamp to edit the V/I curve for a diode clamping low
From the Output Section tab of the IOCell Model Editor, click
❑
PullUp to edit the high state V/I curve
❑
PullDown to edit the low state V/I curve
The V/I Curve Editor is displayed for the specified behavior. The following figure shows the
PowerClamp V/I Curve Editor dialog box.
Figure 4-15 V/I Curve Editor dialog box
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Dialog Box Options and Buttons
The following tables describe the command options and buttons in the Buffer Delays dialog
box.
Table 4-30 V/I Curve Editor Options
Option
Function
Reference
Voltage
Minimum, typical, and maximum reference voltages for the IOCell
model.
V/I Convention
Specified format (Databook or IBIS). In Databook mode, the IBIS
relative voltages are translated to absolute voltages, using the typical
Reference Voltage as gthe offset for Pullup and PowerClamp curves.
Voltage
Voltage of the curve point.
Min I
Minimum tolerance of the curve point in mA.
Typ I
Typical tolerance of the curve point in mA.
Max I
Maximum tolerance of the curve point in mA.
Table 4-31 V/I Curve Editor Buttons
Button
Function
Add
Displays the Set V/I Curve Point dialog box enabling you to Add,
modify, or delete a curve point. See the following figure.
View
Displays a SigWave window showing minimum, typical, and maximum
curves.
Figure 4-16 Set V/I Curve Point dialog box
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Dialog Box Options and Buttons
The following tables describe the command options and buttons in the Set V/I Curve Point
dialog box
.
Table 4-32 Set V/I Curve Point Options
Option
Function
Voltage
Voltage of the curve point.
Min I
Minimum tolerance of the curve point in mA.
Typ I
Typical tolerance of the curve point in mA.
Max I
Maximum tolerance of the curve point in mA.
Table 4-33 Set V/I Curve Point Buttons
Button
Function
Delete
Deletes the selected line from the VI Curve Editor.
See the online help for the V/I Curve Editor, Set V/I Curve Point and SigWave for detailed
usage instructions.
Editing V/T Curve Data
An IOCell model can have any number of V/T curves. Each curve corresponds to one or more
measured waveforms for a given test fixture. SigNoise compares this test fixture data against
existing circuit conditions, analyzes the waveforms, and then adjusts the IOCell model’s
switching characteristic to mimic the measured waveforms as closely as possible.
You can access the V/T curve editor from the Output Section tab of the IOCell editor. To
display a V/T curve editor:
➤
From the Output Section tab of the IOCell Model Editor, click
❑
Rise Wave to edit the rising V/T curve
❑
Fall Wave to edit the falling V/T curve
The V/T curve editor is displayed for the specified VT curve. The following figure shows the
RisingWaveform V/T Curve Editor dialog box.
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Figure 4-17 V/T Curve Editor dialog box
Dialog Box Options and Buttons
The following tables describe the command options and buttons in the V/T Curve Editor
dialog box.
.
Table 4-34 V/T Curve Editor Data Fields
Option
Function
Test
Package (R, L,
C)
Resistance, delay, and capacitance for the test package.
V/T Curve
Test Fixture
(R, L, C) and
(Vmin, Vtyp,
Vmax)
Resistance, delay, and capacitance for the test fixture. The V/T test
fixture is the one that is used to generate the V/T curve data; not the
Delay Measurement test fixture.
Table 4-35 V/T Curve Editor Buttons
Button
Function
View
Display the curve in the SigWave window.
Import
Imports the AWB .wave file.
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V/T Curve Editor Usage Notes
■
Use the V/T Curve Test Fixture fields to modify the test fixture for the V/T curve. Select
a test fixture and edit the values.
■
Use View to open the SigWave window and display the waveform for a selected test
fixture.
The SigWave window is displayed with the waveform for the test fixture. See “Displaying
and Interpreting Waveforms” on page 219 for information on using the SigWave window.
■
Use Import to add a V/T curve from an AWB file to the IOCell model.
If the IOCell model you are editing does not have falling_waveform or rising_waveform
sections, you can import the waveform from a carefully designed AWB simulation.
Specify the path to the AWB wave file that contains the measured waveform and a name
for the text fixture.
Editing ESpice Device Models
You can edit any existing ESpice device model that has been created and added to a Library.
If you created the model by cloning (or copying) an existing model, you need to edit the cloned
model so that it characterizes the device you are modeling. If you created the model from
scratch, it will contain default values that you may want to edit. See “Introduction to Simulation
Models” on page 72 for information on creating device models and adding them to a library
Use Edit in the Model Browser to modify a selected ESpiceDevice model. Your default text
editor is opened with the contents of the ESpice model.
Editing PackageModels
You can edit any existing PackageModel that has been created and added to a Library. If you
created the model by cloning (or copying) an existing model, you need to edit the cloned
model so that it characterizes the device you are modeling. If you created the model from
scratch, it will contain default values that you may want to edit. See “Introduction to Simulation
Models” on page 72 for information on creating device models and adding them to a library.
Use Edit in the Model Browser to modify a selected PackageModel. Your default text editor
is opened with the contents of the PackageModel.
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Editing Cable Models
You can edit any existing cable model that has been created and added to a Library. If you
created the model by cloning (or copying) an existing model, you need to edit the cloned
model so that it characterizes the device you are modeling. If you created the model from
scratch, it will contain default values that you may want to edit. See “Introduction to Simulation
Models” on page 72 for information on creating device models and adding them to a library.
Use Edit in the Model Browser to modify a selected cable model. Your default text editor is
opened with the contents of the cable model.
Editing Analog Output Models
You can edit any existing analog output IOCell model that has been created and added to a
library. If you created the analog output model by cloning (or copying) an existing model, you
need to edit the cloned and renamed copy so that it characterizes the device you are
modeling. If you created the model from scratch, it will contain default values that you may
want to edit. See “Introduction to Simulation Models” on page 72 for information on creating
device models and adding them to a library.
An analog output model represents a driver pin on an analog device. In analog output models,
you specify Cadence Analog Workbench (AWB) wave files for rising and falling edges, pulses,
and inverted pulses to describe the behavior of the driver pin.
Analog Output models are modified using the Analog Output Model editor.
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Figure 4-18 The Model Browser
To display the Analog Output Model Editor:
1. Select an Analog Output model from the Model Browser list box.
If necessary, see “To display the Model Browser from the SPECCTRAQuest
Floorplanner or Allegro/APD:” on page 74.
2. Click Edit.
The Analog Output Model Editor dialog box is displayed as shown in the following figure.
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Figure 4-19 Anaolg Output Model Editor
Analog Output Model Editor
Using the Analog Output Model editor you can perforn the following tasks.
■
Use the Series Resistance field to specify a resistance value.
■
Use the Rise, Fall, Pulse, and Inv Pulse buttons and fields to specify the paths to one
or more AWB files and import the files. (Use the button with an empty field to display a
file browser.) SigWave displays the selected Analog Workbench file.
Analog Output Model Editor Options and Buttons
The following tables describe the command options and buttons on the Analog Model Editor.
Table 4-36 Analog Output Model Editor Options
Option
Function
Model
The name of the Analog Model.
Series Resistor
The resistance value for a series resistor.
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Table 4-37 Analog Output Model Editor Buttons
Button
Function
Rise
Specifies the path to an Analog Workbench file or displays a file
browser.
Fall
Specifies the path to an Analog Workbench file or displays a file
browser.
Pulse
Displays the path to an Analog Workbench file or displays a file
browser.
Inv Pulse
Displays the path to an Analog Workbench file or displays a file
browser.
Editing and Regenerating Interconnect Models
All interconnect models are written in the Interconnect Description Language (IDL).
To edit an interconnect model:
1. Click to select the interconnect model in the Model Browser list box.
2. Click TextEdit.
Your default text editor containing the interconnect model is displayed.
Once you have modified the geometry portion of an interconnect model using TextEdit, you
can regenerate the model’s electrical data using the Solve button on the Model Browser.
To regenerate an interconnect model:
1. Click to select the modified interconnect model in the Model Browser list box.
2. Click Solve.
The two-dimensional field solver runs the geometry for that model and writes a new
RLGC matrix into the model.
If you select a via model, the three-dimensional field solver is used. This creates a more
accurate model, but requires more computation time.
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Managing Models in a Design
For improved performance and design portability, device models used for signal integrity
analysis are stored directly in the design database (.brd file). Whenever you edit model
source within a Device Model Library (DML), you will need to refresh the design database in
order to incorporate your changes into the models within your current design.
Models are refreshed by searching DML files based on their pre-defined order in the SigNoise
library list. The first model of the same name and type that is found is used for the refresh.
This scheme allows you to move libraries or add new ones as desired.
When a model in the database is re-loaded from a DML, any Xnets that are affected by the
model are updated. Additionally, pin-use codes of all componenets affected by the refresh are
re-checked. If they are inconsistent with the new model, they are updated and a text window
is displayed with a report listing the pins whose pin-use codes were updated.
When required, device models in the current design can also be dumped to a new signal
integrity model library.
You may want to dump the models in order to:
■
Display the data for the device models in your design.
■
Generate a new DML to enable the portability of the device models (independent of the
design database) that are resident in the current design.
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Model Dump/Refresh Dialog Box
The Model Dump/Refresh dialog box contains functions which enable you to perform
verification and source management operations on the device models in your current design.
Upon display of the dialog box, models are checked against their source while a meter is
displayed showing the progress of the task. Upon completion of the check, a list box displays
a listing of all models resident in the current design.
To display the Model Dump/Refresh dialog box:
➤
Select the option shown in the following figure from the main menu of either the
SPECCTRAQuest Floorplanner or Allegro/APD .
The Model Dump/Refresh dialog box is displayed as shown in the following figure.
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Figure 4-20 The Model Dump/Refresh Dialog Box
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The following tables describe the Model Dump/Refresh dialog box command options and
buttons.
Table 4-38 Model Dump/Refresh Options
Options
Function
Signal
Model
A tree widget showing all models stored in the selected design or the
selected library. The models are grouped according to category. Categories
can be expanded to see model names.
Refresh
Source
The name of the DML (Device Model Library) containing the model. If the
message Not Found is displayed, the model cannot be found in the current
SigNoise libraries
Note: DML files are searched based on their pre-defined order in the
SigNoise library list.
Status
A current status message for the models based on an automatic source
check. See “About Model Status Messages” on page 121.
Table 4-39 Model Dump/Refresh Buttons
Button
Function
View
Differences
Invokes the generation of a Model Differences (line by line comparison)
report for the selected model in a pop-up window. See “View Differences”
on page 122.
Refresh
Causes the selected model in the current design to be overwritten by the
model data contained in its source when its Status field contains a number
greater than zero. This will take effect upon clicking either Apply or OK
Note: The button will be grayed out if a model is not selected or if the model
status is listed as Same.
Refresh All
Causes all the models in the current design that are different to be
overwritten by the model data contained in their corresponding source.
This will take effect upon clicking either Apply or OK.
Note: The button will be grayed out if no models in the current design are
different.
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Table 4-39 Model Dump/Refresh Buttons
Button
Function
Dump
Dumps (writes) all the device models in the current design to
boardname.dml/boardname_encrypted.dml. When the dump is
complete, a confirmer pop-up window is displayed with a message which
reads:
“Model dump finished. For Log messages see dump_libraries.log.”
OK
Applies all the changes made and closes the form.
Apply
Applies all the changes made in the form without closing the form. After
applying the changes a summary report is displayed to verify all the
changes. See “Model Refresh Summary” on page 121.
About Model Status Messages
There are two possible status messages that can appear against a device model in the Signal
Model window. They are described in the following table.
Table 4-40 Model Status Messages
Message
Meaning
Same
The code of the model resident in the current design is
identical to the source code of the model in the library.
Note: For all models from Cadence standard libraries and
Zeelan libraries (which users cannot change), the Status
field value will always be Same.
<integer> differences
There are <integer> differences between the code of the
model resident in the board and its source code within the
library shown in the Refresh Source field.
Reports
Model Refresh Summary
Through the use of the Refresh and Apply buttons in the dialog box, the models in the
current design can be refreshed individually and changes applied without having to close
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(OK) the form. When the Apply button is selected, a Model Refresh report displays providing
verification on the models refreshed thus far. The following figure shows a sample report.
Figure 4-21 Sample Model Refresh Report
View Differences
When the status of a device model is listed as an integer, there are differences between the
model code in the current design and its source. You can check these differences by first
selecting the model and then clicking View Differences on the Model Dump/Refresh dialog
box. The following figure shows a sample report.
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Figure 4-22 Sample View Differences Report
The report shows a line by line comparison of the differences between the selected model’s
data within the current design and its source. If no differences are detected, a message is
displayed
Model Audit
The dmlcheck Utility
Use the dmlcheck utility to check the syntax of one or more library files or models. There are
actually several ways to invoke dmlcheck. As you recall, the IBIS model editors have DML
Check buttons (see Edit Pins Command Buttons table on page 83) which enable you to check
the syntax of new models as they are created. You can check a group of libraries (.dml files)
using a command line entry. Also, in some cases, the dmlcheck utility is invoked
automatically, such as after assigning IOCell models from the Database Setup Advisor.
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Still another way to invoke dmlcheck is to use one of the following Library Audit options.
To check device model and library syntax:
1. Select one of the options (shown in the following figure) from the main menu of either the
SPECCTRAQuest Floorplanner or Allegro/APD. A file browser appears.
2. Select or enter the name of the library (.dml) or library list (.lst) file to be checked.
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Upon completion of the library syntax check, the dmlcheck message log window appears with
a description of any warnings or errors found with a library or model format. A sample log is
shown in the following figure.
In cases where dmlcheck has modified a curve to fix some problem, a confirmer pop-up is
displayed asking to overwrite the original library with the output from dmlcheck.
To check library syntax from the UNIX command line:
➤
At the operating system prompt, enter the dmlcheck command with the following
arguments:
dmlcheck [options] <library_filename>...
Table 4-41 dmlcheck Command Arguments
Options
Function
-bufferdelay
Calculate the buffer delay for each IBIS Device pin. You
must also specify the -o option with this option.
-curvedir
<directory>
Creates the specified directory into which each VI and VT
curve creates a SigWave waveform file.
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Table 4-41 dmlcheck Command Arguments
Options
Function
-o <extension>
Appends the specified extension to the output file created by
dmlcheck.
library_filename
One or more device model libraries to be checked.
The dmlcheck utility checks the syntax of each file in turn. It prints errors and warning
messages as necessary to standard text output and also reports when a file checks out okay.
Dmlcheck Command Line Examples
■
The following example checks all library files in the current directory.
dmlcheck *.dml
■
The following example checks all library files in the current directory, and writes
converted data into files with the .new extension.
dmlcheck -o new *.dml
■
The following example simulates to measure BufferDelay, which is stored in the .new
output file.
dmlcheck -bufferdelay -o new *.dml
■
The following examples creates a "curves" directory into which is placed a .sim waveform
file for each V/I and V/T curve.
dmlcheck -curvedir curves *.dml
Each waveform file contains the following curves:
❑
The minimum, typical, and maximum curves in the input file.
❑
The same three curves after dmlcheck fixing.
The files are named with the IOCell name and curve name, separated by an underscore.
For example, CDSDefaultIO_Pullup.sim. Use SigWave to view the curves.
Translating Models to DML
You can use translation utilities to translate models from third-party formats to dml files used
by SigNoise. The following table shows which translator to use for each third-party model
format supported by Cadence
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Table 4-42 Model Translation
Model Format to be Translated to DML
Translator to use
IBIS
ibis2signoise
QUAD
quad2signoise
See Appendix E, “IBIS to DML” or Appendix E, “QUAD to DML” for details on translating
models and for information regarding error and warning messages.
Translating ESpice files to Generic Spice Formats
You can use the spc2spc utility to read a named SigNoise netlist and generate Spice or
Spectre formated output files, with options to allow flattening, node renaming and ladder
network generation. An option to allow the generation of HSpice elements is also available.
Enabling this option also causes HSpice rlgc specification files to be written for each different
coupled transmission line topology.
See Appendix E, “Translating ESpice Files to Generic Spice Files,” for details on translating
ESpice files and for additional information regarding spc2spc translation rules.
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Analyzing for Signal Integrity and EMI
■
“Simulation Preferences and Parameters” on page 130
■
“Simulating for Signal Integrity and EMI” on page 147
■
“Analysis Results” on page 163
■
“Analyzing to Generate Text Reports” on page 163
■
“Standard Report Generation” on page 170
■
“Analyzing to Generate Waveforms” on page 214
■
“Conductor Cross Sections” on page 220
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Simulation Preferences and Parameters
Before analyzing a design for signal integrity and EMI, you should set up SigNoise to perform
simulation analysis according to your preferences.
To set simulation preferences:
➤
Select the option shown in the following figure from the main menu of either the
SPECCTRAQuest Floorplanner or Allegro/APD.
The Analysis Preferences dialog box is displayed as shown in the following figure.
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Figure 5-1 Analysis Preferences Dialog Box - Device Models Tab
Using this dialog box you can specify:
■
IOCell model defaults
■
Interconnect model defaults
■
Crosstalk specific defaults
■
Simulation mode defaults
■
EMI specific defaults
■
Default simulation units
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DeviceModels Tab
From the DeviceModels tab on the Analysis Preferences dialog box, you can determine
whether or not SigNoise will use a default IOCell model when it encounters a driver or
receiver pin without an associated IOCell model. You can further specify which IOCell model
SigNoise will use for six specific pinuse types: IN, OUT, BI, TRI, OCL, and OCA. Use Browse
Models to open the Model Browser set to display IOCell models. See the online help file for
more information.
Tab Options and Buttons
The following tables describe the command options and buttons in the different areas of the
Devices tab.
.
Table 5-1 DeviceModels Tab Options
Option
Function
Use Defaults
for Missing
When checked, SigNoise uses specified default models for devices
without specific model assignments. The default is checked.
Whenunchecked, simulations proceed only for nets with models
assigned for all components.
IN
Defines the default IOCell model for a pin with the PINUSE property
value of IN. The default is CDSDefaultInput.
OUT
Defines the default IOCell model for a pin with a PINUSE property
value of OUT. The default is CDSDefault Output.
BI
Defines the default IOCell model for a pin with a PINUSE property
value of BI. The default is CDSDefaultIO.
TRI
Defines the default IOCell model for a pin with a PINUSE property
value of TRI. The default is CDSDefaultTristate.
OCL
Defines the default IOCell model for a pin with a PINUSE value of
OCL. The default is CDSDefaultOpenDrain.
OCA
Defines the default IOCell model for a pin with a PINUSE value of
OCA. The default is CDSDefaultOpenSource.
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Table 5-1 DeviceModels Tab Options
Option
Function
Buffer Delays Specifies how SigNoise obtains buffer delays for the simulation.
From Library specifies that SigNoise obtain buffer delays stored
with the model in the library. This is the default.
On-the-fly specifies that SigNoise measure buffer delays and use
these delays in the remaining calculations.
Table 5-2 DeviceModels Tab Buttons
Button
Function
Browse Models
Displays the Model Browser, where you can locate and select IOCell
models. See Chapter 4, “The Model Browser.”
InterconnectModels Tab
From the InterconnectModels tab on the Analysis Preferences dialog box, you can establish
default values to determine how interconnect is modeled during simulation both before and
after routing and how crosstalk and SSN analysis is performed.
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Figure 5-2 Analysis Preferences Dialog Box - Interconnect Models Tab
Tab Options
The following table describes the options in the different areas of the InterconnectModels
tab.
.
Table 5-3 InterconnectModels Tab Fields
Option
Function
Percent
Manhattan
Sets the percent of manhattan distance value for unrouted
transmission lines. The default is 100%.
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Table 5-3 InterconnectModels Tab Fields
Option
Function
Default
Impedance
Sets the default impedance value. A typical value for most
technologies is 20-75 Ohms. The default is 60.
Default Prop
Velocity
Sets the default propagation velocity for unrouted transmission lines.
The default is 1.4142e+ or 0.08M/s.
Cutoff Frequency
Indicates the bandwidth within which interconnect parasitics are to
be solved. The default is 0GHz (and assumes a bandwisth of 1GHz).
Shape Mesh Size
Indicates the boundary element size when modeling routed traces,
which may be considered as shapes if the traces are 40 mils or
wider. The default is 50 mils.
Note: The default mesh size is 50 mils to improve simulator
performace. To get more accurate models for shapes and thick
traces, adjust this parameter to a lower value.
Via Modeling
Specifies how vias are modeled.
Fast Closed Form generates a via sub-circuit on the fly. This is the
default.
Ignore Vias reduces the via to a node in the net.
Accurate Closed Form searches the interconnect model library for
an appropriate via model and creates one if necessary.
Geometry Window Displays the distance away from the primary net that SigNoise
searches for neighbor nets when searching for sources of crosstalk.
SigNoise takes into account the nets on either side of the primary net
as well as the nets on layers above and below the primary net. The
default distance is 10 mil.
Min Coupled
Length
Displays the minimum length for which a primary net and a neighbor
net falling within the geometry window must run parallel in order for
them to be analyzed for crosstalk. The default is 300 mil.
Min Neighbor
Capacitance
Displays the minimum level of capacitive coupling between a primary
net a neighbor net falling within the geometry window in order for
them to be analyzed for crosstalk. The default is 0.1pF
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Table 5-3 InterconnectModels Tab Fields
Option
Function
Do Plane
Modeling
Specifies whether or not ground plane modeling is active. Be sure
that Do Plane Modeling is selected only when you are actively
using ground plane analysis. Checking this causes SSN simulations
to use an RLC mesh representation of the power and ground planes,
which models the delivery of the supply current to components.
Unchecking this models the power and ground planes as ideal
voltage sources in SSN simulations.
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Simulation Tab
From the Simulation tab on the Analysis Preferences dialog box, you can determine how
simulations are performed by default and define fast, typical, and slow simulation modes.
Figure 5-3 Analysis Preferences Dialog Box - Simulation Tab
Tab Options
The following table describes the command options and buttons in the different areas of the
Simulation tab.
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Table 5-4 Simulation Tab Options
Option
Function
Pulse Cycle Count
Sets the pulse number to measure from a series of pulses.
This value controls the simulation duration so that the
requested number of pulses propagates before the simulation
stops. The default is 1.
Pulse Clock Frequency
Displays the frequency of the pulse stimuli for nets that have
no specific pulse rate assigned. The default is 50 Mhz.
Pulse Duty Cycle
Sets the length of the high portion of the cycle as a fraction.
(0.5 represents equal high and low portions of the cycle.)
Pulse/Step Offset
Sets the launch time offset for the primary driver.
Fixed Duration
When checked the specified value determines the length of
time a simulation will run. If unchecked, SigNoise determines
the duration dynamically for each simulation.
Waveform Resolution
(Time)
Sets the waveform resolution as the default or as one of the
specified values. Controls how many data points are
generated by the simulation and how far apart they are in
time.
Values are: Default (Pulse Cycle Period/100), 10ps,
20ps, 50ps, 100ps, 200ps, 500ps, 1ns, 2ns, 5ns, 10ns.
Choosing a small value results in larger waveform files and
longer simulation times. You can change the default divisor
value with the ANL_WAVE_RESOLUTION_FACTOR
environment variable.
Measure Delays At
Specifies the voltage threshold from which SigNoise
measures delays.
Input Thresholds specifies that SigNoise measure delays at
the Input Logic Thresholds, Vil and Vih.
V Measure specifies that SigNoise measure delays at the
predetermined Buffer Delay Measurement Threshold, Vmeas
or Vmeasure.
Run Simulations in
Debug Mode
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When checked SigNoise ensures that prerequisites are in
place by running a net audit before running the simulation.
The default is unchecked.
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Table 5-4 Simulation Tab Options
Option
Function
Report Source Sampling When checked SigNoise reports data for the primary driver as
Data
if it is also a receiver. The default is unchecked.
Table 5-5 Simulation Tab Command Buttons
Button
Function
Fast/Typical/Slow
Opens the dialog box shown in the following figure for setting
default values fast, typical, and slow simulation modes.
Figure 5-4 Fast/Typical/Slow Dialog Box - General Tab
You can represent device operating conditions by simulating in Fast, Typical, and Slow
modes. The device model data is given as minimum, typcial, and maximum values. This form
controls the selection of model values for each simulation mode. For example, minimum Die
Capacitance usually results in the fastest operating mode.
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Units Tab
From the Units tab on the Analysis Preferences dialog box, you can determine the units in
which certain parameters are presented in dialog boxes and reports.
Figure 5-5 Analysis Preferences Dialog Box - Units Tab
Tab Options
The following table describes the data fields in the different areas of the Units tab.
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Table 5-6 Units Tab Options
Option
Function
Design Voltage
Displays a pull-down menu of available units for voltage: mV and
V. The default is V. Power supply voltages use this value.
Noise Voltage
Displays a pull-down menu of available units for noise voltage: mV
and V. The default is mV. Crosstalk, overshoot, and undershoot
use this value.
Design Resistance
Displays a pull-down menu of available units for resistance:
mOhm and Ohm. The default is Ohm. Resistor values use this
value.
Parasitic Resistance
Displays a pull-down menu of available units for parasitic
resistance: mOhm and Ohm. The default is mOhm. Package R
uses this value.
Design Capacitance
Displays a pull-down menu of available units for capacitance: pF,
nF, and uF. The default is pF. Capacitor values use this value.
Parasitic
Capacitance
Displays a pull-down menu of available units for parasitic
capacitance: pF, nF, and uF. The default is pF. Package C uses
this value.
Parasitic Inductance
Displays a pull-down menu of available units for parasitic
inductance: nH, pH, and uH. The default is nH. Package L uses
this value.
Delay Time
Displays a pull-down menu of available units for delay time: nS,
uS, mS, and S. The default is nS.
Length
Displays a pull-down menu of available units for length: mil,
Meter, mM, and uM. The default is Meter.
Spacing
Displays a pull-down menu of available units for spacing: mil,
Meter, mM, and uM. The default is mil.
EMI Tab
From the EMI tab on the Analysis Preferences dialog box, you can establish basic setup
information for EMI single net simulation. Use the Standard Preferences to establish an
environment appropriate for EMI simulation during design.
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Use the information in the Advanced Preferences area to view whether advanced EMI
simulations are selected and to establish advanced preferences for EMI single net simulation.
The advanced EMI preferences specify general control settings for EMI computations,
establish an OATS test environment appropriate for evaluation of an experimental setup, and
define values for computation of near field EMI effects.
Figure 5-6 Analysis Preferences Dialog Box - EMI Tab
Tab Fields
The following table describes the command options and buttons in the different areas of the
EMI tab.
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Table 5-7 EMI Tab Options - Standard Preferences Area
Option
Function
EMI Regulation
Specifies one of six available EMI regulations against which to
evaluate the design: FCC Class A, FCC Class B,
CISPR Class A, CISPR Class B, VCCI Class 1,
and VCCI Class 2.
The selected regulation determines which regulation curve is
superimposed on the emission level in the SigWave display and
the reported pass/fail status of the emission level.
Design Margin
Sets the design margin value. The Design Margin value is
subtracted from the regulation curve and affects the graphic
display of the regulation curve as well as the pass/fail status of the
report.
The default is 10dB.
Analysis Distance
Sets the distance between the board and the receiving antenna in
the measurements setup. The Analysis Distance value takes
precedence over any measurement distance specified by the
regulation.
The default is 3M.
Table 5-8 EMI Tab Options - Advanced Preferences Area
Option
Function
Emulate OATS
Displays whether or not an Open Area Test Site (OATS) test
scenario is enabled and specified in the Advanced Preferences
dialog box.
The default is No.
Compute Near Fields Displays whether or not computation of near field EMI effects is
enabled and specified in the Advanced Preferences dialog box.
The default is No.
Compute Current
Distribution
Displays whether or not computation of current distribution in the
frequency domain is enabled and specified in the Advanced
Preferences dialog box.
The default is No.
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Table 5-9 EMI Tab Buttons
Button
Function
Set Advanced
Preferences
Opens the dialog box shown in the following figure for specification
of:
■
General control settings for EMI computations
■
Control settings for OATS (Open Area Test Site) test scenario
■
Control settings for computation of near field EMI effects
Figure 5-7 Advanced Preferences Dialog Box
About Setting Preferences and Parameters
IOCell Model Defaults
Using the DeviceModels tab, you can determine whether or not SigNoise will use a default
IOCell model when it encounters a driver or receiver pin without an associated IOCell model.
You can further specify which IOCell model SigNoise will use for six specific pinuse types: IN,
OUT, BI, TRI, OCL, and OCA. Use Browse Models to open the Model Browser set to display
IOCell models. See the online help file for more information.
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Interconnect Model Defaults
Using the InterconnectModels tab, you can establish default values to determine how
interconnect is modeled during simulation both before and after routing and how crosstalk
analysis is performed.
Unrouted Interconnect Models
For pre-route signal integrity analysis, SigNoise models hypothetical traces using a percent
Manhattan value, a default impedance value, and a default propagation velocity. See the
online help for more information.
Routed Interconnect Models
For post-route signal integrity analysis, you can specify a field solver cutoff frequency and the
way that vias are modeled. The field solver cutoff frequency establishes a bandwidth within
which interconnect parasitics are solved. This prompts the SigNoise field solver to generate
frequency-dependent Cable models in the interconnect library. The default cutoff frequency
of 0GHZ directs the field solver to disregard signal frequencies. This saves computation time,
but may not be as accurate as frequency-dependent interconnect modeling.
To define how vias are modeled during simulation, first select whether vias are to be ignored
or whether each via should have a closed-form model. If you specified that closed-form
models are to be used, you can further specify whether SigNoise should save via models in
the interconnect library and search the interconnect library for via models.
Crosstalk
For crosstalk analysis, you can specify the size of the area that SigNoise will search for
neighbor nets and the minimum mutual capacitance value for a net to be considered a
neighbor net. The geometry window specifies the axial distance from the edge of the trace
that SigNoise will search for neighbor nets. The minimum coupled length is the minimum
distance that two traces must run parallel to each other within the geometry window distance
for SigNoise to consider the adjacent trace to be a neighbor net. The minimum mutual
capacitance value is the minimum amount of capacitive coupling between traces for SigNoise
to look for crosstalk.
Traces falling within the geometry window distance of the interconnect, traveling parallel to it
for more than the minimum coupled length, and having more than the minimum amount of
capacitive coupling will be regarded as neighbor net for the purpose of crosstalk calculations.
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Simulation Defaults
Using the Simulation tab, you can determine how simulations are performed by default and
define fast, typical, and slow simulation modes.
Define pulse stimuli in the following ways:
■
Use Pulse Cycle count to control the duration of the simulation by entering the number
of pulses to propagate through the system during the simulation.
■
Use Pulse Clock Frequency to control the cycle period for the pulse voltage sources
used for active drivers in the simulation.
■
Use Pulse Duty Cycle to specify the portion of the time the pulse stimuli is held in the
high state as a fraction of the entire pulse period.
A value of 0.5 represents equal high and low portions of the cycle period.
■
Use Pulse/Step Offset to control the launch time offset for the primary net driver.
■
Use Fixed Duration to specify the duration for a simulation. When this is not checked,
SigNoise chooses a duration for each simulation dynamically.
■
Use Fixed Timestep to specify the timestep for the simulation. When this is not
checked, SigNoise chooses a timestep for each simulation dynamically. Use caution
when setting fixed timesteps. A timestep that is too large can cause convergence failure
or inaccurate simulation results.
■
Use Fast/Typical/Slow to display the Fast/Typical/Slow Simulation Definition dialog box
to define simulation parameters for fast, typical, and slow simulation modes.
Fast, Typical, and Slow Simulation Modes
Use the Fast/Typical/Slow Simulation Definition dialog box to define simulation
parameters for fast, typical, and slow simulation modes.
On the Simulation tab, use Fast/Typical/Slow to display the Fast/Typical/Slow
Simulation Definition dialog box.
Each tab on this dialog box lets you define fast, typical, and slow mode for a list of related
properties. Properties are listed in a column on the left. Each property is followed by an array
of pulldown menus, one each for slow, typical, and fast mode. These choices refer to the
minimum, typical, and maximum values given in the IOCell model.
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In most cases the menu choices are minimum, typical, and maximum. On the General tab,
Ramp Rate choices are FastSlew, TypSlew, and SlowSlew. On the V/I Currents tab, all the
choices are TempCntl, Typ-Z, Low-Z, and High-Z.
If the simulation type is Temperature Controlled, the options in the Typical column of the form
are used, except for the V/I currents. In this case, the V/I curve used is interpolated between
the three given curves based on temperatures for each IOCell and the
VIReferenceTemperature parameter.
Default Units
Using the Units tab, you can establish default unit values by selecting an available unit from
the pulldown menu. See the online help for more information.
Simulating for Signal Integrity and EMI
Simulation Methodology
This section describes a use model for a design process that employs SigNoise to check for
signal integrity and EMI in high-speed printed circuit board (PCB) designs. This process is
part of the Cadence Performance Engineering Methodology.
The simulation tasks outlined include:
■
Setting up SigNoise and performing signal integrity analysis before routing.
■
Performing signal integrity analysis during routing of critical nets.
■
Performing signal integrity analysis after routing.
Preroute Signal Intergrity Analysis
Preroute signal integrity analysis comes after preliminary placement and before routing. In
preroute signal integrity analysis you are looking for the following:
■
How placement effects critical delays and reflections in the design.
■
How net scheduling effects delays and reflections.
■
The need for terminators on nets in the design.
■
An early evaluation of the power distribution system.
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Preroute Analysis Setup
The following figure and instructions describe the procedure for setting up SigNoise for
preroute signal integrity analysis.
Figure 5-8 Preroute Setup Diagram
Procedure:
1. Optionally, initialize an analysis directory to tell SigNoise where to write signal analysis
data files.
After placement, SigNoise can provide you with delay and distortion data that comes
from hypothetical traces. SigNoise develops these hypothetical traces based on a
percent Manhattan distance between pins and user-defined assumptions for the
characteristic impedance and propagation velocity. This information is specified on the
InterconnectModels tab in the Analysis Preferences dialog box.
2. Load device model libraries.
3. Assign device models from these libraries to components in the design.
4. Set simulation preferences and set up the layout cross section.
The preferences specify, for example, default IOCell models and the units of
measurements for reports. When you set up the cross section, you define, for example,
how the layers stack up and what materials and thicknesses you use for these layers.
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Performing Preroute Signal Integrity Analysis
After you set up your device models and device model libraries and make IOCell model
assignments, you can perform simulations and generate analysis data.
The following figure and instructions describe the procedure for performing preroute signal
integrity analysis.
Figure 5-9 Preroute Analysis Flow Diagram
Procedure:
1. Select signals for simulation by
❑
Clicking to select a ratsnest line or a pin in the design window.
–or–
❑
Specifying a net by name in the Signal Analysis dialog box.
–or–
❑
Specifying a netlist file by name in the Signal Analysis dialog box or selecting the
nets through Net Browser dialog box.
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2. Select the type of analysis results to create.
❑
Click Reports in the Signal Analysis dialog box to present the analysis results as text
reports. This opens the Report Generator.
–or–
❑
Click Waveforms in the Signal Analysis dialog box to present the analysis results as
waveform files. This opens the Waveform Simulation dialog box.
3. Specify the type of simulation you want SigNoise to run.
Select the appropriate options in the Report Generator or the Waveform Simulation
dialog box.
To use the Power Plane Designer to analyze your power and ground plane design,
specify the Do Plane Modeling interconnect modeling preference and perform a SSN
simulation.
4. Trigger the simulation.
Click Create Report or Create Waveforms. SigNoise performs the necessary simulations
based on your specifications.
5. Following simulation, you can look at the delay and distortion data in text reports, view
time domain waveform displays at driver and receiver pins, or view animated movies of
ground bounce between the power and ground planes.
The simulation results might lead you to edit the placement of components again, to
modify net schedules, or to experiment with terminators to suppress distortion.
Critical Net Analysis
After preroute analysis you might want to interactively route critical nets and then analyze
them for signal integrity.
The following figure and instructions describe the procedure for performing Critical Net
analysis during routing.
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Figure 5-10 Critical Net Analysis Flow Diagram
During preroute analysis, SigNoise built a simulation circuit model. It used the device models
that you specified and the hypothetical interconnect models that it approximated from the
percent Manhattan distance, the default impedance, and the default propagation velocity that
you specified. Now that the critical nets have been routed, you can analyze them more
precisely, this time using the actual etch instead of the Manhattan-based estimates.
Procedure:
1. You can begin critical net analysis with interconnect library setup to specify where you
want SigNoise to save the interconnect models it creates. You might also create a
Parasitics report for a critical net.
2. You can also scan the design for problem areas using the same steps you followed in
preroute analysis.
3. You then select a net for simulation and look at the results as waveform displays and text
reports.
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4. After you examine your results you can edit the routing for that critical net and perform
another analysis. The process of analysis and editing the traces is an iterative process
that you can continue until you see satisfactory simulation results.
Postroute Analysis
During postroute signal integrity analysis you look for:
■
The effect of the routed interconnect on signal integrity and EMI.
■
The effect that the routed interconnects have on each other.
That is, you can now see the effect of couplings between interconnect segments and how
they create crosstalk and affect signal integrity and EMI.
■
The effect of neighboring interconnects that you have added since critical nets were
routed.
The following figure and instructions describe a typical procedure for postroute analysis.
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Figure 5-11 Postroute Analysis Flow Diagram
1. Begin with the parasitic analysis.
2. After parasitic analysis you can scan the design for problem areas or proceed to detailed
analysis of individual nets.
You can run single or multi-line simulations depending on whether you want to take
neighboring nets into account.
3. After simulation you can:
❑
Look at the Delay, Ringing, Crosstalk, SSN, and EMI Single Net reports.
❑
Use the Conductor Cross Section window (sigxsect) to look at geometric displays of
the models SigNoise writes for interconnect segments.
❑
Use the EMWave window to view ground bounce movies.
If two interconnect segments are within the distance specified in Geometry Window
parameter and if you are running multi-line simulations, SigNoise writes a model that includes
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both interconnect segments. You see both segments in the Conductor Cross Section
Window. You can also display equipotential field lines between interconnects in the Conductor
Cross Section window. You can slide interconnect segments and see how it changes both the
field lines and the RLGC matrix of the model.
Note: Because of the high volume of simulations often performed for postroute analysis, you
have the option to run postroute analysis in batch mode rather than from the UI. For details,
see “Batch Simulation” on page 160.
Interactive Simulation
Using SigNoise interactively, you can quickly examine, or scan, one or more signals by
performing Reflection simulations and crosstalk estimations on entire designs or on large
groups of signals. You can also probe individual signals, or small groups of signals, where you
want to delve into specific signal behaviors in detail through the generation of discrete text
reports or waveforms.
Text Reports
When generating text reports, you can sort the results by specific criteria (that is, undershoot,
noise margin, or crosstalk) in order to rapidly identify signals that violate electrical constraints.
Waveforms and VI Curves
The waveform data shows the waveform of a signal on a driver-receiver pair. SigNoise
contains a waveform display tool called SigWave. Waveforms for all pins in a simulation circuit
can be displayed in SigWave. SigWave also displays the VI curves for IOCell models.
Conductor Cross Sections
SigNoise generates models for the interconnect in your design. The SigNoise field solver
generates the parasitic values in the model. The SigNoise sigxsect window shows you a
three-dimensional view of the interconnect and its parasitic values.
Ground Bounce “Movies”
When you use power and ground plane design features of the Power Plane Builder to perform
SSN simulation with the Do Plane Modeling feature enabled, SigNoise produces a three
dimensional, animated movie depicting the ground bounce generated during the simulation.
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You can use the EMWave window to view the movie as well as a static view of the RF hot
spots that occurred.
Simulation Process
SigNoise can locate problem areas in your design. Use the following steps to diagnose and
resolve those problems:
1. First quickly examine, or scan, large groups of nets, or the entire design, for problem
areas.
2. Based on the waveforms and text reports resulting from these initial analyses, analyze
small groups of signals, or specific individual signals, in order to troubleshoot signal
integrity or EMI issues.
Important
Before performing simulation, be sure that the following optional setup tasks have
been considered:
❑
Manual simulator Initialization
See Chapter 2, “Setting Up the Simulation Environment” for more information.
❑
Specification of simulation preferences and parameters
See “Simulation Preferences and Parameters” on page 130.
Color Highlighting During Analysis
SigNoise will highlight pins and connect line segments on nets when you analyze a design.
When SigNoise analyzes the pin-to-pin connections in a design, it highlights the objects
shown in the following table. The highlight colors can be modified using the
Display – Color/Visibility dialog box in SPECCTRAQuest or the Color – Color Display
dialog box in Allegro/APD
.
Table 5-10 Object Hightlight Colors
Object
Assigned Highlight Color
The connect line segment that contributes Temp highlight
the most crosstalk to the pin-to-pin
connection.
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Table 5-10 Object Hightlight Colors
Object
Assigned Highlight Color
The driver and receiver pins, the connect
line between them, and all components
between these pins such as a series
resistor.
Perm highlight
To begin interactive signal integrity and EMI analysis:
➤
Select the option shown in the following figure from the main menu of either the
SPECCTRAQuest Floorplanner or Allegro/APD .
The Signal Analysis dialog box is displayed as shown in the following figure.
Figure 5-12 Signal Analysis dialog box
Use the Signal Analysis dialog box as the starting point for performing signal integrity and EMI
emissions simulations. The Signal Analysis dialog box enables you to select nets and driverreceiver combinations for analysis.
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You can also display the Signal Analysis Wave and Report Generator dialog boxes from the
Signal Analysis dialog box. In these dialog boxes, you specify which waveforms or reports to
generate. SigNoise performs the necessary simulations accordingly.
The SigXplorer topology editor and the sigxsect interconnect cross-section viewer can also
be launched from the Signal Analysis dialog box. Use SigXplorer to perform what-if studies
on different driver and receiver combinations and transmission line scenarios. Use sigXsect
to display cross-sections of routed interconnect segments.
The following tables describe the data fields and command buttons in the different areas of
the Signal Analysis dialog box.
Table 5-11 Signal Analysis Dialog Box - Options
Option
Function
Net
Specifies a net name or a net name match pattern. New names and
match patterns are added to the pull down list of names.
Nets
Lists the selected nets.
Driver Pins
Lists all driver pins on the net highlighted in the Nets list box.
Load Pins
Lists the receiver pins (or loads) seen by the driver pin highlighted in the
Driver Pins list box.
Other Pins
Lists all the pins seen by the driver pin highlighted in the Driver Pins list
box that are not driver or receiver pins. These pins usually have the
UNSPEC pinuse.
Table 5-12 Signal Analysis Dialog Box - Buttons
Button
Function
List of Nets
Displays a file browser to display netlist files.
Net Browser
Displays an XNET browser for selecting nets.
Reports
Displays the Analysis Report Generator dialog box, for specifying,
generating, viewing, and storing text reports of simulation results.
Waveforms
Displays the Analysis Waveform Generator dialog box for specifying,
generating, viewing, and storing simulation results as waveforms.
View
Topology
Launches the SigXplorer topology modeling interface for the selected
signal.
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Table 5-12 Signal Analysis Dialog Box - Buttons
Button
Function
View
Geometry
Displays the sigxsect viewer for displaying cross-sectional views of routed
interconnect segments.
Selecting Nets and Pins for Simulation
In the Signal Analysis dialog box, you can select nets for analysis in several different ways:
■
Click on ratsnest lines, routed etch, etch, or pins in the design window.
■
Click Net Browser in the Signal Analysis dialog box to select groups of nets by browsing
for netlist files.
❑
■
You can create a netlist file with a text editor. See “Netlist” in the online help for more
information.
At the SPECCTRAQuest Floorplanner or Allegro/APD command line, type:
net <name>
Upon selection of a net or a pin pair, the names of the nets and driver, and receiver pins
appear in the Nets, Driver Pins, and Load Pins list boxes in the Signal Analysis dialog box.
Also, the Allegro message line or the SPECCTRAQuest message log window display
messages that tell you that SigNoise is gathering extended net information for the nets that
you selected.
General Steps for Interactive Simulation
Use the Signal Analysis dialog box and the following procedures to perform interactive signal
integrity and EMI analysis.
To scan a group of nets for signal integrity problem areas:
1. Create a group of nets to analyze in one of the following ways:
❑
Click List of Nets browser to select an existing netlist file.
– or –
❑
Click Net Browser to choose nets by name from a list of available nets.
2. Select the type of simulation output you desire in one of the following ways:
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❑
Click Reports to display the Report Generator dialog box to create one of ten
standard text reports or a customized text report.
– or –
❑
Click Waveforms to display the Waveform Generator dialog box to create results as
waveform (.sim) files.
3. In either the Report or Waveform Generator dialog box, specify the details of the
simulation. For example, the type of stimulus to use. See “Analysis Results” on page 163
for more information.
4. Examine the simulation results.
5. Based on your interpretation of the simulation results
❑
Perform more simulations on the current group of nets or select a different group of
nets.
– or –
❑
Perform a more detailed analysis on a smaller group of nets or on a selected net or
driver pin and load pin pair.
To analyze a single net or a single driver pin and load pin pair for signal integrity and
electromagnetic interference problems:
1. Select a net or driver pin and load pin pair in one of the following ways:
❑
Select the net by name from the Nets list box.
– or –
❑
Select the driver pin and load pin by name from the Driver Pins and Load Pins list
boxes
– or –
❑
Select a net by clicking to select it in the design.
2. Select the type of simulation output you desire:
❑
Click Reports to display the Report Generator dialog box to create one of nine
standard text reports or a customized text report.
– or –
❑
Click Waveforms to display the Waveform Generator dialog box to create results as
waveform (.sim) files.
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3. In either the Report or Waveform Generator dialog box, specify the details of the
simulation. For example, the type of stimulus to use. See “Analysis Results” on
page 163for more information.
4. Examine the simulation results.
5. Based on your interpretation of the simulation results:
❑
Perform another detailed analysis on the selected net or driver pin and load pin pair.
– or –
❑
Perform a more detailed analysis on a smaller group of nets.
Move back and forth between analyzing groups of nets and probing individual nets and driver
pin and receiver pin pairs where you have located signal integrity problems.
Batch Simulation
In addition to performing signal integrity analysis interactively from the UI, you can also use
SigNoise in batch mode. See the Batch Generation information in each of the text report
sections within “Standard Report Generation” on page 170for more information
Crosstalk Analysis
You can choose between two modes of crosstalk analysis: estimated and simulated.
❑
Estimated crosstalk lets you quickly scan your design to identify problem areas for
further, detailed, crosstalk simulations. Estimated crosstalk constructs a table of
crosstalk data based on a series of crosstalk simulations performed on the specified
traces at various trace spacings.
❑
Detailed crosstalk analysis uses multiline simulations for more detailed and accurate
analysis.
Both crosstalk estimation and detailed crosstalk simulation can be timing-driven. Performing
timing driven crosstalk analysis using crosstalk timing windows greatly increases real-world
accuracy.
Timing-Driven Crosstalk Analysis
SigNoise lets you perform timing driven crosstalk analysis using crosstalk timing windows.
Timing driven crosstalk analysis can both minimize crosstalk false alarms and reduce the
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overall pessimism of crosstalk results, thus helping you to increase the density of your
designs.
Crosstalk timing windows use crosstalk timing properties to determine when nets are active
and sensitive. Only aggressor nets that have an active time overlap with the victim nets
sensitive time as crosstalk contributors are considered.
The following crosstalk timing properties can be applied to nets:
❑
XTALK_ACTIVE_TIME
❑
XTALK_SENSITIVE_TIME
❑
XTALK_IGNORE_NETS
You can assign the XTALK_ACTIVE_TIME property to a net to specify the times during which
that net can generate crosstalk on a neighbor net. If a net has no attached
XTALK_ACTIVE_TIME property, SigNoise assumes that the net can generate crosstalk at all
times.
You can assign the XTALK_SENSITIVE_TIME property to specific nets for even greater
accuracy to indicate times when that net is susceptible to crosstalk and when it is not.
You can use the XTALK_IGNORE_NETS property to tell a net or a group of nets to disregard
other nets or group of nets as a source of crosstalk. An example would be when you want to
disregard crosstalk between bits on a synchronous bus.
A Simple Example
In Crosstalk simulations, the XTALK_ACTIVE_TIME, XTALK_SENSITIVE_TIME, and
XTALK_IGNORE_NETS crosstalk properties can be used to determine how to stimulate
multi-line circuits for crosstalk analysis. For example, assume a victim net being analyzed for
crosstalk had 2 aggressor nets, and they had the following properties:
❑
victim net - XTALK_SENSITIVE_TIME = 5-10
❑
neighbor #1 - XTALK_ACTIVE_TIME = 7 - 15
❑
neighbor #2 - XTALK_ACTIVE_TIME = 20-25
Neighbor #2 would not be stimulated in the circuit, since its active time does not overlap with
the victim net's sensitive time. In this case, stimulating both aggressor nets together would be
overly pessimistic, and not indicative of real-world behavior.
For more information, see Chapter 6, “Crosstalk Timing Windows.”
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EMI Analysis
Simulation
SigNoise provides EMI single net simulations which allow you to compute differential mode
radiated electric field emissions from traces. Simulation results include a graphical display of
the emission spectrum and a text report summarizing emission details and compliance
results.
Using EMControl with SigNoise
You can use SigNoise in conjunction with EMControl to perform EMI analysis. Some of the
signal routing and signal quality rules provided with EMControl employ SigNoise simulations
and SigNoise device models during analysis for EMI. Using EMControl enables design
engineers to begin evaluating their designs for EMI early in the design process and with
increasing accuracy throughout design development.
Before running EMC rule-checking, you need to perform the following SigNoise setup tasks:
❑
Specify any analysis preferences. If necessary, SigNoise will create a new
simulation case directory.
❑
Specify which device and interconnect model libraries SigNoise should use.
❑
Assign the SIGNAL_MODEL property to components.
In addition when you initialize the EMControl run directory, you need to point EMControl to
this SigNoise run directory. For additional information, see EMControl in the online help.
Multi Board Analysis
SigNoise lets you perform multi-board (or system level) simulation for a design that is made
up of more than one printed circuit board (PCB). When a net extends to more than one PCB,
SigNoise can analyze and report the behavior of a signal as it propagates from a driver on
one PCB to a receiver on another.
Nets that span multiple PCBs are analyzed using a multi-board System Configuration. A
multi-board System Configuration contains a pin map, to hook up connector pins on one PCB
to connector pins on another. When a circuit is built for an system extended net (SXnet) that
spans multiple PCBs, SigNoise traces out the interconnect to the connector pin, then finds
the system connection in the device library and jumps to the next PCB to continue tracing out
the circuit. The System Configuration can contain a model to represent the mated connector
or cable that physically connects the two PCBs. One circuit, spanning the multiple PCBs, is
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generated for the entire xnet, allowing full system-level simulations to be done. For details,
see Chapter 9, “Multi-Board Designs (Systems).”
Analysis Results
SigNoise provides analysis results in the following forms:
■
Ten differerent types of standard analysis text reports.
■
Custom designed text reports.
■
Waveforms and accompanying data.
■
VI curves and accompanying data.
For details on how to display, see VI Curves in the online help.
■
Conductor Cross Section diagrams.
■
Ground Bounce “movies” .
For details on how to display, see EMWave in the online help.
Analyzing to Generate Text Reports
When you perform analysis for signal integrity or EMI emmissions by generating text reports,
SigNoise performs the necessary simulations based on the specifications you make in the
Signal Analysis and Analysis Report Generator dialog boxes.
Having both dialog boxes open together, you can switch back and forth between them
selecting nets and pins for analysis from the Signal Analysis dialog box and specifying report
and simulation details from the Analysis Report Generator dialog box.
After examining the report data, you can then refine your net/pin selection and simulation
details, change simulation preferences (if necessary), and perform more specific analyses to
pinpoint problem signals.
The following table describes the different text reports which are available
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.
Table 5-13 Standard Analysis Reports
Type
Description
Reflection Summary
Gives delay and distortion data in a concise, summary format.
See “Reflection Summary Report” on page 170.
Delay
Gives propagation delays, switch delays (rising and falling edge),
settle delays (rising and falling edge), and reports a pass or fail
status for first incident rise and fall and monotonic rise and fall
heuristics for selected nets. See “Delay Report” on page 182.
Ringing
Gives overshoot and noise margin values for selected nets. See
“Ringing Report” on page 186.
Single Net EMI
Gives essential EMI data for the net in a concise, single-line
format. See “Single Net EMI Report” on page 191.
Parasitics
Gives total self capacitance, impedance range, and transmission
line propagation delays for selected nets. See “Parasitics Report”
on page 193.
SSN
Gives noise levels induced on a component’s power and ground
busses when drivers on that bus switch simultaneously. See
“SSN Report” on page 195.
SDF Wire Delay
Displays the standard delay format report. See “SDF Wire Delay
Report” on page 200.
Segment-based
Crosstalk Estimation
Presents detailed segment-based coupling information derived
from xtalk tables. See “Segment Crosstalk Report” on page 201.
Crosstalk Summary
Gives peak and total crosstalk for selected nets in a concise,
summary format. Crosstalk values are derived from multi-line
simulations. See “Crosstalk Summary Report” on page 206.
Crosstalk Detailed
Gives total crosstalk on selected nets. For all cases simulated,
crosstalk values are derived from multi-line simulations. See
“Crosstalk Detailed Report” on page 209.
To begin text report based analysis:
➤
Click Reports in the Signal Analysis dialog box. See Figure 5-12 on page 156for more
information.
The Analysis Report Generator dialog box is displayed, as shown in the following figure.
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Figure 5-13 The Analysis Report Generator Dialog Box - Standard Report Tab
Note: The dialog box is shown with default selections.
In the Signal Analysis dialog box you can:
■
Select nets and pin pairs for analysis. See “Selecting Nets and Pins for Simulation” on
page 158for more information.
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In the Analysis Report Generator dialog box you can:
■
Select one of ten standard report types.
■
Specify the format for a custom report.
■
Select simulation details common to both Standard and Custom reports.
■
Select whether or not to use timing windows and save circuit files and waveform files.
■
Display the Analysis Preferences dialog box to modify simulation preferences.
■
Run simulations and generate reports based on the selection criteria.
The Standard Report Tab
Tab Sections and Buttons
The following tables describe the different sections and command buttons in the Standard
Report tab. For more detailed information, see the online help.
Table 5-14 Tab Sections
Section
Function
Current Case
The name of the current case including a pulldown menu of
available cases from which you can select to report on.
Report Types
Check boxes to indicate report types currently selected. Multiple
report types may be selected to generate a more comprehensive
report.
Fast/Typical/Slow
Mode
Check boxes to specify the speed at which SigNoise will run
simulations.
Victim
Pull down menus for selecting victim net(s) to be monitored
during simulation and selecting victim net driver(s) to be
stimulated when victim nets are held in the high state.
Aggressor
Pull down menus for selecting aggressor switch mode, net
selection, and driver selection.
Reflection Data
Simulation
Radio buttons for simulation type and stimulus measurement
type.
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Table 5-14 Tab Sections
Section
Function
Use Timing Windows
A check box to indicate if SigNoise will use timing window
properties to refine the crosstalk simulations to account for
received crosstalk that is insignificant due to the timing of signals.
Save Circuit Files
A check box to indicate if SigNoise will save resulting tlsim and
Spice circuit files in the simulation case directory for each
simulation performed.
Save Waveforms
A checkbox to indicate if SigNoise will save waveform files in the
case directory for each simulation performed.
Table 5-15 Tab Buttons
Button
Function
Create Report
Starts report generation using the selections you specified in the
both the Signal Analysis and Report Generator dialog boxes.
Preferences
Displays the Analysis Preferences dialog box enabling you to
modify simulation preferences as you specify simulations and
generate reports.
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The Custom Report Tab
Figure 5-14 The Analysis Report Generator Dialog Box - Custom Report Tab
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Tab Sections and Buttons
The following tables describe the different sections and command buttons in the Custom
Report tab. For more detailed information, see the online help.
Table 5-16 Tab Sections and Options
Section or Option
Function
Case Selection
The current case including a pulldown menu of available cases
from which you can select to report on.
Report Name
The current report format including a pulldown menu to select an
existing report to copy and rename. CustomRpt is the default
format name.
Sort By
The current sort column including a pulldown menu to select an
alternate data column by which to sort the report data. Worst
case values are sorted to the front.
Check boxes to specify one or more speeds at which SigNoise will
Fast/Typical/Slow
run simulations. Fast/Slow and Slow/Fast refers to speeds of
Mode
driver/receiver combinations.
The current net and driver selection mode including pull down
Victim
menus to select an alternate net or driver selection mode.
Simulation Data Table The current report column content including pulldown menus to
define alternate content for up to eight columns within the report.
Define an empty column by selecting the Blank option from its
pulldown menu.
The current column content for the setup data table including
Setup Data Table
pulldown menus to define alternate column content for the setup
data table printed at the end of the report. Define an empty column
by selecting the Blank option from its pulldown menu.
A
check box to specify that SigNoise use timing window properties
Use Timing Windows
to refine the crosstalk simulations to account for received crosstalk
that is insignificant due to the timing of signals.
A check box to specify that SigNoise save resulting tlsim and
Save Circuit Files
Spice circuit files in the simulation case directory for each
simulation performed.
A checkbox to specify that SigNoise save waveform files in the
Save Waveforms
case directory for each simulation performed.
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Table 5-17 Tab Buttons
Button
Function
Clone Selected
Report
Copies the selected report. You are prompted to enter a name for
the copy. The renamed copy is added to the pulldown menu in
the Report Name: field.
New Custom Report
Creates a new report. You are prompted to enter a name for the
new report. The new report is added to the pulldown menu in the
Report Name: field.
Generates the report as you have specified it in the Signal
Analysis and Report Generator dialog boxes.
Displays the Analysis Preferences dialog box enabling you to
modify simulation preferences as you specify simulations and
generate reports.
Create Report
Preferences
Standard Report Generation
Reflection Summary Report
The Reflection summary report presents simulation results for propagation delays, switch
delays (rising and falling edge), and settle delays (rising and falling edge). It also reports a
pass/fail status for first incident rise and fall and monotonic rise and fall for selected nets.
In the case of multiple receivers on a net, the Reflection summary report shows only the worst
case. While the delay report shows data for all receivers, the Reflection summary is generally
a good first cut when you analyze the entire board (simulating all nets) as it limits the data to
one line per receiver net.
The Reflection report can be generated either in batch mode or interactively from the Analysis
Report Generator dialog box.
Batch Generation
Following is an example of a batch command which would generate a Reflection summary
report:
signoise -f my_nets.txt -r ReflectionSummary -s reflection -o ref_rp1.txt my.brd
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Table 5-18 Batch Command Switches - Reflection Summary Report
Switch
Description
-f
A list of nets file
-r
Report type to be generated
-s
Simulation type to perform (Reflection or Comprehensive)
-o
Name of output file to be created
Interactive Generation
Selection of the Reflection Summary option in the Analysis Report Generator dialog box
specifies a Reflection summary report for selected nets. See Figure 5-13 on page 165.
Sample Reflection Summary Report
Note: Some report sections are split to fit the page.
################################################################################
# SPECCTRAQuest 14.0
# (c) Copyright 1998 Cadence Design Systems, Inc.
#
# Report: Standard Reflection Summary Sorted By Worst Settle Delay
#
Wed Feb 9 14:13:48 2000
################################################################################
********************************************************************************
Delays (ns), Distortion (mV), (Typ FTSMode)
********************************************************************************
XNet
Drvr
Rcvr
NMHigh NMLow
OShootHigh
---------------- --------------- -------------- ------ ------ ---------1 memory A4
memory J47 35
memory U18 29 678.7
-84.46
4001
1 memory A4
memory J47 35
memory U3 29
991
819.1
3991
1 memory -CAS
memory J47 111 memory U14 17 -30.5
769.2
3984
1 memory A0
memory J47 33
memory U14 23 643.1
-39.78
3994
1 memory -CAS
memory J47 111 memory U7 17
-24.21 777.6
3976
1 memory BA0
memory J47 122 memory U18 20 624.8
-29.29
3979
...
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Sample Report (continued)
********************************************************************
********************************************************************
OShootLow SwitchRise SwitchFall SettleRise SettleFall Monotonic
--------- ----------- ----------- ----------- ----------- ---------334.6
4.667
2.01
8.236 *
3.169 *
FAIL
313.4
4.689
2.027
8.183 *
3.155 *
FAIL
253.1
4.828
2.037
8.17 *
3.145 *
FAIL
250.6
4.769
1.98
8.159 *
3.115 *
FAIL
248.4
4.843
2.04
8.135 *
3.136 *
FAIL
273.8
4.687
1.923
8.133 *
3.151 *
FAIL
...
******************************************************************
Pulse Data Per Xnet
******************************************************************
XNet
PulseFreq PulseDutyCycle PulseCycleCount
---------------------- --------- -------------- --------------1 memory WP
50MHz
0.5
1
1 memory UN4CAP226PA0
50MHz
0.5
1
1 memory UN4CAP225PA0
50MHz
0.5
1
1 memory SDA
50MHz
0.5
1
1 memory SCL
50MHz
0.5
1
1 memory SA2
50MHz
0.5
1
...
***********************************************
Description of column abbreviations
***********************************************
Column
Description
------------ --------------------------------XNet
Extended net
Drvr
Driver Pin
Rcvr
Receiver Pin
NMHigh
Noise Margin High
NMLow
Noise Margin Low
OShootHigh
Maximum Overshoot
OShootLow
Minimum Overshoot
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Report Computations
Delay Criteria
Propagation Delay
Propagation delay is the summation of all calculated transmission line delays along the
shortest path between two points. Although propagation delay is a calculated value, tlsim (the
simulator) performs the calculation since it is the only tool that has a system level view of the
transmission line paths.
Propagation Delay Measurement Points
Propagation Delay Simulation
Propagation delay is measured from any simulation available. SigNoise performs a Reflection
simulation with pulse stimulus if no simulation results are available. Propagation delay is used
for the DELAY_RULE and MATCHED_DELAY constraints.
First Switch Delay
For a rising edge, the simulation measurement is from time zero to when the receiver first
crosses Vil, the low voltage switching threshold. The associated rising buffer delay for the
driving IOCell is subtracted from this measurement value to produce the reported first switch
delay.
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For a rising edge: First switch delay = time to reach Vil - buffer delay
Rising Edge Switch Delay Measurement Points
For a falling edge, the simulation measurement is from time zero to when the receiver first
crosses Vih, the high voltage switching threshold. The associated falling buffer delay of the
driving IOCell is subtracted from this measurement value to produce the reported first switch
delay.
For a falling edge: First Switch = time to reach Vih - buffer delay
Falling Edge Switch Delay Measurement Points
Switch Delay Simulation
SigNoise performs either a Reflection or Comprehensive simulation with pulse stimulus to
collect a first switch delay measurement which is used for the MIN_FIRST_SWITCH
constraint.
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Final Settle Delay
Final settle delay is the time to reach the second threshold voltage encountered and stay
above or below it, minus the Buffer Delay for the driver.
For a rising edge, the simulation measurement is from time zero to when the receiver crosses
Vih, the high threshold voltage, the final time and settles into the high logic state. The
associated rising buffer delay for the driving IOCell is subtracted from this measurement value
to product the reported final settle delay.
Rising Edge Settle Delay Measurement Points
For a falling edge, the simulation measurement is from time zero to when the receiver first
crosses Vih, the high voltage switching threshold. The associated falling buffer delay of the
driving IOCell is subtracted from this measurement value to produce the reported first switch
delay.
Falling Edge Settle Delay Measurement Points
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Settle Delay Simulation
SigNoise performs either a Reflection or Comprehensive simulation with pulse stimulus to
collect a final switch delay measurement which is used for the MAX_FINAL_SETTLE
constraint.
Buffer Delay
Buffer delay is the time it takes the voltage of a driver to reach a predefined measurement
voltage, Vmeas, when driving a standard test load. Buffer delay is subtracted from the
absolute time for a receiver waveform to reach a logic threshold. The difference between
these two measurements represents the portion of the delay attributable to interconnect
effects. Buffer delay is measured for both rising and falling edges.
When measuring waveforms at a receiver against time zero in a simulation, the buffer delay,
or driving IOCell delay, is included as well as the delay contributed by the interconnect. For
the purpose of timing analysis, the buffer delay is already accounted for in the overall
component delay. In order that the buffer delay is not counted twice, the assumed buffer delay
is subtracted from the simulation results when reporting first switch and final settle delays.
Since the actual topology to which each pin is attached is not available for up-front timing
analysis, a test load (or test fixture) is assumed to be attached to the buffer in order to derive
the component delay. SigNoise hooks up the IOCell to its corresponding test load circuit and
runs simulations to capture the slow, typical, and fast buffer delay values, measured at Vmeas
for rising and falling edges.
Rising Edge Buffer Delay Measurement Points
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Buffer Delay Simulation
When a simulation is run for a design, the appropriate buffer delay is subtracted to properly
compensate switch and settle delays so that these delay measurements represent
interconnect contribution only.
The buffer delay selection information you enter in the SPECCTRAQuest, Allegro, or signal
explorer Analysis Preferences dialog box allows you to specify how SigNoise should obtain
the buffer delay values to use during the simulation. You can instruct SigNoise to retrieve
stored buffer delay values from the device model or to measure buffer delay at the start of the
simulation.
Note: Use the Buffer Delay Selection options on the Device Models tab to set From Library
or On-the-Fly.
Once measured, buffer delay is stored with the pin data for the individual pins of an IBIS
Device Model. Buffer delay values for a pin are found on the Buffer Delays dialog box which
is accessible from the IBIS Device Pin Data dialog box of the IBIS Device Model Editor. When
buffer delay values are not available in the IBIS device model, buffer delays are not subtracted
from the reported first switch and final settle delay values. You may use On-the-fly buffer delay
method to compute the buffer delays along with other simulation results in that case.
Distortion Criteria
Noise Margin
For a rising edge, high state noise margin is the measure of how close the high state receiver
waveform comes to the high state switching threshold, Vih. This measurement, Vmin, is taken
after the waveform crosses Vih and before the onset of a falling transition that crosses both
thresholds (falling side of the pulse).
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Rising Edge Noise Margin Measurement Points
For a falling edge, low state noise margin is the measure of how close the low state signal
comes to the low switching threshold. This measurement is taken after crossing the low
switching threshold, and before the onset of a rising transition that crosses both thresholds
(rising side of the pulse).
Falling Edge Noise Margin Measurement Points
Noise Margin Simulation
SigNoise performs either a Reflection or a Comprehensive simulation to collect the noise
margin measurement which is used for the MIN_NOISE_MARGIN constraint.
Overshoot
Overshoot is the maximum voltage excursion of a signal measured in absolute voltage units.
Note that the overshoot voltages are measured relative to the zero volt ideal ground, not the
steady state value of the signal, Vss.
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For a rising edge, high state overshoot is the highest voltage seen. For a falling edge, low
state overshoot is the lowest voltage seen.
Rising Edge High State Overshoot Measurement Points Falling Edge Low State Overshoot Measurement Points
Overshoot Simulation
SigNoise performs either a Reflection or Comprehensive simulation to collect overshoot
measurements which are used for the MAX_OVERSHOOT constraint. Note that for rising
edges, the high state overshoot is greater than MAX_OVERSHOOT and for falling edges, the
low state overshoot is less than MAX_OVERSHOOT.
Non-Monotonic Edge
Non-monotonic edge is a PASS or FAIL status value indicating whether an edge is monotonic
or not. A rising edge is monotonic if each next point in time has a greater voltage value than
the previous point until it crosses Vih. A falling edge is monotonic if each next point in time
has a smaller voltage value than the previous point until it crosses Vil.
A non-monotonic edge is considered significant for clock signals. The presence of a nonmonotonic edge can be regarded as non-monotonic switching.
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For a rising edge, a non-monotonic edge is a signal reversal that occurs after crossing the low
voltage threshold, Vil, but before the signal reaches the high voltage threshold, Vih.
Rising Edge Non-Monotonic Edge Measurement Points
For a falling edge, a non-monotonic edge is a signal reversal that occurs after crossing the
high voltage threshold, Vih, but before the signal reaches the low voltage threshold, Vil.
Falling Non-Monotonic Edge Measurement Points
Non-Monotonic Edge Simulation
SigNoise performs either a Reflection or Comprehensive simulation to collect the nonmonotonic edge data which is used for the EDGE_SENS constraint.
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Electrical Constraints
The following constraints can be set on a net or on a pin-to-pin connection for evaluation
during delay analysis
.
Table 5-19 Measure Delay Value Comparisons
Constraint
Definition
Format
MAX_OVERSHO
OT
Limits the minimum and maximum
absolute voltage for a receiver.
maximum value:minimum value
MIN_NOISE_MAR Limits the amount of ringback as
GIN
compared to the receiver’s voltage
thresholds.
maximum value:minimum value
MIN_FIRST_SWIT Limits the time to reach and stay
CH
above/below the low/high switching
threshold voltage.
maximum value:minimum value
MAX_FINAL_SET Limits the time to reach and stay
TLE
above/below the high/low switching
threshold voltage.
maximum value:minimum value
Table 5-20 Timing Rule Constraint Checks
Constraint
Item
DELAY_RULE
Minimum propagation delay
Maximum propagation delay
MIN_FIRST_SWIT Minimum first switch delay
CH
MAX_FINAL_SET Maximum final settle delay
TLE
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Delay Report
The delay report presents simulation results for propagation delays, switch delays (rising and
falling edge), and settle delays (rising and falling edge). It also reports a pass/fail status for
first incident rise and fall and monotonic rise and fall for selected nets.This report is good for
checking clock nets, particularly to detect non-monotonic rise or fall.
Important
You can use the delay values and First Incident Switch heuristic to check data nets,
but they are not a substitute for full-path-based timing analysis which is
recommended. It is possible that adjusting interconnect lengths or terminating to
achieve first incidence switching will solve problems found by the delay report.
The delay report can be generated either in batch mode or from the Analysis Report
Generator dialog box.
Batch Generation
Following is an example of a batch command which would generate a delay report on a list
of nets with comprehensive odd simulations using typical FTS mode:
signoise -f my_nets.txt -r Delay -n Odd -s Comprehensive -o delay_rpt1.txt my.brd
Table 5-21 Batch Command Switches - Delay Report
Switch
Description
-f
A list of nets file
-r
Report type to be generated
-n
Neighbor switching mode for Comprehensive simulation
-s
Simulation type to perform (Reflection or Comprehensive)
-o
Name of output file to be created
Interactive Generation
Selection of the Delay option in the Analysis Report Generator dialog box specifies a
delay report for selected nets. See Figure 5-13 on page 165.
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Sample Delay Report
Note: Some report sections are split to fit the page.
################################################################################
# SPECCTRAQuest 14.0
# (c) Copyright 1998 Cadence Design Systems, Inc.
#
# Report: Standard Delay Report
#
Thu Feb 10 14:39:17 2000
################################################################################
********************************************************************************
Delays (ns) (Typ FTSMode)
********************************************************************************
XNet
Drvr
Rcvr
PropDly SwitchRise
---------------- --------------- -------------- ------- ---------1 memory A4
memory J47 35
memory U20 29
0.7089
5.188
1 memory -CAS
memory J47 111
memory U9 17
0.6992
5.376
1 memory A3
memory J47 118
memory U12 26
0.6884
5.192
1 memory CLKE1
memory R4 2
memory U12 37
0.6876
3.189
1 memory CLKE1
memory R4 2
memory U20 37
0.6875
3.197
1 memory A2
memory J47 34
memory U12 25
0.6869
5.225
...
...
********************************************
********************************************
SwitchFall SettleRise SettleFall
---------- ---------- ---------2.415
7.847 *
2.749 *
2.404
7.89 *
2.8 *
2.353
7.786 *
2.681 *
2.293
5.881 *
2.649 *
2.308
5.88 *
2.641 *
2.379
7.86 *
2.716 *
...
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Sample Report (continued)
********************************************************************************
Monotonicity (Typ FTSMode)
********************************************************************************
XNet
Rcvr
FirstIncRise FirstIncFall MonotonicRise
---------------- -------------- ------------ ------------ ------------1 memory WP
memory U11 7
PASS
PASS
PASS
1 memory WP
memory U10 7
PASS
PASS
PASS
1 memory CLKE1
memory U20 37 PASS
PASS
PASS
1 memory CLKE1
memory U19 37 PASS
PASS
PASS
1 memory CLKE1
memory U12 37 PASS
PASS
FAIL
1 memory CLKE1
memory U14 37 PASS
PASS
PASS
...
*************
*************
MonotonicFall
------------PASS
PASS
PASS
PASS
PASS
PASS
...
*********************************************************************************
Driver I/O Characteristics (Typ FTSMode) RiseSlew/FallSlew in (mV/ns)
*********************************************************************************
Drvr
IOModel
Volmax Vohmin
RiseSlew FallSlew
------------- ---------------- ------ ------- -------- -------memory R6 1
CDSDefaultOutput 100 mV 4500 mV 3333
3333
memory C23 1
CDSDefaultOutput 100 mV 4500 mV 3333
3333
memory R3 1
CDSDefaultOutput 100 mV 4500 mV 3333
3333
memory RP5 2
CDSDefaultOutput 100 mV 4500 mV 3333
3333
memory U5 11
CDSDefaultOutput 100 mV 4500 mV 3333
3333
memory U5 47
CDSDefaultOutput
100 mV
4500 mV
3333
3333
...
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Sample Report (continued)
*************************************************
Load I/O Characteristics:
*************************************************
Rcvr
IOModel
Vilmax
Vihmin
-------------- --------------- ------- ------memory U11 7
CDSDefaultInput 2000 mV 3000
memory U10 7
CDSDefaultInput 2000 mV 3000
memory U20 37
CDSDefaultInput 2000 mV 3000
memory U19 37
CDSDefaultInput 2000 mV 3000
memory U12 37
CDSDefaultInput 2000 mV 3000
memory U14 37
CDSDefaultInput 2000 mV 3000
...
mV
mV
mV
mV
mV
mV
*********************************************************************************
Pulse Data Per Xnet
*********************************************************************************
XNet
PulseFreq PulseDutyCycle PulseCycleCount
---------------------- --------- -------------- --------------1 memory WP
50MHz
0.5
1
1 memory UN4CAP226PA0
50MHz
0.5
1
1 memory UN4CAP225PA0
50MHz
0.5
1
1 memory SDA
50MHz
0.5
1
1 memory SCL
50MHz
0.5
1
1 memory SA2
50MHz
0.5
1
...
***********************************************
Description of column abbreviations
***********************************************
Column
Description
------------ --------------------------------DefImp
Default Impedence
DefPropVel
Default Propagation Velocity
DiffPairMate Differential Pair Mate
Drvr
Driver Pin
FTSMode
Fast/Typical/Slow Mode
FallDly
Fall Buffer Delay
FallSlew
Fall Slew : 20%/80% dV/dT
FirstIncFall First Incident Switch Fall
FirstIncRise First Incident Switch Rise
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GeomWin
IOModel
JTemp
MhtPercent
PropDly
Rcvr
RiseDly
RiseSlew
SettleFall
SettleRise
SwitchFall
SwitchRise
Vihmin
Vilmax
Vohmin
Volmax
XNet
Geometry Window
I/O Cell Model Name
Pin Junction Temperature
Percent Manhattan Distance
Propagation Delay
Receiver Pin
Rise Buffer Delay
Rise Slew : 20%/80% dV/dT
Settle Fall Delay
Settle Rise Delay
Switch Fall Delay
Switch Rise Delay
High State Logic Input Threshold
Low State Logic Input Threshold
High State Logic Output Threshold
Low State Logic Output Threshold
Extended Net
Report Computations
The Delay report computations are the same as those for the Reflection Summary Report.
For more information, see “Report Computations” on page 173.
Ringing Report
The ringing report shows noise margin as well as overshoot high and low values for all
selected nets. It also identifies IOCell characteristics that have been applied. This report
requires either a Reflection or Comprehensive simulation for each driver pin.
Use this report to detect impedance discontinuities that are significant due to the high slew
rates of the drivers. Usually these problems are corrected by changing terminations, topology,
or driver characteristics.
The ringing report also includes the Extended Net Distortion section containing the following:
■
A subsection for each driver on the extended net and the noise margin and overshoot
information for the driver-receiver pair.
■
Pins on the extended net and buffer model information about the pins.
You can generate the ringing report either in batch mode or interactively from the Analysis
Report Generator dialog box.
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Batch Generation
Following is an example of a batch command which would generate a ringing report on a list
of nets with Fast/Slow FTS mode:
signoise -f my_nets.txt -r Ringing -m Fast/Slow -o ring_rpt1.txt my.brd
Table 5-22 Batch Command Switches - Ringing Report
Switch
Description
-f
A list of nets file
-r
Report type to be generated
-m
Mode to be used while simulating for reports or waveforms
-o
Name of output file to be created
Interactive Generation
Selection of the Ringing option in the Analysis Report Generator dialog box specifies a
ringing report for selected nets. See Figure 5-13 on page 165.
Sample Report
Note: Some report sections are split to fit the page.
################################################################################
# SPECCTRAQuest 14.0
# (c) Copyright 1998 Cadence Design Systems, Inc.
#
# Report: Standard Ringing Report Sorted By Worst Noise Margin
#
Mon Feb 14 16:59:38 2000
################################################################################
********************************************************************************
Distortion (mV) (Typ FTSMode)
********************************************************************************
XNet
Drvr
Rcvr
NMHigh NMLow
OShootHigh
---------------- --------------- -------------- ------ ------ ---------1 memory SDA
memory U10 5
memory U11 5
1960
1943
5007
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1 memory
1 memory
1 memory
1 memory
1 memory
...
...
DQM1
-CS1
-CS3
SCL
DQM1
memory
memory
memory
memory
memory
J47
J47
J47
J47
J47
29
114
129
83
29
memory
memory
memory
memory
memory
U5 39
U17 19
U14 19
U10 6
U3 39
1936
1934
1932
1930
1964
1936
1954
1936
1931
1928
5012
5003
5013
5013
5002
*********
*********
OShootLow
---------471
-595.8
-682
-695.6
-138.7
-626.7
...
...
Sample Report (continued)
********************************************************************************
Driver I/O Characteristics (Typ FTSMode) RiseSlew/FallSlew in (mV/ns)
********************************************************************************
Drvr
Device
IOModel
Volmax
--------------- ------------------------------- ---------------- -----memory R6 1
RES_603-0,1A,603,E-603
CDSDefaultOutput 100 mV
memory C23 1
CAP_603-10PF,5%,50V,603,E-603
CDSDefaultOutput 100 mV
memory R3 1
RES_603-10,5%,603,E-603
CDSDefaultOutput 100 mV
memory RP5 2
RPAK4C-4R_SM-10,5%,A1206-SM
CDSDefaultOutput 100 mV
memory U5 11
SDRAM2MX4BX8_SSOP-SDRAM2MX4BX8A CDSDefaultOutput 100 mV
memory U5 47
SDRAM2MX4BX8_SSOP-SDRAM2MX4BX8A CDSDefaultOutput 100 mV
...
************************************************
************************************************
Vohmin
RiseSlew FallSlew JTemp DiffPairMate
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------4500 mV
4500 mV
4500 mV
4500 mV
4500 mV
4500 mV
...
-------3333
3333
3333
3333
3333
3333
-------- ----3333
3333
3333
3333
3333
3333
-----------NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
********************************************************************************
Load I/O Characteristics
********************************************************************************
Rcvr
Device
IOModel
Vilmax
-------------- ------------------------------- --------------- ------memory U11 7
NM24C03_SSOP-UNKNOWN,E-SSOP
CDSDefaultInput 2000 mV
memory U10 7
EPROMSERIAL_SOI8-624664-301-SOA CDSDefaultInput 2000 mV
memory U20 37
SDRAM2MX4BX8_SSOP-SDRAM2MX4BX8A CDSDefaultInput 2000 mV
memory U19 37
SDRAM2MX4BX8_SSOP-SDRAM2MX4BX8A CDSDefaultInput 2000 mV
memory U12 37
SDRAM2MX4BX8_SSOP-SDRAM2MX4BX8A CDSDefaultInput 2000 mV
memory U14 37
SDRAM2MX4BX8_SSOP-SDRAM2MX4BX8A CDSDefaultInput 2000 mV
...
*********************
Sample Report (continued)
*********************
Vihmin
DiffPairMate
------- -----------3000 mV NA
3000 mV NA
3000 mV NA
3000 mV NA
3000 mV NA
3000 mV NA
...
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*********************************************************************************
Pulse Data Per Xnet
*********************************************************************************
XNet
PulseFreq PulseDutyCycle PulseCycleCount
---------------------- --------- -------------- --------------1 memory WP
50MHz
0.5
1
1 memory UN4CAP226PA0
50MHz
0.5
1
1 memory UN4CAP225PA0
50MHz
0.5
1
1 memory SDA
50MHz
0.5
1
1 memory SCL
50MHz
0.5
1
1 memory SA2
50MHz
0.5
1
...
***********************************************
Description of column abbreviations
***********************************************
Column
Description
------------ --------------------------------DefImp
Default Impedence
DefPropVel
Default Propagation Velocity
DiffPairMate Differential Pair Mate
Drvr
Driver Pin
FTSMode
Fast/Typical/Slow Mode
FallSlew
Fall Slew : 20%/80% dV/dT
GeomWin
Geometry Window
IOModel
I/O Cell Model Name
JTemp
Pin Junction Temperature
MhtPercent
Percent Manhattan Distance
MinNM
Minimum Noise Margin
NMHigh
Noise Margin High
NMLow
Noise Margin Low
OShootHigh
Maximum Overshoot
OShootLow
Minimum Overshoot
Rcvr
Receiver Pin
RiseSlew
Rise Slew : 20%/80% dV/dT
Vihmin
High State Logic Input Threshold
Vilmax
Low State Logic Input Threshold
Vohmin
High State Logic Output Threshold
Volmax
Low State Logic Output Threshold
XNet
Extended Net
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Report Computations
The Ringing report computations are the same as those for the Reflection Summary Report.
For more information, see “Report Computations” on page 173.
Single Net EMI Report
EMI simulation computes the differential mode radiated emission arising from clock signals
propagating on all fully routed nets taking one net (or Xnet) at a time. EMI Simulations
simulate only the victim net and none of the neighboring aggressor nets. EMI simulation does
not account for the parasitics of power and ground pins.
In EMI simulations, SigNoise:
1. Traces out the extended net (xnet)
2. Characterizes the interconnect cross sections
3. Obtains the relevant device models
4. Builds a single-line circuit (disregards neighbor nets)
5. Runs a Reflection simulation using a pulse stimulus one cycle in length
6. Obtains and stores geometrical information for EMI computations (for example,
interconnect coordinates, and circuit board orientation)
The pulse stimulus is applied to the driver pin on the Xnet. In the case of multiple drivers on
a net, multiple simulations are run, with one active driver stimulated in each simulation. Other
drivers on the Xnet are inactive during the simulation.
The transient simulation output is time domain voltage and current waveforms at a set of
predetermined nodes. As a minimum, all driver and receiver pins on the xnet are treated as
nodes. Additional nodes at transmission line branch points may be included for increased
accuracy.
The single net EMI report can be generated either in batch mode or interactively from the
Analysis Report Generator dialog box.
Batch Generation
Following is an example of a batch command which would generate a single net EMI report.
signoise -f nets.txt -r SingleNetEMISummary -o emi.txt my.brd
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Table 5-23 Batch Command Switches - Single Net EMI Report
Switch
Description
-f
A list of nets file
-r
Report type to be generated
-o
Name of output file to be created
Interactive Generation
Selection of the Single Net EMI option in the Analysis Report Generator dialog box
specifies a single net EMI report for selected nets. See Figure 5-13 on page 165.
Sample Report
Note: Some report sections are split to fit the page.
################################################################################
# SPECCTRAQuest 14.0
# (c) Copyright 1998 Cadence Design Systems, Inc.
#
# Report: Single Net Emissions Report
#
Tue Feb 15 14:16:08 2000
################################################################################
********************************************************************************
Voltage (V), Time (ns), Emission (dBuV/m), (Typ FTSMode)
********************************************************************************
XNet
Drvr
PulseFreq VoltageSwing RiseTime
---------------------- --------------- --------- ------------ -------1 memory WP
memory R6 1
50MHz
4.4
0.9
1 memory UN4CAP226PA0
memory C23 1
50MHz
4.4
0.9
1 memory UN4CAP225PA0
memory R3 1
50MHz
4.4
0.9
1 memory SDA
memory U10 5
50MHz
4.4
0.6
1 memory SCL
memory J47 83
50MHz
4.4
0.9
1 memory SA2
memory J47 167 50MHz
4.4
0.9
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**************************************
**************************************
PeakEmission PeakFrequency EMIStatus
------------ ------------- --------28.86
850Mhz
Pass
NA
NA
NA
NA
NA
NA
36.05
1250Mhz
Pass
34.19
950Mhz
Pass
32.69
950Mhz
Pass
...
Sample Report (continued)
*************************************************
Pulse Data Per Xnet
*************************************************
XNet
PulseFreq PulseDutyCycle
---------------------- --------- -------------1 memory WP
50MHz
0.5
1 memory UN4CAP226PA0
50MHz
0.5
1 memory UN4CAP225PA0
50MHz
0.5
1 memory SDA
50MHz
0.5
1 memory SCL
50MHz
0.5
1 memory SA2
50MHz
0.5
Parasitics Report
The parasitics report shows total self capacitance, impedance range, and transmission line
propagation delays for selected nets. The total net self capacitance includes capacitance
from the transmission lines, via padstacks, pin padstacks, and IOCell die. Delay values are
compared against delay constraints, if any exist. Information about the pins of the selected
nets is included.
You can use the parasitics report to identify nets that are either overloaded or have excessive
impedance discontinuities. The net parasitics report is a good choice for analyzing analog
nets. This report does not use crosstalk estimations.
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You can generate the parasitics report either in batch mode or interactively from Analysis
Report Generator dialog box.
Batch Generation
Following is an example of a batch command which would generate a Parasitics report.
signoise -f my_nets.txt -r Parasitics -o parasitics_rpt1.txt my.brd
Table 5-24 Batch Command Switches - Parasitics Report
Switch
Description
-f
A list of nets file
-r
Report type to be generated
-o
Name of output file to be created
Interactive Generation
Selection of the Parasitics option in Analysis Report Generator dialog box specifies a
parasitics report for selected nets. See Figure 5-13 on page 165.
Sample Report
Note: This report has been split to fit the page.
################################################################################
# SPECCTRAQuest 14.0
# (c) Copyright 1998 Cadence Design Systems, Inc.
#
# Report: Standard Parasitics Report
#
Thu Feb 17 10:08:16 2000
################################################################################
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********************************************************************************
XNet Parasitics
********************************************************************************
XNet
MinImpedance MaxImpedance Capacitance Inductance
---------------------- ------------ ------------ -------------------1 memory WP
70.72
70.72
2.035e-12
NA
1 memory UN4CAP226PA0
70.72
70.72
4.607e-13
2.525e-09
1 memory UN4CAP225PA0
70.72
70.72
5.447e-13
2.946e-09
1 memory SDA
70.72
70.72
1.639e-1
NA
1 memory SCL
70.72
70.72
1.45e-12
NA
1 memory SA2
70.72
70.72
1.426e-12
NA
...
**********
**********
---------Resistance
NA
0.005502
0.008619
NA
NA
NA
...
SSN Report
The SSN report shows noise levels induced on the power and ground busses of a component
when all drivers deriving power from that bus switch simultaneously. These noise levels are
used as an approximation of the distortion effects that will be seen at the signal pins. The
power bus noise is used as the basis for Rise distortion, and ground bus noise for Fall
distortion. The power and ground busses are identified in this report.
Only power and ground nets must be routed to yield accurate results for the SSN report,
although package parasitics are accounted for even without power and ground routing.
Component placement adjustment, decoupling, power and ground net reassignment, and
power/ground plane rearrangement are techniques used for solving SSN noise problems. It
may be useful to use this report during both placement and routing phases, taking care to
update the SimulSwitch simulations.
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The SSN report also includes the Extended Net SSN section containing:
■
A subsection for each driver pin on the extended net and the Rise SSN and Fall SSN
information for the driver.
■
Pins on the extended net and information about the pins.
The SSN report can be generated either in batch mode or interactively from the Analysis
Report Generator dialog box.
Batch Generation
Following is an example of a batch command which would generate an SSN report.
signoise -f my_nets.txt -r SSN -o ssn_rpt1.txt my.brd
Table 5-25 Batch Command Switches - SSN Report
Switch
Description
-f
A list of nets file
-r
Report type to be generated
-o
Name of output file to be created
Interactive Generation
Selection of the SSN option in the Analysis Report Generator dialog box specifies a
simultaneous switching noise report for selected nets. See Figure 5-13 on page 165.
Sample Report
Note: Some sections of this report have been split to fit the page.
################################################################################
# SPECCTRAQuest
# (c) Copyright 1998 Cadence Design Systems, Inc.
#
# Report: Standard SSN Report
#
Mon Mar 27 17:57:23 2000
################################################################################
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*********************************************************************************
Simultaneous Switching Noise (mV) for XNet `2 ssn NET1` (Typ FTSMode)
*********************************************************************************
Drvr
Net
PowerBus SSNRise GroundBus SSNFall
-------- -------- -------- ------- --------- ------ssn U1 2 ssn NET1 pwrbus
505.5
gndbus
944.2
--------------------------------------------------------------------*********************************************************************************
Driver I/O Characteristics (Typ FTSMode) RiseSlew/FallSlew in (mV/ns)
*********************************************************************************
Drvr
IOModel
Volmax Vohmin
RiseSlew FallSlew
-------- ------------ ------ ------- -------- -------ssn U1 2 CDSDefaultIO 100 mV 4500 mV 5000
5000
--------------------------------------------------------------------*****************************
Load I/O Characteristics
*****************************
Rcvr IOModel Vilmax Vihmin
---- ------- ------ ----------------------------------
Sample Report (continued)
******************************************************
Pulse Data Per Xnet
******************************************************
XNet
PulseFreq PulseDutyCycle PulseCycleCount
---------- --------- -------------- --------------2 ssn NET1 50MHz
0.5
1
-----------------------------------------------------********************************************************
Simulation Preferences
-------------------------------------------------------Variable
Value
-------------------------------------Percent Manhattan
100
Default Impedance
60ohm
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Default Prop Velocity
Geometry Window
Min Neighbor Capacitance
Cutoff Frequency
Pulse Clock Frequency
Pulse Duty Cycle
Pulse Step Offset
1.4142e+08M/s
10mil
0.1pF
0GHz
50MHz
0.5
0ns
******************************************************
Description of abbreviations
******************************************************
Abbr
Abbreviations
---------- -----------------------------------------DefImp
Default Impedence
DefPropVel Default Propagation Velocity
Drvr
Driver Pin
FTSMode
Fast/Typical/Slow Mode
FallSlew
Fall Slew : 20%/80% dV/dT
GeomWin
Geometry Window
IOModel
I/O Cell Model Name
MhtPercent Percent Manhattan Distance
Rcvr
Receiver Pin
RiseSlew
Rise Slew : 20%/80% dV/dT
SSNFall
Simultaneous Switching Noise on Ground Bus
SSNRise
Simultaneous Switching Noise on Power Bus
Sample Report (continued)
Vihmin
High State Logic Input Threshold
Vilmax
Low State Logic Input Threshold
Vohmin
High State Logic Output Threshold
Volmax
Low State Logic Output Threshold
XNet
Extended Net
-----------------------------------------------------*****************************************************************
Net name syntax
----------------------------------------------------------------Net: <design name> <net name>
XNet: <number of nets> <design name> <first net name>
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----------------------------------------------------------------*********************************************************************************
Pulse Data Per Xnet
*********************************************************************************
XNet
PulseFreq PulseDutyCycle PulseCycleCount
--------------------- --------- -------------- --------------1 memory WP
50MHz
0.5
1
1 memory UN4CAP226PA0 50MHz
0.5
1
1 memory UN4CAP225PA0 50MHz
0.5
1
1 memory SDA
50MHz
0.5
1
1 memory SCL
50MHz
0.5
1
1 memory SA2
50MHz
0.5
1
...
Report Computations
For the high state, the magnitude of the largest negative excursion of the power bus voltage
is measured. All driver pins are simultaneously switched for the rising edge and waveforms
are generated at the die for the driver device’s power bus. The rising edge simultanous
switching noise is taken as the magnitude of difference between the steady state voltage of
the power bus minus the lowest excursion of the power bus waveform.
For the low state, the magnitude of the largest positive excursion of the ground bus voltage is
measured. All driver pins are simultaneously switched for the falling edge and waveforms are
generated at the die for the driver device’s ground bus. The falling edge simultanous switching
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noise is taken as the magnitude of difference between the highest excursion of the ground
bus waveform minus the steady state voltage of the ground bus.
Simultaneous Switching Noise Measurement Points
Electrical Constraints
The following constraints can be set on a net or on a pin-to-pin connection for evaluation
during delay analysis
.
Table 5-26 Measured Delay Value Comparisons
Constraint
Definition
Format
MAX_SSN
Limits noise due to simultaneous
switching outputs.
maximum value:minimum value
SDF Wire Delay Report
You can generate a Standard Delay Format Wire Delay report either in batch mode using the
a2sdf command or interactively from the Analysis Report Generator dialog box.
Using the a2sdf command to Extract Wire Delay Data
You can use the a2sdf wire delay extract utility to generate a standard delay format file
containing compensated switch and settle delays as well as rise fall compensation delays.
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Enter the following command at the operating system prompt:
a2sdf [optional_arguments] drawing_file
Table 5-27 a2sdf Command Arguments- SDF Wire Delay Report
Argument
Description
-s
Include simulated compensated switch and settle delays.
-R
Include only rising propagation delays.
-F
Include only falling propagation delays.
-f netfile
Analyse only tje nets in the specified file.
drawing_file
A .brd file from which to extract wire delay data.
Interactive Generation
Selection of the SDF Wire Delay option in the Analysis Report Generator dialog box
specifies a SDF Wire Delay report for the specified board. See Figure 5-13 on page 165.
Segment Crosstalk Report
The segment crosstalk report presents detailed segment-based coupling information derived
from post-layout verification. Included in the report is a segment-by-segment listing of
coupled lengths, indication of layers involved, along with x-y coordinates of where coupling
occurs and estimated crosstalk for coupled segments. The segment crosstalk report also
includes the information on crosstalk received from each single aggressor neighbor XNet and
total crosstalk received from all aggressor neighbor nets.
This report is actually a superset of both crosstalk and parallelism reports. This means that
segments within the geometry window that are parallel, but have no crosstalk effects on each
other, will still appear in the table with crosstalk values set to zero. Also, when there are no
crosstalk values available, only the parallelism data will be shown in the report with crosstalk
values set to NA. The report data is supplied in a delimited text format suitable for export to
spreadsheet applications.
Segment-based crosstalk estimation is intended to support an interactive crosstalk
debugging/etch-editing use model, where rapid results and quick identification of worst
offenders are required. Rather than performing costly coupled-line time domain simulation in
real time, this technique performs the time domain simulation up front to sweep
representative crosstalk circuits for the design, generating tables of crosstalk data. Although
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net to net results are available in the report format, they are also enforced by on-line Design
Rule Checks (DRCs) in the SPECCTRAQuest™ Floorplanner and Allegro® environments, as
well as by the SPECCTRA™ autorouter.
Important
Segment-based crosstalk estimation does not take into account detailed topological
effects like reflections, wave cancellation, or the plethora of unique stimulus
combinations that can occur in actual designs. To analyze these effects, full time
domain crosstalk simulation should be utilized.
The segment crosstalk report can be generated either in batch mode or interactively from the
Analysis Report Generator dialog box.
Batch Generation
Following is an example of a batch command which would generate a segment crosstalk
report:
signoise -f nets.txt -g 100 -l 500 -r SegmentXtalk -a Each -o test_xtalk.rpt
test.brd
Table 5-28 Batch Command Switches - Segment Crosstalk Report
Switch
Description
-f
A list of nets file
-g
Geometry window size
-l
Minimum coupled length to consider
-r
Report type to be generated
-a
Which aggressors to include in the crosstalk estimations (Each
should be specified to generate a segment report)
-o
Name of the output file to be created
Interactive Generation
Selection of the Segment Crosstalk option in the Analysis Report Generator dialog box
specifies a Segment Crosstalk report for selected nets. See Figure 5-13 on page 165.
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Note: To generate an appropriate report, be sure to select the Each Neighbor option (for Net
Selection) in the Aggressor section of the dialog box.
Important
To obtain segment-based crosstalk results, crosstalk tables must be available in
your board file. If not, the dialog box shown below will appear after clicking the
Create Report button asking if you would like to have them generated. If you select
No, your report will include parallelism data only, with all crosstalk values set to NA.
Figure 5-15 Crosstalk Tables Dialog Box.
Sample Report
################################################################################
# SPECCTRAQuest 14.0
# (c) Copyright 1998 Cadence Design Systems, Inc.
#
# Report: Standard Segment Crosstalk Report
#
Thu Feb 03 14:07:53 2000
################################################################################
*********************************************************************************
Segment Crosstalk (mV)
*********************************************************************************
Victim
Aggressor
Layer:Layer
XYCoord Gap Length SegXtalk
-------------- ---------------------- ------------ -------- --- ------ --2 dimm128 DQ47 all_neighbor_xnets
NA
NA
NA
NA
18.1
2 dimm128 DQ47 dimm128 DQR45
NA
NA
NA
729
12.69
2 dimm128 DQ47 dimm128 DQR45
BOTTOM:BOTTOM 1672:243
10
233
7.823
2 dimm128 DQ47 dimm128 DQR45
BOTTOM:BOTTOM 1842:290
10
116
3.895
2 dimm128 DQ47 dimm128 DQR45
BOTTOM:BOTTOM 1544:232
13
32
0.8844
2 dimm128 DQ47 dimm128 DQR45
BOTTOM:BOTTOM 2006:473
50
267
0.8566
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2 dimm128
2 dimm128
2 dimm128
2 dimm128
2 dimm128
2 dimm128
2 dimm128
2 dimm128
2 dimm128
2 dimm128
2 dimm128
0.02591
2 dimm128
2 dimm128
2 dimm128
2 dimm128
2 dimm128
2 dimm128
...
...
January 2002
DQ47
DQ47
DQ47
DQ47
DQ47
DQ47
DQ47
DQ47
DQ47
DQ47
DQ47
dimm128
dimm128
dimm128
dimm128
dimm128
dimm128
dimm128
dimm128
dimm128
dimm128
dimm128
DQR45
DQR45
DQR45
DQR45
DQR45
DQR43
DQR43
DQR43
DQR43
DQR43
DQR43
BOTTOM:BOTTOM
BOTTOM:BOTTOM
BOTTOM:BOTTOM
BOTTOM:BOTTOM
BOTTOM:BOTTOM
NA
BOTTOM:BOTTOM
BOTTOM:BOTTOM
BOTTOM:BOTTOM
BOTTOM:BOTTOM
BOTTOM:BOTTOM
DQ47
DQ47
DQ47
DQ47
DQ47
DQ47
dimm128
dimm128
dimm128
dimm128
dimm128
dimm128
DQR42
DQR42
DQR42
DQR42
DQR42
DQR46
NA
NA
NA
421
BOTTOM:BOTTOM 1659:291 26 230
BOTTOM:BOTTOM 1801:318 26 74
BOTTOM:BOTTOM 1827:381 38 74
BOTTOM:BOTTOM 1523:291 48 43
NA
NA
NA
367
204
1895:353 18 19
1903:370 23 23
1532:207 25 18
1889:337 38 17
1532:218 16 4
NA
NA
448
1663:275 10 237
1813:307 10 88
1844:380 21 76
1523:275 32 43
1844:340 36
4
0.3371
0.2855
0.207
0.09458
0.0868
11.27
7.958
2.955
1.013
0.357
3.919
2.54
0.8171
0.4117
0.1504
3.876
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Report Format
Column
Data Description
Victim
The net receiving the coupling from the neighbor nets.
Aggressor
The net contributing the coupling to the victim net.
Specifies for this coupled segment, the layer the victim and aggressor nets
are routed on respectively. For example, if the coupled segments of both
nets are routed on the TOP layer, it would read TOP:TOP. If the coupled
segment had the victim net on INT1 and the neighbor net on INT2, then this
column would read INT1:INT2. Layer to layer information is only applicable
to coupled segments.
Specifies the xy coordinate for the middle of the aggressor segment
coupling, enabling crossprobing, troubleshooting and debugging. The xy
coordinate is available only for segment-to-segment couplings. It is not
applicable to net-to-net coupling in the table.
Specifies the distance between the segments on the victim and neighbor
nets. For cases where the coupling occurs on the same layer, this is simply
the spacing between the traces. For layer-to-layer coupling cases, this gap
represents a combination of the dielectric spacing between the layers and
the offset between the victim and neighbor (Pythagorean Theorem). The
gap only applicable to coupled segments.
The length of the coupled segment. Note that the table gives a segment-bysegment breakdown, and also an overall net-to-net value, and an overall allneighbors-to-victim-net value.
Amount of voltage coupled over from the aggressor to the victim in that
particular coupled segment.
Layer:Layer
XYCoord
Gap
Length
SegXtalk
Note: The initial value in this column represents the total crosstalk received
from all neighbors. The next set of values consists of a single neighbor
crosstalk total followed by a segment-by-segment crosstalk breakdown for
the same neighbor. This pattern is then repeated for each neighbor listed in
the report.
Report Computations
The all-neighbors-to-victim-net value is calculated based on the root-sum-squared (RSS)
summation method.
Crosstalk is the magnitude of the voltage change seen at a pin on a victim net where the
voltage change is induced by signals on coupled neighboring aggressor xnets when drivers
on aggressor nets are switching simultaneously.
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The crosstalk measurement for a victim net held in the high state is taken as the magnitude
of the difference between the lowest excursion of the receiver waveform minus the victim net’s
steady state voltage. The crosstalk measurement for a victim net held in the low state is
measured as the magnitude of the difference between the highest excursion of the receiver
waveform minus the victim net’s steady state voltage.
Crosstalk measurements for victim nets in both the high and low states are shown in the
following figure.
Crosstalk Measurement Points
Crosstalk Summary Report
The crosstalk summary report delivers an abbreviated crosstalk report, identifying only the
selected victim xnet and driver, and reporting on high and low state crosstalk for odd and even
stimulus.
You can generate the crosstalk summary report either in batch mode or interactively from the
Analysis Report Generator dialog box.
Batch Generation
Following is an example of a batch command which would generate a crosstalk summary
report with All Neighbor crosstalk simulations on the entire board using fast mode.
signoise -f my_nets.txt -a All -n Odd,Even -r XtalkSummary -m Fast
-o xtlksum_rpt1.txt my.brd
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Batch Command Switches - Crosstalk Summary Report
Switch
Description
-f
A list of nets file.
-a
Aggressors specified for crosstalk simulations. Choices are:
Each, All, Inter, or Intra.
-n
Neighbor switching mode specified for crosstalk and
comprehensive simulations. Choices are: Even,Odd or
Odd,Even.
-r
Report type to be generated.
-m
Mode to be used while simulating for reports or waveforms.
-o
Name of output file to be created.
Interactive Generation
Selection of the Crosstalk Summary option in the Analysis Report Generator dialog box
specifies a Crosstalk Summary report for selected nets. See Figure 5-13 on page 165.
Sample Report
Note: This report has been split to fit the page.
################################################################################
# SPECCTRAQuest 14.0
# (c) Copyright 1998 Cadence Design Systems, Inc.
#
# Report: Standard Crosstalk Summary Report Sorted By Worst Case Crosstalk
#
Thu Feb 17 12:02:03 2000
################################################################################
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********************************************************************************
All Neighbors Crosstalk (mV) (Typ FTSMode)
********************************************************************************
Victim XNet
Victim Drvr
HSOddXtalk HSEvenXtalk LSOddXtalk
--------------------- -------------- ---------- ----------- ---------1 memory A7
memory J47 120 401.5
NA
214.6
1 memory A0
memory J47 33
387.9
NA
229.8
1 memory A3
memory J47 118 384.2
NA
207.3
1 memory A4
memory J47 35
351.4
NA
200.5
1 memory A9
memory J47 121 306.4
NA
168.7
1 memory BA1
memory
J47 39
297.8
NA
159.5
...
***********
***********
LSEvenXtalk
----------NA
NA
NA
NA
NA
NA
...
Report Computations
Crosstalk is the magnitude of the voltage change seen at a pin on a victim net where the
voltage change is induced by signals on coupled neighboring aggressor xnets when drivers
on aggressor nets are switching simultaneously.
The crosstalk measurement for a victim net held in the high state is taken as the magnitude
of the difference between the lowest excursion of the receiver waveform minus the victim net’s
steady state voltage. The crosstalk measurement for a victim net held in the low state is
measured as the magnitude of the difference between the highest excursion of the receiver
waveform minus the victim net’s steady state voltage.
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Crosstalk measurements for victim nets in both the high and low states are shown in the
following figure.
Crosstalk Measurement Points
Crosstalk Detailed Report
The crosstalk detailed report identifies the selected victim xnet, drivers, and all receivers, and
reports on high and low state crosstalk for odd and even stimulus. It also provides information
on the devices and models used, their electrical characteristics, the default simulation
settings, and a full glossary of abbreviations.
The crosstalk detailed report can be generated either in batch mode or interactively from the
Analysis Report Generator dialog box.
Batch Generation
Following is an example of a batch command which would generate a crosstalk detailed
report with All Neighbor crosstalk simulations on the entire board using fast mode.
signoise -f my_nets.txt -a Each -D All -n Odd,Even -r XtalkDetailed
-m Fast -o xtlkdet_rpt1.txt my.brd
Table 5-29 Batch Command Switches - Crosstalk Detailed Report
Switch
Description
-f
A list of nets file.
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Table 5-29 Batch Command Switches - Crosstalk Detailed Report
Switch
Description
-a
Aggressors specified for crosstalk simulations. Choices are:
Each, All, Inter, or Intra.
-D
Use either the fastest driver or the all drivers on the neighboring
aggressor nets. Choices are: Fastest or All.
-n
Neighbor switching mode specified for crosstalk and
comprehensive simulations. Choices are: Even,Odd or
Odd,Even.
-r
Report type to be generated.
-m
Mode to be used while simulating for reports or waveforms.
-o
Name of output file to be created.
Interactive Generation
Selection of the Crosstalk Detailed option in the Analysis Report Generator dialog box
specifies a Crosstalk Detailed report for selected nets. See Figure 5-13 on page 165.
Sample Report
Note: Some sections of this report have been split to fit the page.
################################################################################
# SPECCTRAQuest 14.0
# (c) Copyright 1998 Cadence Design Systems, Inc.
#
# Report: Standard Crosstalk Report Sorted By Worst Case Crosstalk
#
Thu Feb 17 16:42:21 2000
################################################################################
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********************************************************************************
All Neighbors Crosstalk at Receivers (mV) (Typ FTSMode)
********************************************************************************
Victim XNet
Victim Drvr
Victim Rcvr
HSOddXtalk HSEvenXtalk
--------------- -------------- ------------- ---------- ----------1 memory A7 memory J47 120 memory U17 32 401.5
NA
1 memory A7 memory J47 120 memory U4 32
391
NA
1 memory A0 memory J47 33
memory U12 23 387.9
NA
1 memory A3 memory J47 118 memory U12 26 384.2
NA
1 memory A0 memory J47 33
memory U17 23 380.2
NA
1 memory A3 memory J47 118 memory U9 26
376.4
NA
...
***********************
***********************
LSOddXtalk LSEvenXtalk
---------- ----------214.6
NA
209.3
NA
229.8
NA
207.3
NA
210.1
NA
202
NA
...
Sample Report (continued)
*********************************************************************************
Pulse Data Per Xnet
*********************************************************************************
XNet
PulseFreq PulseDutyCycle PulseCycleCount
--------------------- --------- -------------- --------------1 memory WP
50MHz
0.5
1
1 memory UN4CAP226PA0 50MHz
0.5
1
1 memory UN4CAP225PA0 50MHz
0.5
1
1 memory SDA
50MHz
0.5
1
1 memory SCL
50MHz
0.5
1
1 memory SA2
50MHz
0.5
1
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...
*********************************************************************************
Description of abbreviations
*********************************************************************************
Column
Description
------------ ---------------------------------------------------------HSEvenXtalk
Crosstalk, Rise Stimulus to Neighbors and Victim held High
HSOddXtalk
Crosstalk, Fall Stimulus to Neighbors and Victim held High
LSEvenXtalk
Crosstalk, Fall Stimulus to Neighbors and Victim held Low
LSOddXtalk
Crosstalk, Rise Stimulus to Neighbors and Victim held Low
Victim Drvr
Victim Driver Pin
Victim Rcvr
Victim Receiver Pin
Victim XNet
Victim Extended Net
------------------------------------------------------------------------
Report Computations
Crosstalk is the magnitude of the voltage change seen at a pin on a victim net where the
voltage change is induced by signals on coupled neighboring aggressor xnets when drivers
on aggressor nets are switching.
The crosstalk measurement for a victim net held in the high state is taken as the magnitude
of the difference between the lowest excursion of the receiver waveform minus the victim net’s
steady state voltage. The crosstalk measurement for a victim net held in the high state is
taken as the magnitude of the difference between the victim net's steady state voltage minus
the lowest excursion of the receiver waveform.
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Crosstalk measurements for victim nets in both the high and low states are shown in the
following figure.
Crosstalk Measurement Points
Electrical Constraints
The following constraints can be set on a net or on a pin-to-pin connection for evaluation
during delay analysis
.
Table 5-30 Measures Delay Value Comparisons
Constraint
Definition
Format
MAX_XTALK
Limits the total crosstalk on a victim
net from all aggressor nets.
maximum value:minimum value
MAX_PEAK_XTAL Limits the crosstalk on a victim net
K
from a single aggressor net.
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Analyzing to Generate Waveforms
When signal integrity problems are detected in a critical net, waveforms are often used to
diagnose the root causes. SigWave is an oscilloscpe emulator that can be used to display the
waveforms resulting from your simulations.
When you perform analysis for signal integrity or EMI emissions by creating and viewing
waveforms, SigNoise performs the necessary simulations based on specifications you make
in the Signal Analysis and Analysis Waveform Generator dialog boxes.
Having both dialog boxes open together, you can move back and forth between them,
selecting nets and pins for analysis in the Signal Analysis dialog box and specifying
simulation details in the Analysis Waveform Generator dialog box.
After examining the resulting waveforms in the SigWave window, you can refine your net and
pin selections and simulation details, change simulation preferences (if necessary), and
perform more specific analyses to pinpoint problem signals for a more refined analysis.
To begin waveform based analysis:
➤
Click Waveforms in the Signal Analysis dialog box. For details, see Figure 5-12 on
page 156.
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The Analysis Waveform Generator dialog box is displayed, as shown in the following
figure.
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In the Signal Analysis dialog box you can:
■
Select nets and pin pairs for analysis. For details, see “Selecting Nets and Pins for
Simulation” on page 158.
In the Analysis Waveform Generator dialog box you can:
■
Select a simulation tab to perform one of five types of simulations: Reflection,
Comprehensive, Crosstalk, SSN, or EMI Single.
■
Specify simulation details
■
❑
Select a simulation case
❑
Select the stimulus (choices vary between simulation types)
❑
Select the Fast/Typical/Slow Simulation speed mode
❑
Select the Victim nets and drivers
❑
Select the Aggressor net switching mode (for Crosstalk and Comprehensive
simulations) and Aggressor nets and drivers (for Crosstalk simulations)
❑
Select whether or not to save circuit files or use timing windows (for Crosstalk
simulations)
Specify additional information for a standard report
❑
Select one of ten standard report types to produce
❑
Select the Aggressor nets, drivers, and switching mode
❑
Specify the type of simulation (Reflection, Comprehensive Odd, Comprehensive
Even, or Comprehensive Static) to perform and the stimulus to apply (Pulse or Rise/
Fall)
■
Create the waveforms
■
After reviewing waveforms, open the Analysis Preferences dialog box to modify
simulation preferences to further refine the waveforms resulting from subsequent
simulations.
■
View selected waveforms
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Specifying the Simulation Type
Select one of the five tabs in the Analysis Waveform Generator dialog box to determine the
type of simulation performed to generate the waveforms.
■
Use the Reflection tab to perform You can generate t simulations .
■
Use the Comprehensive tab to perform Comprehensive simulations .
■
Use the Crosstalk tab to perform crosstalk simulations .
■
Use the SSN tab to perform simultaneous switching noise simulations .
■
Use the EMI Single tab to perform EMI single net simulations .
Reflection Simulations simulate only the victim net and none of the neighboring aggressor
nets. Reflection simulation does not take the parasitics of power and ground pins into
account.
Comprehensive Simulations simulate the specified victim net and its neighboring
aggressor nets at the same time. In Comprehensive simulation, SigNoise applies the stimulus
type you select to the victim net and either the same or the opposite stimulus to the
neighboring aggressor nets depending on the switch mode you specify. Comprehensive
simulation takes power and ground parasitics into account. It also shows glitches in the victim
net that are produced by activity on the aggressor nets.
Crosstalk Simulations simulate one or more specified victim nets and one or more
neighboring aggressor nets at the same time.
Specifying All/Group Neighbors for aggressor nets shows how activity on the specified
aggressor nets can cause crosstalk on the victim nets. With a stimulus type of Rise or Pulse,
SigNoise holds the victim nets high and applies a Fall or Inverted Pulse stimulus to the
neighboring aggressor nets. With a stimulus type of Fall or Inverted Pulse, SigNoise holds
the victim nets low and applies a Rise or Pulse stimulus to the neighboring aggressor nets.
Specifying Each Neighbor isolates crosstalk contributions from individual neighboring
aggressor nets. In each neighbor crosstalk analysis, SigNoise runs multiple simulations
where in each simulation, a single aggressor net is active while the other neighboring nets
are passive (held in the same state as the victim net). With a stimulus type of Rise or Pulse,
SigNoise holds the victim nets high and applies a Fall or Inverted Pulse stimulus to the
neighboring aggressor nets. With a stimulus type of Fall or Inverted Pulse, SigNoise holds
the victim nets low and applies a Rise or Pulse stimulus to the neighboring aggressor nets.
SSN Simulations examine what happens when all the drivers on a device that use the same
power and ground bus as the driver in the selected victim nets trigger simultaneously, causing
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power and ground bounce. SigNoise monitors the ripple at the internal power and ground
buses and takes them into account in the analysis of the extended net (or Xnet).
EMI Single Simulations
Performs a Reflection simulation for a single net to evaluate the differential mode radiated
emissions for the net.
Common Tab Areas
The following tables describe the common sections and buttons for all tabs.
Table 5-31 Common Tab Sections
Section
Function
Current Case
The name of the current case including a pulldown menu of
available cases from which you can select to report on.
Stimulus
The current stimulus type including a pulldown menu of available
stimulus choices. Choices are Pulse, Rise, Fall, Rise/Fall and
InvertedPulse.
Check boxes to specify one or more speeds at which SigNoise will
run simulations. Fast/Slow and Slow/Fast refers to speeds of
driver/receiver combinations.
Pull down menus for selecting victim net(s) to be monitored
during simulation and selecting victim net driver(s) to be
stimulated when victim nets are held in the high state.
Fast/Typical/Slow
Mode
Victim
Save Circuit Files
A check box to indicate if SigNoise will save resulting tlsim and
Spice circuit files in the case directory for each simulation
performed.
Table 5-32 Common Tab Buttons
Button
Function
Create Waveforms
Starts report generation using the selections you specified in the
both the Signal Analysis and Report Generator dialog boxes.
View Waveform
Opens the SigWave window and loads the waveform file selected
from the listbox.
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Table 5-32 Common Tab Buttons
Button
Function
Preferences
Displays the Analysis Preferences dialog box enabling you to
modify simulation preferences as you specify simulations and
generate waveforms.
Optional Tab Sections
The following table describes the optional sections found only on the Comprehensive and/
or Crosstalk tabs.
.
Table 5-33 Optional Tab Sections
Section
Function
Aggressor
Pull down menus for selecting switch mode, net selection and
driver selection.
A check box to specify that SigNoise use timing window properties
to refine the crosstalk simulations to account for received crosstalk
that is insignificant due to the timing of signals.
Use Timing Windows
Displaying and Interpreting Waveforms
The SigWave window is SigNoise’s waveform viewer. Its primary purpose is to display
response waveforms from circuit simulations. SigWave is also used by other applications that
require waveform display. For example, using SigWave you can display IBIS VI and VT
transfer curves.
To display a waveform in the SigWave window:
1. Select a waveform file from the listbox in the Analysis Waveform Generator dialog box.
2. Click View Waveform. The SigWave window appears displaying the selected waveform.
The SigWave window with a sample waveform is shown in the following figure.
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Figure 5-16 The SigWave Window
For more detail on displaying and interpreting waveforms, see SigWave in the online help.
Conductor Cross Sections
The Conductor Cross Section window (sigxsect) allows you to view the geometry of
Interconnect Models and the equipotential field lines between the cross sections of
interconnect.
To view interconnect cross section geometry:
1. Select a net from the listbox in the Signal Analysis dialog box.
2. Click View Geometry in the Signal Analysis dialog box. For details, see Figure 5-12
on page 156.
The sigsect window with a sample conductor cross-section is shown in the following figure.
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Figure 5-17 The sigxsect Window
For more detail on viewing interconnect models, see sigxsect in the online help.
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Crosstalk Timing Windows
■
“Overview” on page 224
■
“Crosstalk False Alarms” on page 224
■
“Crosstalk Timing Properties” on page 226
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Crosstalk Timing Windows
Overview
Crosstalk timing windows are a set of timing properties that specify either intervals of time
during which nets (crosstalk aggressors) are actively switching or intervals when nets
(crosstalk victims) are sensitive to crosstalk. Using crosstalk timing windows increases the
accuracy of crosstalk analysis by taking inter-signal timing into account. This reduces
pessimistic crosstalk false alarms by not allowing the effects of out-of-phase aggressor nets
to be combined on victim nets.
Crosstalk False Alarms
When you do not use crosstalk timing windows, your simulation can present overly
pessimistic crosstalk information (false alarms) that would never occur during the normal
operation of the design. If you respond to crosstalk false alarms by separating interconnect
lines to prevent these false problems, you might overconstrain the design and lose routing
channels.
In the following cases you can prevent crosstalk false alarms by using crosstalk timing
windows to preclude:
■
Crosstalk falsely reported on a victim net caused by activity on a neighboring aggressor
net during a time interval when the victim net is not vulnerable to crosstalk.
■
Crosstalk falsely reported on a victim net caused by activity on multiple neighboring
aggressor nets during a time interval when activity on the aggressor nets does not
overlap to create significant crosstalk on the victim net.
The timing diagram that follows shows a clock cycle and the activity you might expect on
victim net named DATA and an aggressor net named NEIGHBOR.
S0
S1
S2
S3
S0
S1
S2
S3
CLOCK
stable
in-transition
NEIGHBOR
stable
in-transition
DATA
Based on this diagram, you can assume the following:
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Crosstalk Timing Windows
■
DATA is only sensitive to crosstalk when it is stable.
■
NEIGHBOR can only generate crosstalk on DATA when NEIGHBOR is in transition.
■
DATA is never sensitive to crosstalk when NEIGHBOR can generate it.
By using crosstalk timing windows you can specify time intervals when NEIGHBOR
generates crosstalk and time intervals when DATA is susceptible to crosstalk. With crosstalk
timing windows, SigNoise can detect when the time intervals overlap to produce crosstalk. In
this case SigNoise reports no crosstalk on DATA. Without using crosstalk timing windows,
SigNoise might falsely report crosstalk on DATA generated by NEIGHBOR.
The following diagram shows two cases of how the voltages at three probe points in a layout
would appear in a scope.
Case 1 is the worst-case example. Neighboring drivers D2 and D3 are simultaneously
creating crosstalk. The crosstalk at XTALK1 is the sum of the crosstalk generated by D2 and
D3.
In case 2 the drivers do not transition simultaneously so the crosstalk at XTALK1 is not the
sum of the crosstalk generated by D2 and D3.
By using crosstalk timing windows you can specify different transition times for D2 and D3. If
you do not use crosstalk timing windows, SigNoise does not know transition times and reports
crosstalk based on the possibility of a simultaneous transition in D2 and D3.
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Crosstalk Timing Windows
The following timing diagram shows the bits of a data bus and the clock cycle for read and
write operations on that bus.
READ/ WRITE
in-transition
stable
in-transition
stable
DATABUS1
DATABUS2
DATABUS3
DATABUS4
...
In this example, receivers read data on the rise of the clock cycle and drivers write on the fall
of the clock cycle. Drivers write to all bits simultaneously. All crosstalk between the bits in this
bus occurs during the in-transition write operation. In this case, crosstalk between the bits is
irrelevant.
A bus is often routed in a tight group so the coupling, and therefore the potential for crosstalk,
among bits is high. With crosstalk timing windows you can instruct SigNoise to ignore
crosstalk among bits. Without crosstalk timing windows, SigNoise reports the crosstalk
among bits in the most pessimistic fashion.
Crosstalk Timing Properties
You can solve the crosstalk timing problem by providing relative timing information as values
for the three properties shown in the following table
Table 6-1 RelativeTiming Properties
Property
Description
XTALK_ACTIVE_TIME
Specifies the times during which a net can generate
crosstalk on a neighbor net. If a net has no attached
XTALK_ACTIVE_TIME property, SigNoise assumes that the
net can generate crosstalk at all times. See “Specifying
Crosstalk Activity” on page 227.
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Crosstalk Timing Windows
Table 6-1 RelativeTiming Properties
Property
Description
XTALK_SENSITIVE_TIME
Specifies the times during which a net is susceptible to
crosstalk from its neighbors. If a net has no attached
XTALK_SENSITIVE_TIME property, SigNoise assumes that
the net is susceptible to crosstalk at all times. See
“Specifying Crosstalk Sensitivity” on page 227.
XTALK_IGNORE_NETS
Specifies that a net is never susceptible to crosstalk from the
specified nets. See “Specifying Ignore Crosstalk” on
page 228.
When you attach these properties to a net, you can specify times when the net is susceptible
to crosstalk generated by neighboring nets, times when the net can generate crosstalk on
neighboring nets, and that the net is never susceptible to crosstalk generated by neighboring
nets.
Specifying Crosstalk Activity
To tell SigNoise when a net can generate crosstalk:
➤
Use the XTALK_ACTIVE_TIME property.
You can, for example, assign this property to a net and specify the times when the net
can generate crosstalk.
Note: If you do not assign an XTALK_SENSITIVE_TIME property to a net, SigNoise
assumes that the net can generate crosstalk at all times.
Specifying Crosstalk Sensitivity
To tell SigNoise when a net is susceptible to crosstalk:
➤
Use the XTALK_SENSITIVE_TIME property.
You can, for example, assign this property to a data net and specify its setup and hold
times as the times when this net is susceptible to crosstalk.
Note: If you do not assign an XTALK_SENSITIVE_TIME property to a net, SigNoise
assumes that the net is always susceptible to crosstalk.
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Crosstalk Timing Windows
The values for the XTALK_SENSITIVE_TIME property are single values, or ranges of values.
You separate the values and ranges of values with commas. You specify ranges with a
hyphen between the start and end values of a range. The following is an example of
simulation time values for this property.
150-175, 400, 450-475
You can specify only positive integers as values. SigNoise ignores tabs and spaces. You
cannot include alphabetic or special characters in these values.
You can specify NONE to tell SigNoise that the net is never susceptible to crosstalk.
Specifying Ignore Crosstalk
To tell SigNoise not to look for crosstalk on certain nets
➤
Use the XTALK_IGNORE_NETS property.
You can, for example, use this property on the bits of a synchronous data bus where
there is no functional crosstalk between bits.
When you assign the XTALK_IGNORE_NETS property to the nets in a bus, the bus is routed
with minimum spacing instead of separating the bits and blocking routing channels to avoid
crosstalk between the bits.
The XTALK_IGNORE_NETS property values are net names and Electrical Constraint Set
(ECSet) names. You separate these names with commas.
If a name value matches a net name, SigNoise ignores the net in crosstalk analysis. If a name
matches an Electrical Constraint Set name, SigNoise ignores all nets using that constraint set
in crosstalk analysis.
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Properties
■
“Overview” on page 230
■
“Attaching and Editing Properties” on page 230
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Properties
Overview
SPECCTRAQuest and Allegro/APD have a set of predefined properties that can be attached
to design elements. You can attach properties to elements in a design to instruct
SPECCTRAQuest or Allegro/APD on how to operate on those elements. For example, a net
with the NO_GLOSS property attached is not affected by the Allegro/APD glossing router.
Different Cadence applications use different properties.
You can attach properties:
■
directly to a design element in SPECCTRAQuest or Allegro/APD.
■
to a Concept schematic that you would import into Allegro/APD.
■
through a third-party netlist that you would import into Allegro/APD.
Attaching and Editing Properties
You can attach and edit properties on the elements listed in the following table:
Table 7-1 Design Elements that Accept Properties
CLINES
LINES
COMPONENTS
PIN DEFINITIONS DEFINITIONS
PINS
DRCS
RECTANGLES
FIGURES
SHAPES
FRECTANGLES
SYMBOLS
FUNCTION
VIAS
FUNCTIONS
VOIDS
LAYOUT (a property
attached to the entire
design)
GROUPS
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Properties
To attach or edit element properties:
1. Select the option shown in the following figure from the main menu of either the
SPECCTRAQuest Floorplanner or Allegro/APD.
2. Click the element in the design which you want to attach the properties to.
The element is highlighted; the Edit Properties and Show Properties dialog boxes are
displayed as shown in the following figure. The Show Properties dialog box lists any
properties which have been previously associated with the selected design element.
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Properties
Figure 7-1 The Edit Property Dialog Box
3. Click on the desired property to be attached or edited from the Available
Properties list box in the Edit Property dialog box. As an option, you can also enter
a valid property name in the Name field. The property is displayed on the right side of
the dialog box.
4. If desired, change the value of a property using its Value box or delete a property by
clicking (check) its Delete box.
5. Click Apply to associate the new property list with the element. The new properties are
displayed in the Show Properties dialog box.
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EMI and Power Plane Modeling
■
“Overview” on page 234
■
“Power Plane Builder” on page 234
■
“The EMWave Window” on page 235
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EMI and Power Plane Modeling
Overview
One of the most important considerations in the design of any high-speed system is its power
and ground structure which is usually realized as a pair of power and ground planes. Digital
engineers often assume that the ground plane is a zero-volt reference and that the VCC plane
is 5-volts. However, in a high-speed system this is seldom the case. While the copper planes
on a printed circuit board (PCB) offer a lower impedance than that offered by the power and
ground bus, the copper planes still have a finite, non-zero impedance. As such, the currents
resulting from high speed switching as well as the return currents resulting from high-speed
clocks and signals, cause the reference voltages of these planes to vary considerably across
the board.
Power Plane Builder
The Power Plane Builder provides the design engineer with the ability to manage the effects
of one of the primary sources of common-mode noise between the power and ground planes,
RF hot-spots in the ground plane caused by high-speed switching. Switching events can
occur in less than a nanosecond and contain spectral components that reach into the
microwave spectrum.
Briefly, here’s how RF hot spots occur. When a device switches, it draws current from a
source (in this case, the power plane, or more correctly, the decoupling capacitors servicing
the device on the power plane) and the current flows down a via to the ground plane. As this
sudden surge of current travels down the via, the via behaves like a tiny antenna by emiting
an electric field which propagates outward from the via between the power and ground
planes, inducing a voltage between the planes.
For the Fourier components of the switching event that are higher in frequency than the
natural resonant frequency of the power and ground plane pair (this resonant frequency is a
function of the length and width of the planes as well as the dielectric constant of the material
between them) the planes appear as an electrically large resonant structure. As with any
large resonant structure, there are high-order waveguide-type modes that can be excited.
These high-order modes are the hot-spots in the ground plane that EMC engineers have
come to recognize as problems. It is these types of problems that cause common-mode
radiated emissions from I/O and power cables or degradation in a chip’s signal integrity. It is
this behavior that Power Plane Builder displays in a three dimensional animation in EMWave.
Preparing the PCB Early in the Design Process
Using the Power Plane Builder, you can begin to deal with high speed switching problems by
characterizing the behavior of the power and ground plane pair early in the design cycle.
During the early exploration phase of a design, you may have only an idea of what the board
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geometry is going to be and the type of devices that are going to be used. Even so, this
information is sufficient to provide meaningful answers about how the board’s power and
ground plane structure is going to behave under the influence of high-speed switching.
Before using Power Plane Builder on a board where you have already placed chips and
defined the layering stackup, ensure that the VOLTAGE property is attached to the DC nets
(for example, VCC and GND) and identify a voltage source pin for both the power and ground
nets. This effectively designates the driving source for the current switched through the via
that causes the noise in the power and ground planes. You can both define the voltage
properties and identify the voltage source pins in SPECCTRAQuest using the Netlist –
Identify DC Nets command.
Before you simulate, make sure that:
■
the power and ground planes are defined. This is usually done in Allegro/APD by the
PCB designer.
■
the parts you want to analyze have their power and ground connections fanned out and
connected to the power planes. This can be done in either Allegro/APD or
SPECCTRAQuest.
Creating vias early on the design process enables the Power Plane Builder to more
accurately predict the plane noise. Vias can have the effect of breaking up traveling modes in
the planes. Further, if there is no ground via defined, the Power Plane Builder is going to
assume the PCB ground point to be at the 0,0 coordinate.
Preparing to Examine Ground Bounce in EMWave
Perform an SSN simulation with the Do Plane Modeling option selected on the
Interconnect Models tab of the Analyse – SI/EMI Sim – Preferences dialog box. The
waveforms list box at the bottom of the SSN tab of the Analysis Waveform Generator
dialog box will display two files for each simulation: simx.map and simx.sim.
■
Use the simx.map file to display a ground bounce movie depicting a time domain,
animated view of the ground bounce surface as it developed throughout the simulation.
For details, see “To display a ground bounce movie:” on page 239.
■
Use the simx.sim file to display the Voltage vs. Time waveform for the simulation. For
details, see “To display the corresponding time-domain waveform:” on page 239.
The EMWave Window
The EMWave window is a three-dimensional viewer for display of time domain, animated
ground bounce waves propagating between power and ground planes on a printed circuit
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board (PCB). EMWave displays ground bounce waves in boards having one pair of power and
ground planes. Components and decoupling capacitors are superimposed on the ground
bounce movie to assist you in assessing their effectiveness. EMWave can also operate in
noise map mode for display of a static image of the RF hot spots which occurred during the
simulation.
The EMWave window is comprised of the four areas shown in the following table
.
Table 8-1 EMWave Window Areas
Area
Function
Display Window
Displays the ground bounce surface in time-domain, animated movie
or in a static noise map view.
Menu Bar
Provides menu commands to operate the viewer.
Tool Bar
Provides icons to run the movie and adjust the display window.
Status Bar
Displays an informational message.
The following figure shows the EMWave window with a ground bounce movie displayed.
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Figure 8-1 The EMWave Window
The following tables describe the menu options and toolbar buttons in the EMWave window.
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Table 8-2 EMWave Window - Menu Options
Option
Function
File – Open
Opens a waveform (.sim) file created by a SSN simulation with the
Do Plane Modeling option active.
File – Exit
Closes the EMWave window.
View – Toolbar
Toggles toolbar display.
View – Status Bar Toggles status bar display.
Help – Topics
Displays this help file.
Help – About
Displays the revision of the EMWave program.
Table 8-3 EMWave window - Toolbar Buttons
Button
Function
Play
Toggles Play animation mode on and Pause off. Plays the ground
bounce movie.
Pause
Toggles Play off and Pause on. Pauses display of the ground
bounce movie.
X, Y, Z rotation
Toggles rotation of the movie on and off around the X, Y, or Z axes.
Zoom In
Moves your viewpoint closer to the display, magnifying your view of
the ground bounce surface.
Zoom Out
Moves your viewpoint further away from the display, widening your
view of the ground bounce surface.
About
Displays the revision of the emwave program.
Mesh
Toggles between solid and mesh mode for display of the ground
bounce surface. In solid mode, the ground bounce surface appears
as a solid sheet. In mesh mode, the surface appears as a mesh of
polygons.
Reset
Restores the original viewpoint.
Movie
Toggles between the default animation mode and a static noise map
mode. Noise map mode displays only the hot spots that occur during
the simulation.
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To display a ground bounce movie:
1. Click to select the simx.map file in the waveforms list box on the SSN tab of the
Analysis Waveform Generator dialog box.
2. Click the View Waveform button.
The EMWave window appears with the first frame of the ground bounce movie displayed
as shown in the following figure.
3. Click Play (the triangle) in the EMWave toolbar to start the movie.
4. Click Pause (to the right of Play) to pause the movie.
To display the corresponding static noise map:
1. Click to select the simx.map file in the Waveforms list box of the Signal Analysis
(casex) dialog box.
2. Click View Waveform.
The EMWave window appears with the first frame of the ground bounce movie
displayed.
3. Click Movie/Map (the icon furthest to the right) in the EMWave toolbar to display the
static noise map view.
To display the corresponding time-domain waveform:
1. Click to select the simx.sim file in the Waveforms list box on the SSN tab of the
Analysis Waveform Generator dialog box.
2. Click View Waveform.
The SigWave window appears with the waveform displayed.
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9
Multi-Board Designs (Systems)
Topics in this chapter include
■
“System-Level Simulation” on page 242
■
“Modeling Strategies” on page 244
■
“Working with System Configurations” on page 245
■
“Setting Constraints at the System-Level” on page 251
■
“System-Level Simulation” on page 252
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System-Level Simulation
A design is a board file (.brd) in SPECCTRAQuest, Allegro or APD. A system consists of
all participating designs, along with the interconnecting cables and connectors. For example,
a system may consist of a motherboard, a power supply, a cooling fan, and several plug-in
cards such as a video controller, a sound card, and RAM modules.
With system-level simulation, you analyze an extended net (system-level Xnet) that spans
more than one design. The simulation takes into account the path through all the designs in
the system and the connectors and cables that connect these designs.
What is a system configuration?
A system configuration file (.scf) is a database representation of all the participating designs,
including interconnecting cables and connectors, that comprise the system. The system
configuration also includes the Xnets and pin-pairs that traverse a system and their assigned
constraint values.
A system configuration represents the electrical characterization of a system. For example, a
motherboard may have four slots for memory modules. If two of these slots are populated,
then that is considered a system configuration. If four of these slots are populated, then that
is considered an entirely different system configuration.
As another example, if only the first memory slot is populated, moving the memory module to
the fourth slot is considered a change in the system configuration because the trace to the
fourth slot is further from the signal source than the trace to the first slot.
For each permutation of memory modules (1 through 4, populated or vacant) there is a
different system configuration. You can constrain each of these unique configurations as a
different system configuration database. A final example is swapping out the cable that
connects one design to another. If it is swapped for another cable, perhaps a longer one, then
this is considered a change in the system configuration.
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Eventually the design or board the file (.brd) can be constrained such that any system
configuration meets the system level constraint requirements.
With system configuration database, you can:
■
Switch between various system configurations without loss of information.
■
Use a single system configuration database for multiple participating design databases.
■
Use Constraint Manager to manage system-level constraints.
■
Preserve system-level constraints, system pin-pairs, and system Xnets from one project
session to the next.
What is a DesignLink?
To simulate a design (in a system of designs), you must specify the designs in the system and
how to connect the designs together. To do this, you use a DesignLink. A DesignLink is a type
of model that specifies both a set of connections and the other designs to which you make
connections. Each system configuration file is established (seeded) from a DesignLink.
Once the system configuration is established (or activated), it is saved to a system
configuration database file (.scf) which then keeps the system connectivity in the database
format. At this point, the DesignLink is no longer used.
What is a cable model?
A cable model represents the parasitics of the cable running between multiple designs. A
cable model is similar to a PackageModel; both contain RLGC matrices (or circuit models).
However, you insert a cable model into a DesignLink and you insert a PackageModel into an
IbisDevice model.
You can edit any existing cable model that has been created and added to a Library. If you
created the model by cloning (or copying) an existing model, you need to edit the cloned
model so that it characterizes the device you are modeling. If you created the model from
scratch, it will contain default values that you may want to edit.
Note: Cadence recommends that you create new cable models by cloning an existing cable
model from the sample library and editing that copy to characterizes the cable which you are
modeling, rather than by building a cable from scratch.
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Modeling Strategies
A typical system configuration might consist of two printed circuit boards, PCB1 and PCB2,
two mated connectors and a cable. A connector is typically made up of a plug and a
receptacle. In this scenario, one receptacle is mounted on PCB1, the other receptacle is
mounted on PCB2, and the two plugs are mounted on the ends of the cable.
The following approach was taken to model this multi-board system:
■
A PackageModel is used to represent the parasitics of a mated connector (plug and
receptacle).
You assign a PackageModel on the board and include the parasitics of both the
receptacle and the plug.
■
An IBISDevice model is generated for each connector on the board, then a
PackageModel is inserted into each IBISDevice model.
When you create an IbisDevice model for a Connector, make sure that you do not assign
any buffer models to connector pins. This way all connector pins will have the UNSPEC
pinuse, which is required for the correct simulations.
In this scenario, identical connectors are used on both PCBs.
■
An RLGC model is used to represent the parasitics of the cable running between the two
boards.
■
A DesignLink model is generated to specify the system-level connections between the
two boards.
The RLGC model is inserted into the DesignLink model.
Use the following guidelines when employing a modeling strategy:
Modeling Common Multi-Board Configurations
To model...
Use...
PCBs connected through a cable, with a
connector on the PCBs at each end of the
cable.
Represent the connectors on the PCBs as a
PackageModel within an IBIS device model.
Represent the cable as an RLGC model
within a DesignLink model. Always set the
PINUSE for connector pins to UNSPEC.
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To model...
Use...
Daughter boards with gold fingers plugged
into a card-edge connector on a backplane.
Represent the connector as an RLGC
model within a DesignLink model. Do not
make IBIS device models for the connectors
on the PCBs; set their PINUSE to
UNSPEC.
An MCM in a Pin-Grid-Array (PGA) package
plugged into a PCB.
Model the pins of the PGA in an RLGC
model within a DesignLink model. Do not
make IBIS device models for the thru-holes
on the PCB; set their PINUSE to UNSPEC.
Working with System Configurations
The following sections describe how to use system configurations.
Establishing a new System Configuration
A new system configuration is established with a DesignLink model. It specifies both the
participating designs and how they are connected. The following steps guide you through the
process.
1. From Allegro/APD, SPECCTRAQuest, or Constraint Manager, choose Analyze–
SI/EMI Sim–Library).
The Library Browser appears.
2. In the Signal Analysis Library Browser dialog box, click Browse Models.
The Model Browser appears.
3. Click Add Model.
4. Select DesignLink from the pop-up menu
A dialog box will appear for you to name the new DesignLink.
5. Enter a name for the DesignLink.
6. Click Edit.
The System Configuration Editor appears with all fields empty.
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Figure 9-1 System Configuration Editor dialog box
7. Complete the configuration as described in the System Configuration Editor Controls
table on page 247.
8. Once the DesignLink model is established, it can be used to create a new system
configuration. See “Choosing among existing System Configurations” on page 249 for
more information.
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Table 9-1 System Configuration Editor Controls
Click this button
To perform this operation
Drawings Fields
Add File
Add a board file (design) to the system configuration
Add BoardModel
Add a BoardModel to the system configuration (a design can be
represented in the abstract as an electrical BoardModel)
Remove
Remove a design from the system configuration
Set Design Name
Add a label to the selected design name
Set Drawing Path
Specify a path to the selected design name. You can, in effect,
instantiate the same design many times with reference to a single
board file (.brd). You give each derivative a unique label. For
example, a memory module of the same design may be
instantiated in a system.
Connections Fields
Add
Name a connection between participating designs in the system
configuration.
Remove
Remove a connection between participating designs in the
system configuration.
Copy
Clone an existing connection between participating designs in the
system configuration.
Set Length
Specify a cable length in meters. Use zero for plug-in boards.
Set Cable Model
Specify a cable model from the library.
Connections
PinMap Fields
Add
Add new pin connections to the selected cable connection.
Presents a series of dialog boxes to collect information on the
first wire number, the number of wires, and the starting pin (at
either end of the connections).
Remove
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Remove the selected pin connections from the selected cable
connection.
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Table 9-1 System Configuration Editor Controls
Click this button
To perform this operation
Set From Pins
Presents a dialog box for you to select the starting pin at one end
of the cable connection
Set to Pins
Presents a dialog box for you to edit the starting pin at the other
end of cable connection
TextEdit PinMap
Opens the entire pin connection map in a text editor for further
manipulation.
Note: The system configuration name is saved as a property (SYS_CONFIG_NAME) within
the board database. If the board file is moved from one place to another, the system
configuration name follows the board file. The system configuration does not have to be
moved as long as it is available in the system configuration path (as defined by SCFPATH
environment variable).
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Choosing among existing System Configurations
➤
From Allegro/APD, SPECCTRAQuest, or Constraint Manager, you can choose from
existing system configurations in the Signal Analysis Initialization dialog box (Analyze–
SI/EMI Sim–Initialize).
Figure 9-2 Multiple System Configurations
The System Configuration pull-down menu shows all available system configuration (.scf)
files as well as all available DesignLink models which use the currently opened Allegro board
(.brd) file.
Of the available system configurations there is the Single Board System. This is the default
system configuration. Single board system uses a single design or board file (without other
participating designs). A system configuration database file is not produced when choosing
Single Board System.
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When a system configuration is chosen (and activated by clicking OK), the system
configuration is checked. If there are any errors with the chosen system configuration, the
previous system configuration is restored.
When a DesignLink model is chosen (and activated by clicking OK) with only one
participating design, the DesignLink is ignored and the previous system configuration is
restored. If the DesignLink model contains multiple participating designs, a new system
configuration is created (with same name as the DesignLink model). The previous DesignLink
model can still be cloned or used to seed a different system configurations.
Important
The only way to create new system configuration is to create a new DesignLink
model (either from scratch or by cloning an existing DesignLink model), and then
choosing the DesignLink model, as a system configuration, from the pull-down
menu in the Signal Analysis Initialization dialog box (see “Multiple System
Configurations” on page 249).
Note: The system configuration path is determined by an Allegro environment variable
SCFPATH which is, by default, set to the current working directory.
Modifying an existing System Configuration
To modify an existing system configuration, select a system configuration from the drop-down
menu of the System Analysis Initialization dialog box (see “Multiple System Configurations”
on page 249), then click Edit System Configuration. The system configuration must be
activated before it can be edited
Make changes to the selected system configuration through the System Configuration Editor
as described in the System Configuration Editor Controls table on page 247.
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Setting Constraints at the System-Level
You can set a constraint directly on a system-Xnet in your layout or you can define the
constraint in Constraint Manager as an ECSet and then reference it to a system-Xnet.
When a board is removed from a system configuration and accessed as a single board, it is
desirable to maintain as much as possible the constraints that were set at the system-level.
Therefore, when a constraint is set on a system-Xnet, the relevant system constraints will be
copied to each net and design-Xnet in the system-Xnet. The source of these design-level
constraints will be marked as system-level, so it will be possible to delete it when the board
is included in a different system configuration. When the board is opened as a single board,
the constraints that were copied from the system-level constraints will remain in the design.
Electrical constraints will be assigned to a system-Xnet as follows:
■
Each non pin-pair based constraint will be copied to every net and design-Xnet in the
system-Xnet as a property override unless the net or design-Xnet already has a defined
constraint value. In this case, the worst-case constraints from the net or Xnet and system
Xnet is chosen.
■
For pin-pair based constraints (Min First Switch, Max Final Settle,
Propagation Delay, Relative Propagation Delay, Impedance), all autogenerated pin-pair rules will be copied to each net and design-Xnet in the system-Xnet.
Any user-defined pin-pair rules on a single design will be copied and flattened to the
design that it references. Those pin pairs that reference pins on different designs will be
saved as system pin-pairs.
Most of the constraints that are set on system-Xnets will be copied to the member nets and
design-Xnets, and will be shown in a Constraint Manager worksheet on both system- and
design-Xnets. The actual values displayed in the worksheet will correspond to the object. For
example, the net level Max Vias constraint will show an actual value that is the total number
of vias in the net. The actual value displayed for a system-Xnet will be the total number of vias
in the system-Xnet.
Note: If any design-Xnet is part of a bus or a diff pair object, the system-Xnet will also be part
of that bus or diff pair. You do not have to define same bus or diff pair objects in all designs.
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System-Level Simulation
After you have created your system configuration, you can proceed to simulate nets that span
multiple designs. When you model for multi-board analysis, consider these basic concepts:
■
The simulator automatically models the parasitics for interconnect structures produced
during routing (for example, traces and vias).
■
Interconnect structures that are not created during routing (for example, packages,
connectors, and cables), are represented by RLGC matrices or circuit models, either
directly in an RLGC model (as in a DesignLink model) or in a PackageModel (as in a IBIS
device model).
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A
Modeling in the Interconnect Description
Language
■
“Overview” on page 254
■
“IDL Interconnect Line Segment Models” on page 254
■
“IDL Via Models” on page 267
■
“IDL Shape Models” on page 273
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Modeling in the Interconnect Description Language
Overview
The Interconnect Description Language (IDL) is the language used by both SigNoise and
device model developers. The language is an extension of Spice and consists of control
characters, keywords, and values. SigNoise uses IDL to write models for the connect line
segments, vias, shapes, and pins in designs. You can modify these models. Device model
developers use IDL to write models for
■
Packages. Package models describe the parasitics between a component’s pads and
the die of the device within.
■
RLGC matrices. RLGC models (matrices of resistance, inductance, conductance, and
capacitance values) specify the parasitics in the connections used in system design
links.
■
Passive components. For example, resistors and capacitors.
This appendix describes IDL interconnect models for connect line segments, shapes, pins,
and vias, and shows how you might modify such models.
IDL Interconnect Line Segment Models
IDL interconnect line segment models can describe one or more of the following:
■
Connect lines
■
Connect line segments
■
Parts of connect lines
■
Parts of connect line segments
When you route connect lines within the distance of the geometry window, the resulting
interconnect models describe more than one connect line, connect segment, or part of a
connect segment.
The following figure shows the three interconnect models that SigNoise writes for the
horizontal connect lines and horizontal connect line segments in the illustration.
■
The model on the left describes the left section of the middle connect line.
■
The model in the middle describes both the left section of the connect line segment on
top and the central section of the middle connect line.
■
The model on the right describes the right section of the connect line segment on top,
the right section of the middle connect line, and the connect line segment on the bottom.
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Figure A-1 Interconnect Models for Connect Line Segments
Three
interconnect
models
RLGC Matrix Values in Interconnect Models
Interconnect models contain matrices of resistance, inductance, conductance, and
capacitance (or RLGC) values. The SigNoise field solver calculates and writes these values
into the model.
You might want to edit the RLGC values in line segment models to change how SigNoise
simulates the corresponding connect line segments. To do this, edit the RLGC matrix values
in the .rlgc declaration in the line segment model.
The .rlgc declaration is located toward the end of the model, and contains parasitic value
matrices. The following is an example of an .rlgc declaration.
.rlgc RLGCT_1S_2R_2914 ( Length=length N=2 )
.C 0
+ 6.625200e-11 -4.567200e-12
+ -4.567500e-12 5.729800e-11
.L 0
+ 4.834800e-07 7.706100e-08
+ 7.705900e-08 4.388100e-07
.G 0
+ 0.000000e+00 -0.000000e+00
+ -0.000000e+00 0.000000e+00
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.R 0
+ 3.586500e+00 0.000000e+00
+ 0.000000e+00 1.793200e+00
.endrlgc RLGCT_1S_2R_2914
The .rlgc declaration is a type of sub-circuit inside a sub-circuit that is written into the
model by the field solver.
The declaration includes matrices that specify the self and mutual parasitic values for the
connect lines, segments, and parts in the model and between the connect lines, segments,
and parts.
■
A self value is the parasitic value of an individual connect line, segment, or part with
respect to some reference, such as a ground plane.
■
A mutual value is the parasitic values between connect lines, segments, and parts.
The more connect lines, segments, and parts in a model the larger the size of the matrices in
the .rlgc declaration. A model for a single connect line, segment, or part contains matrices
that specify only the self value of that connect line, segment, or part. A model for two connect
lines, segments, or parts has matrices of two self values and two mutual values. A model for
three connect lines, segments, or parts, such as that in the figure below, has matrices of three
self values and six mutual values.
Figure A-2 Model for Three Interconnect Lines
C
B
A
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The model illustrated in the previous figure describes connect line segments or parts A, B,
and C. The self values in the matrices have the following arrangement in the matrix:
A
B
C
A matrix with the self and mutual values has the following arrangement:
A
A-B
A-C
B-A
B
B-C
C-A
C-B
C
In this matrix A-B is the mutual value between A and B, C-A is the mutual value between C
and A. Mutual values between the same lines, segments, or parts are identical, so the B-C
mutual value equals the C-B mutual value.
.rlgc Declaration Syntax
The syntax of the .rlgc declaration for a model with two lines, segments, or parts is:
.rlgc subcircuit_name (Length=value N=value)
.C frequency_value
+ self_value
mutual_value
+ mutual_value
self_value
.L frequency_value
+ self_value
mutual_value
+ mutual_value
self_value
.G frequency_value
+ self_value
mutual_value
+ mutual_value
self_value
.R frequency_value
+ self_value
mutual_value
+ mutual_value
self_value
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.endrlgc subcircuit_name
The following table shows the keywords and values used in the .rlgc declaration syntax
.
Table A-1 Keywords and Values
.rlgc
A keyword that specifies the beginning of the declaration that
contains the matrices of parasitic values.
subcircuit_name
The SigNoise field solver generates the matrix values as a
special kind of subcircuit of the model and names this
subcircuit. The name is a derivative of the model name.
Length=value
A keyword and value statement that specifies the length of the
connect lines, segments, or parts. The field solver can enter
the keyword length for this value to tell SigNoise to take the
length value from the layout instead of from the model.
N=value
A keyword and value statement that specifies both the
number of lines, segments, or parts modeled and the size of
the matrix. A value of 2, for example, specifies two lines,
segments, or parts, a 2x2 matrix value specifies two self
values and two mutual values.
.C
Specifies a matrix of capacitance values.
.L
Specifies a matrix of inductance values.
.G
Specifies a matrix of conductance values.
.R
Specifies a matrix of resistance values.
frequency_value
Specifies the minimum frequency to which SigNoise applies
the parasitic values in the following matrix.
+
A continuation character that indicates that a line is part of a
declaration started on a previous line.
self_value
The parasitic value of a connect line, segment, or part.
mutual_value
The parasitic value between two connect lines, segments, or
parts.
Example Line Segment Model
The following example shows an IDL model for two neighboring connect line segments. The
sections following the example describe the model according to its functional parts.
.subckt T_1S_2R_2914
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+X1250Y800L1
+X1225Y800L1
+0
+X1250Y2650L1
+X1225Y2650L1
+0
.material sml6 dielectric=4.5 losstangent=0.001
.material sml5 conductivity=5.959e+07 losstangent=0
.material sml4 dielectric=4.5 losstangent=0.001
.material sml3 conductivity=5.959e+07 losstangent=0
.material sml2 dielectric=4.5 losstangent=0.001
.material ml7 conductivity=3.43e+07
.material ml6 dielectric=4.5
.material ml5 conductivity=5.959e+07
.material ml4 dielectric=4.5
.material ml3 conductivity=5.959e+07
.material ml2 dielectric=4.5
.material ml1 conductivity=3.43e+07
.layerstack Layerstack3
+shield( 3.048e-05 1 0 )
+dielectric( 0.0003048 4.5 0.001 )
.crosssection
+rectangle ( 3.43e+07 0 0.0003048 0.0001524 0.00035814 )
+rectangle ( 3.43e+07 0.0005588 0.0003048 0.0008636 0.00035814 )
+Length=length
.rlgc RLGCT_1S_2R_2914 ( Length=length N=2 )
.C 0
+ 6.625200e-11 -4.567200e-12
+ -4.567500e-12 5.729800e-11
.L 0
+ 4.834800e-07 7.706100e-08
+ 7.705900e-08 4.388100e-07
.G 0
+ 0.000000e+00 -0.000000e+00
+ -0.000000e+00 0.000000e+00
.R 0
+ 3.586500e+00 0.000000e+00
+ 0.000000e+00 1.793200e+00
.endrlgc RLGCT_1S_2R_2914
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**The Characteristic Modal Delay, Admittance and
**Impedance Matrices of these Transmission Lines:
*Delay Matrix.
*Td 0 (n=2)
* 5.706200e-09 0.000000e+00
* 0.000000e+00 4.889800e-09
*Admittance Matrix.
*Y 0 (n=2)
* 1.185600e-02 -1.415100e-03
* -1.415100e-03 1.158100e-02
*Impedance Matrix.
*Z 0 (n=2)
* 8.559500e+01 1.045800e+01
* 1.045800e+01 8.762400e+01
.ends T_1S_2R_291
The following sections describe IDL control characters, keywords, and values as you
encounter them from beginning to end in the model:
■
.subckt
■
.material
■
.layerstack
■
.crosssection
■
.rlgc
■
Delay, Admittance, and Impedance
.subckt Declaration
The sample interconnect model begins with the .subckt declaration:
.subckt T_1S_2R_2914
+X1250Y800L1
+X1225Y800L1
+0
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+X1250Y2650L1
+X1225Y2650L1
+0
This declaration specifies that the model is a subcircuit of a circuit that SigNoise simulates. It
specifies the following:
■
Name of the subcircuit, T_1S_2R_2914
■
External nodes of the circuit
+X1250Y800L1
+X1225Y800L1
+0
+X1250Y2650L1
+X1225Y2650L1
+0
The plus sign (+) is a continuation control character that specifies that a line is a
continuation of a declaration in the previous line.
The zeroes in this list of external nodes indicate a reference to a ground plane and
separate the input external nodes from the output external nodes.
To name the subcircuit, SigNoise used
■
The T prefix identifying this as a trace model
■
The 1S component indicating one shield layer found in the trace model
■
The 2R component indicating two rectangular conductors found in the trace model
■
The 2914 component as an arbitrary number to differentiate this model from other trace
models
The following figure shows how SigNoise can write models for a part of a connect line
segment.
Part
P1
Part
P2
Part
P3
In this figure, SigNoise writes a model for the following:
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■
Part P1 of the middle connect line segment and part of the top connect line segment
■
Part 2 of the middle connect line segment as well as part of the top and bottom connect
line segments
■
Part 3 of the middle connect line segment
The external nodes of a model show where the model connects to other parts of the circuit.
The following figure shows the external nodes in the model for Part P1.
External
nodes
External
nos
Part
P1
The subcircuit name is T_1S_2R_2914. This name does the following:
■
Models more than one connect line segment
■
Has an external node at X and Y coordinates 960 and 2460
■
Is on the first layer
■
Includes the first part of the longer connect line segment in the model
To name the external nodes of the subcircuit, SigNoise combined
■
The left most X coordinate of the external node
■
The lowest Y coordinate of the external node
■
The layer of the external node
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The following figure shows how the model appears in the Conductor Cross Section window,
and labels the external nodes.
X960Y2440L1
X960Y2460L1
X980Y2460L1
X980Y2440L1
.material Declaration
After the .subckt section, the next part of the sample model is the .material
declaration.
.material
.material
.material
.material
.material
.material
.material
.material
.material
.material
.material
.material
sml6
sml5
sml4
sml3
sml2
ml7
ml6
ml5
ml4
ml3
ml2
ml1
dielectric=4.5 losstangent=0.001
conductivity=5.959e+07 losstangent=0
dielectric=4.5 losstangent=0.001
conductivity=5.959e+07 losstangent=0
dielectric=4.5 losstangent=0.001
conductivity=3.43e+07
dielectric=4.5
conductivity=5.959e+07
dielectric=4.5
conductivity=5.959e+07
dielectric=4.5
conductivity=3.43e+07
The .material declarations describe the layers in the design. These declarations contain
dielectric coefficients, conductivity, and loss tangent data from the technology file.
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.layerstack Declaration
After the .material section, the next part of the sample model is the .layerstack
declaration.
.layerstack Layerstack3
+shield( 3.048e-05 1 0 )
+dielectric( 0.0003048 4.5 0.001 )
A layerstack is a stack of layers in the design bounded by the surface of the board, a power
plane, or a ground plane. A board can have more than one layerstack. The first layerstack,
Layerstack1, is the stack of layers that begins with the bottom surface of the board and ends
at a power plane, ground plane, or the top surface of the board. The .layerstack
declaration in this model specifies a model of connect lines in the third layerstack from the
bottom, Layerstack3.
This layerstack consists of one shield layer and one dielectric layer because the declaration
contains only one instance of the keywords shield and dielectric. If, for example, the
layerstack contained more than one dielectric layer, the model would have more than one line
beginning with the plus continuation control character (+) and the keyword dielectric.
The values in parentheses that follow the keywords shield and dielectric specify in
the following order:
■
The thickness of the layer
■
The dielectric constant of the layer
■
The loss tangent of the layer
Note: All layers need these three values. SigNoise applies a dielectric constant value of 1 to
a shield layer as a placeholder even though a shield layer has no dielectric constant.
.crosssection Declaration
After the .layerstack section, the next part of the sample model is the .crosssection
declaration.
.crosssection
+rectangle ( 3.43e+07 0 0.0003048 0.0001524 0.00035814 )
+rectangle ( 3.43e+07 0.0005588 0.0003048 0.0008636 0.00035814 )
The .crosssection declaration specifies the geometry of a cross section of the parts on
connect line segments in the model. For each part of a segment in the model there is a line
beginning with +rectangle and, in parentheses, values for
■
The conductivity of the part of the segment
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■
The four coordinates of the lower left and upper right corners of cross sections of these
parts of segments
These coordinates are for the X and Z axes in models for vertical segments and the Y
and Z axes in horizontal segments, as shown in the following figure.
Z
Y
Axes
X
These coordinates show the positions of the parts of the segments relative to each other.
One X or Y coordinate value is always 0 and the other coordinate values specify the
relative distances of the other lower left or upper right corners to that 0 value.
The line +Length=length specifies that SigNoise takes the lengths of the parts of the
segments from the Allegro layout instead of from the model. Specifying a value instead of
length is valid syntax for an IDL model.
.rlgc Declaration
After the.crosssection section, the next part of the sample model is the .rlgc
declaration.
.rlgc RLGCT_1S_2R_2914 ( Length=length N=2 )
.C 0
+ 6.625200e-11 -4.567200e-12
+ -4.567500e-12 5.729800e-11
.L 0
+ 4.834800e-07 7.706100e-08
+ 7.705900e-08 4.388100e-07
.G 0
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+ 0.000000e+00 -0.000000e+00
+ -0.000000e+00 0.000000e+00
.R 0
+ 3.586500e+00 0.000000e+00
+ 0.000000e+00 1.793200e+00
.endrlgc RLGCT_1S_2R_2914
The .rlgc declaration begins with a name for the sub-circuit. This name is provided by the
field solver. The field solver replaces the STL or MTL prefix for the model sub-circuit name
with the RLGC prefix. In this model, the name of the .rlgc sub-circuit is
RLGCT_1S_2R_2914.
After the name of the .rlgc sub-circuit there is, in parentheses, a reiteration of the
Length=length statement from the .crosssection declaration and the size statement
N=2. The N=2 statement specifies that the .rlgc sub-circuit provides parasitic values for
two connect lines, segments, or parts and that the matrices that specify these values in the
.rlgc sub-circuit have a dimension of 2 by 2 values.
The remainder of the .rlgc sub-circuit contains .C, .L, .G, and .R declarations of
capacitance, inductance, conductance, and resistance value matrices.
All of these matrices have the same format for specifying self and mutual parasitic values. The
matrix lists self values diagonally from the top left to the bottom right of the matrix. The self
value on the top of the matrix is the value of the leftmost part of a connect line segment in a
cross sectional view of the design. The matrix lists mutual values to the left or right of the self
values.
For example, the following section of code is the capacitance value matrix:
.C 0
+ 6.625200e-11 -4.567200e-12
+ -4.567500e-12 5.729800e-11
In this matrix, the part of a segment that appears to the left in a cross section has a self
capacitance of 6.625200e-11. The capacitance between the left segment part and the right
segment part is -4.567200e-12. The right part has a self capacitance of 5.729800e-11 and
the capacitance between the right and left segment parts is once again -4.567500e-12.
In this capacitance value matrix, the value to the right of the .C keyword is the frequency
value. In this model, it specifies that SigNoise apply the matrix values for all frequencies
greater than zero.
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Characteristic Modal Delay, Admittance, and Impedance Matrices
The last part of the example line segment model is the Characteristic Modal Delay,
Admittance, and Impedance section declaration.
**The Characteristic Modal Delay, Admittance and
**Impedance Matrices of these Transmission Lines:
*Delay Matrix.
*Td 0 (n=2)
* 5.706200e-09 0.000000e+00
* 0.000000e+00 4.889800e-09
*Admittance Matrix.
*Y 0 (n=2)
* 1.185600e-02 -1.415100e-03
* -1.415100e-03 1.158100e-02
*Impedance Matrix.
*Z 0 (n=2)
* 8.559500e+01 1.045800e+01
* 1.045800e+01 8.762400e+0
+shield( 3.048e-05 1 0 )
+dielectric( 0.0003048 4.5 0.001 )
IDL Via Models
SigNoise generates IDL models for vias. You can edit these models if you want to change the
values specified in them by SigNoise algorithms.
Example Via Model
The following example shows an IDL model for a via. The sections following the example
describe the statements in a via model and where you might want to change the SigNoise
values in the model.
.subckt VIA_POAR_VIA_L1A0W600L7A135W600
+L1A0W600 L7A135W600 SL3 SL9
.material sml9 conductivity=5.959e+07 losstangent=0
.material sml8 dielectric=4.5 losstangent=0.001
.material sml6 dielectric=4.5 losstangent=0.001
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.material sml4 dielectric=4.5 losstangent=0.001
.material sml3 conductivity=5.959e+07 losstangent=0
.material sml2 dielectric=4.5 losstangent=0.001
.material sml10 dielectric=4.5 losstangent=0.001
.material ml9 conductivity=5.959e+07
.material ml8 dielectric=4.5
.material ml7 conductivity=5.959e+07
.material ml6 dielectric=4.5
.material ml5 conductivity=5.959e+07
.material ml4 dielectric=4.5
.material ml3 conductivity=5.959e+07
.material ml2 dielectric=4.5
.material ml11 conductivity=3.43e+07
.material ml10 dielectric=4.5
.material ml1 conductivity=3.43e+07
.layerstack LayerStackAll
+dielectric( sml10 0.00019304 )
+shield( SL9 sml9 3.048e-05 )
+dielectric( sml8 0.0001524 )
+dielectric( sml6 0.00079248 )
+dielectric( sml4 0.00018288 )
+shield( SL3 sml3 3.048e-05 )
+dielectric( sml2 0.0001397 )
.Via L1A0W600 L7A135W600 SL3 SL9
+ pad( 0.00152146 0.0015748 ellipse(ml1 0.0 0.0 0.0014224 0.0014224))
+ void( 0.00135128 0.00138176 ellipse(ml3 0.0 0.0 0.0014224 0.0014224) )
+ pad( 0.0011684 0.00119888 ellipse(ml5 0.0 0.0 0.0014224 0.0014224))
+ pad( 0.00037592 0.0004064 ellipse(ml7 0.0 0.0 0.0014224 0.0014224))
+ void( 0.00019304 0.00022352 ellipse(ml9 0.0 0.0 0.0014224 0.0014224) )
+ pad( 0 5.334e-05 ellipse(ml11 0.0 0.0 0.0014224 0.0014224))
+ drill(5.334e-05 0.00152146 ellipse(ml1 0.0 0.0 0.0003429 0.0003429))
+ trace( L1A0W600 0 rectangle(sml1 0.0 0.00152146 0.0001524 0.0015748))
+ trace( L7A135W600 135 rectangle(sml7 0.0 0.00037592 0.0001524 0.0004064))
*There is a PIN named U23.1 here.
*There is a VIA here.
* Closed-form formula solution
C0 L7A135W600 0 3.04105e-14
C1 L1A0W600 0 3.04105e-14
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R01 L7A135W600 L1A0W600 1e-7 L= 1.37277e-09
.ends VIA_POAR_VIA_L1A0W600L7A135W600
.subckt Declaration
The via model begins with a .subckt declaration:
.subckt VIA_POAR_VIA_L1A0W600L7A135W600
+L1A0W600 L7A135W600 SL3 SL9
The subcircuit name specifies the following information:
VIA_POAR_VIA_L1A0W600L7A135W600
Specifies a
via model
Width of this
interconnect line
in design units
Design name
Padstack name
Start layer
Angle that an
interconnect line
enters the bottom pad
of the via
Angle that an interconnect
line enters the top pad of the
via
Width of this interconnect
line in design units
End layer
The following information follows the subcircuit name:
+L1A0W600 L7A135W600 SL3 SL9
Repeats information
from the subcircuit
name
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three and layer nine
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.material Declaration
The via model contains a .material declaration for each layer in the via. These
declarations contains dielectric coefficients, conductivity, and loss tangent data from the
technology file.
The .material declaration in the model specifies the following information:
.material sml9
conductivity=5.959e+07 losstangent=0
A placeholder for material layer
number nine. The prefix “s” for this
placeholder indicates that this
.material declaration specifies
two values.
Values for conductivity and
loss tangent.
.layerstack Declaration
Via models use a special type of layer stack called LayerStackAll that includes all the layers
in the design. In the following .layerstack declaration, each line is for a layer of the
design.
.layerstack LayerStackAll
+dielectric( sml10 0.00019304 )
+shield( SL9 sml9 3.048e-05 )
+dielectric( sml8 0.0001524 )
+dielectric( sml6 0.00079248 )
+dielectric( sml4 0.00018288 )
+shield( SL3 sml3 3.048e-05 )
+dielectric( sml2 0.0001397 )
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The first shield layer line contains the following information:
+shield( SL9
sml9 3.048e-05 )
Specifies a shield layer
Thickness of the
layer
Material layer placeholder from
the .material declaration
Shield layer notation from the
.subckt declaration
.via Declaration
The .Via declaration specifies geometry information about via elements such as pads,
voids, drill holes, and the interconnect lines that connect to the via. In the following .Via
declaration, each line is for a pad or void in the via or for the drill hole or the interconnect lines
that connect to the via.
.Via L1A0W600 L7A135W600 SL3 SL9
+ pad( 0.00152146 0.0015748 ellipse(ml1 0.0 0.0 0.0014224 0.0014224))
+ void( 0.00135128 0.00138176 ellipse(ml3 0.0 0.0 0.0014224 0.0014224) )
+ pad( 0.0011684 0.00119888 ellipse(ml5 0.0 0.0 0.0014224 0.0014224))
+ pad( 0.00037592 0.0004064 ellipse(ml7 0.0 0.0 0.0014224 0.0014224))
+ void( 0.00019304 0.00022352 ellipse(ml9 0.0 0.0 0.0014224 0.0014224) )
+ pad( 0 5.334e-05 ellipse(ml11 0.0 0.0 0.0014224 0.0014224))
+ drill(5.334e-05 0.00152146 ellipse(ml1 0.0 0.0 0.0003429 0.0003429))
+ trace( L1A0W600 0 rectangle(sml1 0.0 0.00152146 0.0001524 0.0015748))
+ trace( L7A135W600 135 rectangle(sml7 0.0 0.00037592 0.0001524
0.0004064))
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The first pad line contains the following information:
+ pad( 0.00037592 0.0004064 ellipse(ml7 0.0 0.0
Specifies that
the geometry
information is for
a pad
0.0014224 0.0014224))
Specifies the
material layer
from the
Specifies that
the pad is an
ellipse
.material
declaration
The Z axis
coordinates for the
pad
Specifies the four
coordinates of a
bounding box
around the ellipse of
the pad
Closed-Form Solution
At the end of the via model is a Spice circuit description that represents the behavior of the
via. SigNoise first uses a closed-form method to generate values for this circuit description.
The following is an example of a closed-form solution:
* Closed-form formula solution
C0 L7A135W600 0 3.04105e-14
C1 L1A0W600 0 3.04105e-14
R01 L7A135W600 L1A0W600 1e-7 L= 1.37277e-09
In this example, two capacitors and an inductor are used to represent the behavior of the via.
You can change these values when you edit a via model.
The capacitance and inductance values in this solution automatically come from a closedform solution. You might want to use the more accurate values that come from the SigNoise
three-dimensional field solver.
To generate three-dimensional field solution values for a via model
1. Click left on the model in the list box in the Model Browser.
2. Click left on Solve.
Selecting Solve generates a model with field solution values.
Note: Three-dimensional field solution values take longer to generate than closed-form
values. You can control the choice between performance and accuracy.
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IDL Shape Models
SigNoise also generates IDL models for shapes. You might need to edit these models if you
want to change the values specified in them by the field solver.
You might also want to create your own field solver. If so, you need to understand the structure
of these models.
Example Shape Model
The following example shows an IDL model for a shape. The sections following the example
describe the statements in a shape model and where you might want to change the SigNoise
values in the model.
.subckt SHAPE_BLM_X980Y2660L1
+X1260Y2620L1 X1040Y2580L1
.material sml6 dielectric=5.2 losstangent=0.001
.material sml5 conductivity=5.959e+07 losstangent=0
.material sml4 dielectric=5.2 losstangent=0.001
.material sml3 conductivity=5.959e+07 losstangent=0
.material sml2 dielectric=5.2 losstangent=0.001
.material ml7 conductivity=5.959e+07
.material ml6 dielectric=5.2
.material ml5 conductivity=5.959e+07
.material ml4 dielectric=5.2
.material ml3 conductivity=5.959e+07
.material ml2 dielectric=5.2
.material ml1 conductivity=5.959e+07
C1 0 1 5.92089e-12
R1 1 X1260Y2620L1 1e-6 L=1e-13
R2 1 X1040Y2580L1 1e-6 L=1e-13
.ends SHAPE_BLM_X980Y2660L1
.sbckt Declaration
The shape model begins with a .subckt declaration:
.subckt SHAPE_BLM_X980Y2660L1
+X1260Y2620L1 X1040Y2580L1
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The subcircuit name specifies the following information:
SHAPE_BLM_X980Y2660L1
Specifies a
shape model
The design
name
The X and Y
coordinates of the
first corner of the
shape
The layer number
of the shape
The first corner of a shape is the location of the first point you selected when you drew the
shape.
The following information follows the subcircuit name:
+X1260Y2620L1 X1040Y2580L1
The X and Y coordinates
and the layer number where
another interconnect line
attaches to the shape
The X and Y coordinates
and the layer number
where an interconnect line
attaches to the shape
.material Declaration
The shape model contains a .material declaration for each layer in the design. These
declarations contain dielectric coefficients, conductivity, and loss tangent data from the
technology file.
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The .material declaration in the model specifies the following information:
.material sml6 dielectric=5.5 losstangent=0.001
A placeholder for material layer number
nine. The prefix “s” for this placeholder
indicates that this .material declaration
specifies two values.
Values for the dielectric
coefficient and loss
tangent.
Closed-Form Solution
At the end of the shape model is a Spice circuit description that represents the behavior of
the shape. SigNoise first uses a closed-form method to generate values for this circuit
description.
The following is an example of a closed-form solution:
C1 0 1 5.92089e-12
R1 1 X1260Y2620L1 1e-6 L=1e-13
R2 1 X1040Y2580L1 1e-6 L=1e-13
In this example a capacitor and two inductors are used to represent the behavior of the shape.
As with via models, you can change these values when you edit a shape model.
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DML Syntax
■
“Overview” on page 278
■
“About DML files” on page 278
■
“File Structure” on page 278
■
“DML Syntax” on page 279
■
“Comments” on page 279
■
“ModelTypeCategory Keywords” on page 279
■
“Tokens” on page 280
■
“Parameter of aToken” on page 280
■
“Sub-parameters of PackageModel” on page 281
■
“Example of PackageModel” on page 284
■
“Sub-parameters of Cable” on page 285
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DML Syntax
Overview
This appendix is a summary of the syntax and structure of Device Model Library (DML) files
and their use within package modeling. Most of the examples here are extracted from existing
library files.
About DML files
A DML file is a library that contains models and sub-circuits used in circuit simulation.
Cadence Sample Device Model Library
The Cadence sample device model library is:
/install_dir/share/pcb/signal/cds_iocells.ndx
Look at this file for additional details of the structure of a Device Model Library file, as well as
for examples of the different types of device models.
You can use the Model Browser to list the models in the library, and to edit, add, and delete
models. For details on using the Model Browser to work with the models in a library, see
Chapter 3, “Basic Library Management.”
File Structure
The top 3 levels of a DML file are organized according to the following structure:
("filename.dml" ; Name of this DML file.
(ModelTypeCategory
; A keyword. See “ModelTypeCategory Keywords” on page 279.
("modelname"
; A token, The name the user will know the model by.
<model subparams> ; The data is different for each model type.
)
; End of one model.
<more models>
)
; End of this model type category.
<more model types>
); End of the data in this library.
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DML Syntax
DML Syntax
A DML file contains lists and sub-lists of tokens enclosed within pairs of parentheses.
Comments are also included in the file for documentation purposes.
Comments
A comment consists of all characters on a code line that follow a semi-colon.
Examples:
; This is a comment line.
; End of the package model
ModelTypeCategory Keywords
The following table contains keywords that are used to specify the model type.
Table B-1 ModelTypeCategory Keywords
Keyword
Usage
PackageDevice
Defines part models.
PackageModel
Describes package parasitics which may apply to many
parts.
IbisIOCell
Describes I/O buffer model information, also known as a
buffer.
AnalogOutput
Define a buffer simply by a waveform.
DesignLink
Describes connectivity between modules.
Defines RLGC parasitics matrices and also used by System
Configurations to represent cables.
Cable
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DML Syntax
Tokens
A token is a string of characters enclosed in "double-quotes".
Example:
"Dip14Pin"
Note: If the token contains only alphabetic, numeric, and underscore characters; the doublequotes may be omitted. However, within double-quotes, a token may span multiple lines, with
the line endings retained as part of the token. Semi-colons within double-quotes are semicolons, not the beginning of a comment.
The first token after each left parenthesis is the name of a piece of data.
The first token of a DML file is always the name of the library file.
Example:
("filename.dml" ...
Parameter of aToken
The tokens following the first one, up to the balancing right parenthesis, represent the value
of the data. This collection is called a "parameter."
Example:
(example
(type example_type)
(name "this is a name with spaces and even a newline,
which must be quoted")
(timing
(setup "1.1")
(hold "0.6")
)
)
A parameter may have any number of sub-parameters, implementing a data hierarchy. A
parameter may instead have a value token. Never does a DML parameter have multiple value
tokens, or a value token and sub-parameters.
The order of sub-parameters does not matter. It can be in any order as long as it is present.
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DML Syntax
Sub-parameters of PackageModel
Sub-parameters of PackageModel include:
■
PinNameToNumber
■
R, G, L, C
■
frequency
■
format
■
data
PinNameToNumber
The PinNameToNumber parameter maps pin-names to corresponding wire-numbers, thus
associating each pin with an index in the RLGC matrix.
Note: PinNameToNumber parameter is not necessary if the pin-names are numeric. This
information essentially duplicates the WireNumber (if specified) in the PackagedDevice
models. If both are present in a given circumstance then the WireNumber from the
PackagedDevice overrides the information here. This allows special cases and pin-renaming.
R G L C Matrices
These represent the parasitics matrices at different frequencies.
Note: RLGC data in a PackageModel will be used only if CircuitModels do not exist.
Frequency Value
The frequency point (in Hertz) at which RGLC are extracted.
Format
■
BandedSymmetricMatrix
BandedSymmetricMatrix is used to describe the coupling relationship between pins. Two
values are associated with this format:
❑
band (band B_NUMBER)
B_NUMBER must always be odd. It indicates that each pin has mutuals with
B_NUMBER - 1 neighbors (one on either side).
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DML Syntax
Example:
(band 3) means that pin 5 has neighbor pins 4 and 6; pin 9 has neighbor pins 8
and 10, etc.
❑
dimension (dimension D_NUMBER)
dimension is defined as the number of pins. It is also the matrix dimension of
RLGC parasitics.
■
SymmetricMatrix
SymmetricMatrix format is the same as
BandedSymmetricMatrix with band = 2 * dimension - 1.
■
SparseSymmetricMatrix
SparseSymmetricMatrix format describes a R/G/L/C matrix in SPARSE matrix format.
❑
dimension (dimension D_NUMBER)
dimension is defined same as the one in BandedSymmetricMatrix format.
■
CircuitModels
The CircuitModels format describe a package model using Spice sub-circuit syntax. The
RLGC section does not exist when CircuitModels is defined.
Note: CircuitModels is used for large package model description. It can also embed
arbitrary Spice models for packages.
CircuitModels may contain the following two parameters:
❑
SingleLineCircuits
(SingleLineCircuits (pin_number (SubCircuitName name_of_subckt)
SingleLineCircuits describes a corresponding single line sub-circuit (without coupling to
adjacent lines) for each pin in the package.
pin_number maps the sub-circuit to corresponding pins.
name_of_subckt gives the name of a Spice sub-circuit in the format:
subckt name_of_subckt input output
where input and output are the sub-circuit port nodes; input is to the buffer side for
a package model; and output is to the package side.
Note: The port order cannot be altered.
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DML Syntax
Example:
(SingleLineCircuits
(1 (SubCircuitName longsingle_dc_wire))
(2 (SubCircuitName longsingle_dc_wire))
(4-14 (SubCircuitName longsinglewire)))
...
Example:
(CircuitModels
(SingleLineCircuits
(1-5 (SubCircuitName (typical longsinglewire))))...
SubCircuits"
.subckt longsinglewire 1 2
r13 1 3 0.002 l=3n
t32 3 0 2 0 z0=70 td=0.1n
.ends longsinglewire"
)))
Note: Sub-parameter SingleLineCircuits is REQUIRED in defining CircuitModels.
❑
CoupledLineCircuits
CoupledLineCircuits are needed only for Crosstalk and Comprehensive
simulations.
Data
(data "data_section")
data_section includes the matrix entries of R/L/G/C.
Each entry is separated with space.
■
Data for BandedSymmetricMatrix
The data_section of BandedSymmetricMatrix has total number of data as
SUM (dimension - i), where i = 0, 1, 2, ... K, K = (1 + (band -1 )/2).
Example:
(BandedSymmetricMatrix (band 27) (dimension 14)
...
It has K = (1 + (27 - 1)/2) = 14, therefore, the total number of data in the data section is
equal to 14 + 13 + 12 + ... + 1 = 105
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DML Syntax
Example:
(BandedSymmetricMatrix (band 1) (dimension 14)
...
It has K = 0, and the total number of data is 14.
■
Data for SymmetricMatrix
Same as for BandedSymmetricMatrix with band = 2 * dimension - 1.
■
data for SparseSymmetricMatrix
(data " r_num c_num value...")
r_num and c_num are the row and column numbers of a non-zero entry.
value is the entry's value.
Note: The order of the entries is unimportant, but it is an error to have row > column for
any entry. Give only the upper triangle and the diagonal of the matrix. The lower triangle
is assumed equal to the transpose of the upper triangle.
Example:
(C
(SparseSymmetricMatrix
(dimension 14)
(data " 1 1 643.0f
2 3 -55.6f
...
)
Example of PackageModel
(PackageModel
("Ex_14Pin"
(PinNameToNumber ; Maps pin names to numbers
("A1" 1)
("A2" 2)
("A3" 3)
("A4" 4)
("A5" 5)
("A6" 6)
("A7" 7)
("A8" 8)
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("A9" 9)
("A10" 10)
("A11" 11)
("A12" 12)
("A13" 13)
("A14" 14)
) ; End of PinNameToNumber
(RLGC
; Set of R, L, G, & C matrices per frequency.
(0
; The frequency (in Hertz)
(R
; Begin Resistance matrix
(BandedSymmetricMatrix
(band 27) (dimension 14) ; That makes this a full matrix.
(data "0.0006919231 0 0
...
") ; End of data section of R
) ; End of BandedSymmetricMatrix
) ; End of R description
(L ; Begin Inductance matrix
(BandedSymmetricMatrix
(band 27) (dimension 14)
(data "2.631284E-09 9.014512E-10 5.038304E-10
3.486299E-10 2.649051E-10 2.16809E-10
...
") ; End of data section of L
) ; End of BandedSymmetricMatrix
) ; End of L description
) ; End of RLGC at frequency = 0
...
) ; End of RLGC description
) ; End of Dip14Pin
) ; End of PackageModel
Sub-parameters of Cable
Sub-parameters of Cable include PinNameToNumber, RLGC matrix, and CircuitModels.
■
PinNameToNumber
Same as defined in PackageModel.
■
RLGC
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DML Syntax
RLGC indicates the start of the R/L/G/C matrix section.
There are R, L, G, C sub-parameters under this section. They are defined as those in
PackageModel.
Example:
(Cable
("FourWireCable"
(RLGC ; RLGC here is the sub-parameter of Cable to describe matrices.
(0
(R
...
)
(L
...
)
) ; End of frequency 0
)
); End of FourWireCable
) ; End of Cable
■
CircuitModels
Same as defined in PackageModel.
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C
The Cadence Default Model Library
■
“Overview” on page 288
■
“DIG_LIB Library Models” on page 288
■
“DEFAULT_LIB Library Models” on page 289
■
“Package Library Models” on page 289
■
“Library Location and Structure” on page 290
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The Cadence Default Model Library
Overview
The models in the Cadence Default Library can be included in three categories:
■
DIG_LIB Library Models
Standard digital logic families containing 217 unique parts in a format directly compatible
with SigNoise with their corresponding IBIS files. These models have been made from
spice files from Signetics (except for one device).
■
DEFAULT_LIB Library Models
Default set of models having IOCELLS for GTL, PCI and ASIC types. These IO cells can
be used to select the right buffer for a given application.
■
PACKAGE Library Models
Default set of models having IOCELLS for GTL, PCI and ASIC types. These IO cells can
be used to select the right buffer for a given application.
For a complete list of models, refer to the following file in your Cadence installation directory.
share/pcb/signal/cds_partlib.ndx
DIG_LIB Library Models
The digital device model library supports models for parts from four type of digital logic
families. A part’s digital logic family refers to the different processes and implementations
used in the manufacture of the parts used in integrated circuits. For example, bipolar
transistor-transistor-logic, CMOS, bipolar emitter coupled logic, or a combination of several
technologies can be used.
Each technology has different input and output parameters. The following table shows the
digital logic families and number of parts under each technology that are included in the
library
.
Table C-1 Digital Logic Families
Technology
Family
Description
Number
of Parts
FTTL
FAST Transistor-Transistor Logic for speed critical circuits.
106
ABT
Advanced BiCMOS Technology for bus interfaces with high
drive, lower power consumption and fast propagation.
36
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Table C-1 Digital Logic Families
Technology
Family
Description
Number
of Parts
ALVC
Advanced Low Voltage CMOS for low power consumption.
10
ALS
Advanced Low Power Schottky for low power consumption in
non-speed critical circuits.
65
DEFAULT_LIB Library Models
The following table shows the default model families and number of parts under each
technology that are included in the library
.
Table C-2 Default Model Families
Technology
Family
Description
Number of
IOCELLS
GTL
GTL IO cell derived from Texas gtl spice file.
01
PCI
PCI Compatible IO cells for both 3v and 5v derived from Intel 04
pci spice file.
ASIC
ASIC IO cells for different current capability both for 3 and 5v; 22
with and without slew made from suitable approximations for
the ASIC CMOS technology.
Package Library Models
The default package models include:
■
20dip
■
14soic
■
16soic
■
20soic
■
16ssop
■
20ssop
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The Cadence Default Model Library
■
28plcc
■
44plcc
Library Location and Structure
The Cadence Default Model Library is located in your Cadence installation directory. The
default path is:
/cds/share/pcb/signal/SignalPartLib
The directory contains two sub-directories corresponding to the three model categories.
■
DEFAULT_LIB
Contains signoise .dml files and their corresponding .ibs files. The corresponding
assumption.txt file lists the assumptions, approximations, and validation test_set_up
used.
■
DIG_LIB
Contains subdirectories corresponding to the digital logic family. Each digital logic family
subdirectory contains files for Device models and IOCell models (.dml files). There is
one device model in each file. The corresponding IBIS files(.ibs files) also exist. There
is one DIGlib_assump.txt file giving the test setups used to validate each family.
■
PKG_LIB
Note: In the signal directory, SigNoise uses the device model index file
cds_partlib.ndx to quickly load groups of models.
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D
SPECCTRAQuest Standard Signal
Integrity Libraries
■
“Overview” on page 292
■
“The Libraries” on page 292
■
“Installing and Licensing the Model Libraries” on page 292
■
“Using the Models” on page 294
■
“Cloning Models” on page 294
■
“Model Integrity” on page 294
■
“The Digital Logic SI Library” on page 295
■
“The Memory SI Library” on page 296
■
“The FPGA SI Library” on page 298
■
“The Microprocessor SI Library” on page 298
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SPECCTRAQuest Standard Signal Integrity Libraries
Overview
There are four SigNoise-compatible signal integrity model libraries which contain over 9000
unique parts. Each library part can be packaged in different ways.
These standard signal integrity libraries are available for purchase separate from SigNoise
and require a separate license. They are available for UNIX and Windows NT.
The Libraries
Signal integrity models come in the following libraries:
■
Digital Logic
■
Memory
■
FPGA
■
Microprocessor
Each library is described in the sections that follow. For a complete list of models in each
library, refer to the library’s index file located in:
share/pcb/signal/optlib/<library.ndx>
Installing and Licensing the Model Libraries
You must purchase the standard libraries before you can use them. Licensing and installation
are the same for the standard libraries as they are for all Cadence products. Each of the four
libraries requires a separate license. Once installed, you must set up the libraries.
Note: On Windows NT 4.0, you cannot install the libraries on an NTFS bootable partition.
See the installation notes provided with the software CD for more information.
Setting Up the Standard Libraries
You run signoise_setup to set up the libraries. The signoise_setup program, in turn,
performs a series of parameter checks and then calls dmlinstall to decrypt the libraries.
From UNIX, you run signoise_setup from the installation directory.
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From NT, you run signoise_setup by choosing Start – Programs – Performance
Engineering – signoise_setup.
The signoise_setup program examines the following:
■
Checks for installed libraries
■
Checks for license
■
Queries user for personal data
■
Checks for a destination directory for the decrypted library files that it can write to
■
Decrypts the model files
■
Creates an index to catalog the models in each library (mkdeviceindex)
■
Optionally removes the encrypted installation files, to regain disk space
When you run signoise_setup you must
1. Answer all queries,
2. Choose a product number:
1.
2.
3.
4.
0.
Digital Logic Library
Memory Library
FPGA Library
Microprocessor Library
EXIT
Enter Product No. to Install
The encrypted model files from the product installation are placed in the install directory :
/share/pcb/signal/optlib/install/<library>
Running signoise_setup results in placing decrypted models and library indices in the
appropriate user directory:
/share/pcb/signal/optlib/user/<library>
Depending on the configuration of your computer, it may take over two hours to install and
decrypt the libraries.
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Using the Models
When initializing a new run directory, SigNoise can be directed to load those libraries that you
want to use by setting the signal_optdevlibs environment variable.
setenv signal_optdevlibs ‘dll/index.ndx fpga/index.ndx’
To load optional libraries into an existing run directory, use the Add Existing Library button
in the Library Browser and select Optional Cadence Library from the Open File widget.
You can load the index.ndx file for an entire library, or for one of the manufacturer or family
specified indexes.
Cloning Models
The signal integrity models are protected by copyright. You are free to clone and modify a
standard signal integrity library model to suit your unique requirements. You must, however,
retain the Mentor Graphics copyright notice from the original in any model that you clone.
Model Integrity
The data used to create the models is based on measurements performed by Mentor
Graphics Corporation. To assure realistic representation, measurements are taken in a tightly
controlled environment at a standard temperature. The equipment provides high speed pulse
stimuli, high speed data acquisition, and high resolution DC stimulus measurement. The
measurements produce 40-picosecond, jitter free timing data.
The integrity of the measurements is maintained by routine calibration. The measurement
process is based on the knowledge of engineers experienced in the design of high frequency
measurement equipment for the test and measurement industry and engineers experienced
in the design of high density integrated circuits.
The measurement process begins with the test fixture. Signals for the parts under test are
shielded from external interference. The ground and power distribution system is filtered and
bypassed. High frequency coaxial cables carry the stimulus and response signals to and from
a part during characterization.
The measurement data is stored in a master file for the part. The measurements are then
recalled and modeled, and the modeled data is overlaid on measurement data. The overlay
of measurement and model data allows immediate validation of the stored model information
and the measurement data.
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The libraries cover most manufacturers. Since the source of the data in the library is based
on measurements with actual parts, the models account for differences between different part
numbers in the same digital logic family from the same semiconductor manufacturer.
For a given semiconductor manufacturer there can be significant differences between
different logic types within the same technology. Also, different semiconductor manufacturers
with the same logic type and technology can have differences due to their different
manufacturing processes. By using measurements made on a specific part, the standard
digital device model library provides you with the most realistic models to use in your
simulations.
The Digital Logic SI Library
Models in the digital logic SI library are placed in the following directory:
/share/pcb/signal/optlib/user/dll
The library index is created in:
/share/pcb/signal/optlib
For a complete list of models in the library, you can search the index file using the UNIX grep
command or the NT Find command. The models are for parts (components or devices) from
the following manufacturers.
■
Advanced Micro Devices
■
American Micro System, Inc.
■
Analog Devices
■
AT&T
■
Crystal
■
Cypress Semiconductor Corporation
■
Dallas
■
Ecliptek
■
GEC
■
Goldstar Technology, Inc.
■
Harris Semiconductor Corporation
■
Ideal Semiconductor Corporation
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■
Integrated Device Technology, Inc.
■
IMI
■
Kyocera
■
Lattice Semiconductor
■
Maxim
■
Microlinear
■
Motorola
■
National Semiconductor Corporation
■
Panasonic Semiconductor Corporation
■
Pericom
■
Philips Corporation
■
PLX
■
Quality Semiconductor Corporation
■
SGS Thomson
■
Texas Instruments, Inc.
■
Toshiba
■
Triquint
■
Utmc
■
Vitesse
The Memory SI Library
Models in the memory SI library are placed in:
/share/pcb/signal/optlib/user/memory
The library index is created in:
/share/pcb/signal/optlib
For a complete list of models in the library, you can search the index file using the UNIX grep
command or the NT Find command.
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The models are for parts (components or devices) from the following manufacturers.
■
Advanced Micro Devices
■
Amtel
■
Catalyst
■
Cypress Semiconductor
■
Dallas
■
Goldstar
■
Harris
■
Hitachi
■
Hyundai
■
Ideal
■
Idt
■
Intel
■
ISSI
■
LogicDevices
■
Micron
■
Motorola
■
National
■
Paradigm
■
Phillips
■
Samsung
■
SGS Thompson
■
Siemens
■
Sony
■
Texas Instruments
■
Toshiba
■
Xilinx
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The FPGA SI Library
Models in the FPGA SI library are placed in:
/share/pcb/signal/optlib/user/fpga
The library index is created in:
/share/pcb/signal/optlib
For a complete list of models in the library, you can search the index file using the UNIX grep
command or the NT Find command.
The models are for parts (components or devices) from the following manufacturers.
■
Actel
■
Altera
■
Quicklogic
■
Xilinx
The Microprocessor SI Library
Models in the microprocessor SI library are placed in:
/share/pcb/signal/optlib/user/microprocessor
The library index is created in:
/share/pcb/signal/optlib
For a complete list of models in the library, you can search the index file using the UNIX grep
command or the NT Find command.
The models are for parts (components or devices) from the following manufacturers.
■
AMD
■
IBM
■
Intel
■
Motorola
■
PMC_SIERRA
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Texas Instruments
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E
Model Translation
“Overview” on page 302
“IBIS to DML” on page 304
“Warning Messages from the Ibis2signoise Utility” on page 309
“Error Messages from the Ibis2signoise Utility” on page 313
“QUAD to DML” on page 316
“Warning Messages from the Quad2signoise Utility” on page 317
“Error Messages from the Quad2signoise Utility” on page 317
“Translating ESpice Files to Generic Spice Files” on page 318
“Spc2spc Translation Rules” on page 321
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Model Translation
Overview
The SigNoise simulator supplies utilities for the purpose of translating IBIS and Quad model
formats into the Device Model Library (DML) file format.
There are two methods that can be used to translate models:
■
Model translation through the user interface.
■
Model translation at the command line.
Translation
To translate an IBIS or Quad model file to DML format through the user interface:
1. Open the Signal Analysis Library Browser (Analyze – SI/EMI – Library) from the toolbar
of either SPECCTRAQuest or Allegro/APD.
2. Click the Translate button.
A pop-up menu appears, listing the translator formats. The formats include:
❑
IBIS—Runs the ibis2signoise translation utility. Use ibis2signoise if you have an
industry standard .ibs file.
❑
QUAD—Runs the quad2signoise translation utility. Use quad2signoise if you
have a .mod file (and any required .tlb file) for use with a ViewLogic TLC or XTK
based simulator.
3. Click the translator you want to use.
A file browser appears. For IBIS models, files of type .ibs are listed. For Quad models,
files of type .mod are listed.
4. Use the browser to locate the file you want to translate, then click OK.
The new .dml file is created and added to the directory. Resulting messages or
warnings are shown in a text window.
To translate an IBIS model file to DML format using the command line:
1. Enter the ibis2signoise command in the following syntax:
ibis2signoise [-options] in=infile [out=outfile]
where infile is the name of the file to translate and outfile is the device model
library output file to create from the input data. The default is to create infile.dml when
outfile is not speciifed.
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Model Translation
Available options for this command are listed in the following table.
.
Table E-1 Ibis2signoise Command Options
Option
Function
-u
Creates unique model names. This is the default.
-nu
Leaves model names unchanged.
-curvedir dir
Creates a directory in which a SigWave waveform file is created for
each VI curve and VT curve.
-ebdcomp
For Electronic Board Description (EBD) files, creates an IbisDevice
with a PackageModel instead of a BoardModel.
-serswcomp
Creates an ESpiceDevice component for each Series_switch model, in
addition to the IbisDevice that contains one or more Series_switch
models.
-i
Does not pass the input file through ibischk3. The default is to pass the
input file through ibischk3 before translation.
-d
Does not pass the output file through dmlcheck. The default is to pass
the output file through dmlcheck after translation and save the results.
-version
Displays the version of the software and exits.
The ibis2signoise utility reads the input file. If the ibischk3 program is in your path and you
do not specify the -i option, ibis2signoise runs ibischk3 to verify that the input file is a valid
IBISmodel. The ibis2signoise utility reports any errors detected by ibischk3 and continues.
The ibis2signoise utility then creates the output DML file, and passes this file to the
dmlcheck utility unless you specify the -d option. If no warnings or errors are found, then the
output file is replaced with the cleaned up file produced by dmlcheck.
If errors are found during any of these three phases, the output file is renamed with the
additional .txt extension. In this case the output file should not be used, but it can be
examined to diagnose problems.
To translate a Quad model file to DML format using the command line:
1. Enter the quad2signoise command in the following syntax:
quad2signoise [-options] in=infile [out=outfile]
where infile is the name of the file to translate and outfile is the device model
library output file to create from the input data. The default is to create infile.dml when
outfile is not speciifed.
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Available options for this command are listed in the following table.
.
Table E-2 Quad2signoise Command Options
Option
Function
-curvedir dir
Creates a directory in which a SigWave waveform file is created for
each VI curve and VT curve.
-d
Does not pass the output file through dmlcheck. The default is to pass
the output file through dmlcheck after translation and save the results.
-version
Displays the version of the software and exits.
If there is a .tlb file associated with your .mod file, make sure that there is an include
statement for the .tbl file in the .mod file. For example, part.mod must have an include
part.tlb statement at the beginning.
The quad2signoise utility then creates the output DML file, and passes this file to the
dmlcheck utility unless you specify the -d option. If no warnings or errors are found, then
the output file is replaced with the cleaned up file produced by dmlcheck.
If errors are found during either of these two phases, the output file is renamed with the
additional .txt extension. It should not be used in this case, but it can be examined to
diagnose problems.
IBIS to DML
Translating EBD files
By default, when ibis2signoise translates an IBIS Electronic Board Description (EBD) file, it
produces a BoardModel for each EBD file encountered. You can use the resulting
BoardModel in SPECCTRAQuest as one of the designs in a system configuration.
During translation ibis2signoise loads and translates all .ibs files listed as required in the
Reference Designator Map] section of the EBD file. The BoardModel, as well as all IbisDevice
and IbisIOCell models from all input files, are translated into the single output .dml file.
When you include the -ebdcomp option during translation, ibis2signoise models the EBD
file as a component by producing an IbisDevice with an associated PackageModel rather than
a BoardModel.
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■
The IbisDevice models the single component internal to the EBD that has driver pins. If
the EBD includes either multiple components with drivers or no components with drivers,
ibis2signoise will not translate the EBD with the -ebdcomp option.
■
The PackageModel includes SingleLineCircuits. It is created and assigned to the
IbisDevice to model the internal interconnect within the EBD.
You can use the IbisDevice as a pluggable component in both SPECCTRAQuest and
SPECCTRAQuest signal explorer. In this case a system configuration is not required.
Translating Series_switch Models
By default, when ibis2signoise translates an IBIS file containing Series_switch models, it
produces an IbisDevice component with an associated PackageModel. You can use the
resulting IbisDevice as a pluggable component in SPECCTRAQuest. SPECCTRAQuest
recognizes the series connection and accordingly simulates the connected nets as an xnet.
However, Series_switch pins added into SPECCTRAQuest signal explorer will ignore the
series connection.
To study the operation of Series_switch models in SPECCTRAQuest signal explorer, run
ibis2signoise with the -serswcomp option. A two-pin ESpiceDevice component model is
created for each Series_switch model found in the IBIS file. Each model contains a Spice
subckt for one switch. The resulting Series_switch model can be added into
SPECCTRAQuest signal explorer so you can study the behavior of the switch, but the model
is probably not useful as a model to be assigned to a design component.
The Series_switch Spice subckts reside in the PackageModel associated with IbisDevice
components, and in the ESpiceDevice component, if the -serswcomp option is used.
The switch is initially in the ON state. You can modify the subckt to simulate the OFF state
behavior, or to simulate dynamic ON and OFF switching by text editing the PackageModel.
The following code example, taken from a Series_switch IBIS model, shows the voltage
source that let's you turn the switch on and off:
...
.subckt subcktName_SERIES 1 2
R1 1 2 1e+06
* Voltage source for controlling Series_switch elements
* Set sersw_gate to 0V for Off mode or 5 for On mode
* Or, attach sersw_gate to a pin for external control
Vsersw_gate sersw_gate 0 5
* [On]
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* [Series MOSFET] Vds = 1.000000
* This current source is controlled by Vgs and Vds
GDS_ON0 1 2 PWL 1 2 sersw_gate 2
DATAPOINTS VV
-3.000000 0
-2.000000 0
-1.000000 -1
0 0
1.000000 1
2.000000 0
3.000000 0
END VV
DATAPOINTS VI
0 0
0.1 -0.00061171
0.15 -0.000602017
0.2 -0.000592324
0.25 -0.000594392
...
It is possible, for example, to have the switch turn on or off every 100ns:
Vsersw_gate sersw_gate 0 PULSE(0 5 0 5n 5n 45n 100n)
If you run the simulation with a fixed duration of 500ns, you will see the effects of switch-on
and switch-off on the incoming pulse data.
Viewing VI and VT Curve Waveforms
Use the -curvedir option.to have ibis2signoise create waveforms for each VI curve and
VT curve found in the translated IBIS file. The waveforms are produced by dmlcheck, so they
will not be produced if you use the -d option with ibis2signoise. If the curve directory does
not exist, it is created.
One waveform file is created for each VI curve and VT curve in the translated IBIS file.
Waveform filenames have the form IOCellName_CurveName.sim.
Each waveform file contains 6 waveforms—the original minimum, typical, and maximum
curves and the repaired minimum, typical, and maximum curves. Use SigWave to view the
waveform files.
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In cases where ibis2signoise has modified a curve to fix some problem, the change should
be apparent when you view the curve waveforms. The fixed waveforms are identical to the
original waveforms for unmodified curves.
IBIS to DML Translation Rules
■
The ibis2signoise utility translates IOCell and device data from the following formats to
DML.
❑
1.1
❑
2.1
❑
3.0
❑
3.1
❑
3.2
■
Translation is case independent. The ibis2signoise utility preserves upper and
lowercase for names and strings. You do not have to check the case of keywords,
numeric suffixes, and other syntax elements because they do not require upper or
lowercase for translation.
■
Keywords that consist of two words (such as Voltage Range) must have a single space
character between the words. The ibis2signoise translator does not recognize two-word
keywords if the words are separated by anything other than a single space.
■
You can include scaling suffixes for numerical quantities. The valid scaling suffixes and
the values they specify are shown in the following table
.
Table E-3 Ibis2signoise Scaling Suffixes
Suffix
Scaling Value
F
1e-15
P
1e-12
N
1e-9
U
1e-6
M
1e-3
K
1e+3
X
1e+6
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Table E-3 Ibis2signoise Scaling Suffixes
Suffix
Scaling Value
MEG
1e+6
G
1e+9
T
1e+12
The following table shows suffixes that are valid but have no effect either in translation or
simulation
.
Table E-4 Other Valid Ibis2signoise Scaling Suffixes
A
S
AMP
V
DEG
OHM
H
■
The suffix F is a special case. When preceded by another scaling prefix, such as pF for
pico Farads, the translator sees the F as a unit of measurement and not a scaling suffix.
When not preceded by another suffix, such as FA for femto Amp, the translator sees the
F as a scaling suffix.
All other suffixes are invalid and result in a syntax error.
Warning and Error Messages from the Ibis2signoise Utility
The ibis2signoise translation utility displays warning and error messages that are generated
during the translation. These messages are displayed in:
■
an outfile.temp file if the utility was invoked from the Library Browser dialog box.
-or■
the window which contains the command line from where you invoked the utility.
The significance of the line numbers appearing in the messages depends on which phase of
the translation they appear in. Line numbers in the ibischk3 phase and in the IBIS-to-DML
conversion phase refer to lines in the input IBIS file. Line numbers in the dmlcheck phase refer
to lines in the output DML file. If dmlcheck finds no errors, the input DML file is replaced with
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a new output DML file which may have lines inserted and deleted relative to the original input
file.
To investigate warning messages by line number, you might need to run ibis2signoise with
the -d option to obtain a DML file containing the line numbers to which dmlcheck is referring.
For details on warning and error messages, their probable cause and suggested solution, see
“Warning Messages from the Ibis2signoise Utility” on page 309and “Error Messages from the
Ibis2signoise Utility” on page 313.
Warning Messages from the Ibis2signoise Utility
WARNING @line line_number—BOTH Vinl and Vinh must be specified, or
neither
Probable Cause: The IBIS file omits a Vinl or Vinh statement or there is a syntax error
in one of these statements.
Suggested Solution: Look for the Vinl and Vinh statements beneath the line specified
in the warning message.
WARNING@ line line_number—Duplicate section_name section
Probable Cause: In the IBIS file an IOCell model contains more than one of the
specified sections. Possible duplicated sections include all the V/I curves, ramps, and
voltage ranges.
Suggested Solution: Look for a duplicate of the specified section above the specified
line number in the IBIS file and rename or remove one of these sections.
WARNING@ line line_number—Duplicate component name: component_name
Probable Cause: A component name was used previously in the IBIS file.
Suggested Solution: Look in the IBIS file at the specified line number. The component
name at that line number was used previously in the file. Determine which of the two
components you want translated to an DML device model and delete or rename the other
one.
WARNING @line line_number—Duplicate pin name
Probable Cause: A pin section contains entries for two pins with the same name.
Suggested Solution: At the specified line number, in a pin section, find the pin name
and then look above this line number for a pin with the same name. Rename or delete
one of these two pins.
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WARNING @line line_number—Duplicate model name
Probable Cause: The IBIS file contains models for two IOCell models with the same
name.
Suggested Solution: The specified line contains a model name for an I/O cell. Look
above this line for an IOCell model with the same name. Rename or delete one of these
models.
WARNING @line line_number—Duplicate model parameter parameter_name
Probable Cause: A model in the IBIS file contains more than one entry of a model
parameter. Model parameters include Model_type, Polarity, Enable, C_comp,
Vinl, and Vinh.
Suggested Solution: The specified line contains a model parameter for a model. Look
above this line for another entry of this model parameter and delete one of the entries of
this parameter.
WARNING @line line_number—Duplicate [Model Spec] sub-parameter <PARAM>
Probable Cause: One of the following parameters has appeared twice within one [Model
Spec] section: Vinh, Vinl, Vinh+, Vinl+, Vinh-, Vinl-, S_overshoot_high,
S_overshoot_low, D_overshoot_high, D_overshoot_low,
D_overshoot_time, Pulse_high, Pulse_low, Pulse_time, Vmeas.
Suggested Solution: The specified line contains a sub-parameter for a model. Look
above this line for another entry of this sub-parameter and delete one of the entries of
this sub-parameter.
WARNING @line line_number—Lexical error:
Probable Cause: The IBIS file contains a syntax error at the specified line. Possible
lexical errors include misspelled keywords.
Suggested Solution: Edit the specified line in the IBIS file.
WARNING @line line_number—Model selector entry <MODEL> repeated
Probable Cause: A model in the IBIS file contains a duplicated model selector name.
Suggested Solution: The specified line contains a duplicated model selector name.
Look above this line for another model selector name and delete one of them.
WARNING @line line_number—PackageModel <MODEL> removed from component
<MODEL>
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Probable Cause: One of the internal components of an EBD has a PackageModel
assigned to it, and the -ebdcomp option has been given. Since this option produces an
IbisDevice component for the EBD module as a whole, only the top level IbisDevice may
have a PackageModel. Internal components are regarded as "bare die" in this case.
Suggested Solution: Verify that the referenced PackageModel is not required for EBD
files translated to IbisDevice with the associated PackageModel.
WARNING @line line_number—Repeated C_pkg
Probable Cause: A model in the IBIS file contains two C_pkg specifications.
Suggested Solution: The specified line contains a C_pkg specification. Look above
this line for another C_pkg specification and delete one of them.
WARNING @line line_number—Repeated L_pkg
Probable Cause: A model in the IBIS file contains two L_pkg specifications.
Suggested Solution: The specified line contains an L_pkg specification. Look above
this line for another L_pkg specification and delete one of them.
WARNING @line line_number—Repeated R_pkg
Probable Cause: A model in the IBIS file contains two R_pkg specifications.
Suggested Solution: The specified line contains an R_pkg specification. Look above
this line for another R_pkg specification and delete one of them.
WARNING @line line_number—Repeated ramp key-word: keyword
Probable Causes:
❑
If the specified ramp keyword is Fall, the Ramp section at the specified line number
contains more than one dV/dt_f specification.
❑
If the specified ramp keyword is Rise, the Ramp section at the specified line number
contains more than one dV/dt_r specification.
Suggested Solution: The specified line contains a dV/dt_r or dV/dt_f specification.
Look above this line for another dV/dt_r or dV/dt_f specification and then delete one of
them.
WARNING @line line_number—Too many dV/dt pairs (should be only 3)
Probable Cause: A dV/dt_f or dV/dt_r specification contains more than three pairs. A
dV/dt_f or dV/dt_r specification should contain three pairs of values. Each pair specifies
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the change of voltage over the change in time. The three pairs specify minimum, typical,
and maximum ramp values.
Suggested Solution: Edit the specified line number so that the dV/dt_f or dV/dt_r
specification contains only three pairs of values.
WARNING @line line_number—Unrecognized Enable type character_string.
Defaulting to Active-High.
Probable Cause: An IOCell model has an invalid enable type. IOCell models can have
only two types of enables: Active-High and Active-Low. The ibis2signoise translator
substitutes Active-High for the invalid enable type.
Suggested Solution: If you do not want SigNoise to use the Active-High enable type,
edit the specified line so that it contains the Active-Low enable type.
WARNING @ line line_number—Unrecognized model type: character_string,
Defaulting to Load.
Probable Cause: A model type in Model_type specification is invalid. The valid model
types are Output, I/O, 3-state, and Load. The ibis2signoise translator substitutes Load
for the invalid model type.
Suggested Solution: If you do not want SigNoise to use the Load model type, edit the
specified line so that it contains another valid model type.
WARNING @line line_number—Unrecognized Polarity character_string.
Defaulting to Non-Inverting.
Probable Cause: An IOCell model has an invalid polarity specification. IOCell models
can have only two types of polarities: Inverting and Non-Inverting. The ibis2signoise
translator substitutes Non-Inverting for the invalid polarity specification.
Suggested Solution: If you do not want SigNoise to use the Non-Inverting polarity, edit
the specified line so that it contains the Inverting polarity specification.
WARNING @line line_number—Pentium_processor(735|90,815|100) will be
written as Pentium_processor_73590_815_100.
Probable Cause: The ibis2signoise translator replaces all illegal model name
characters with underscores in the final SigNoise model output.
WARNING @line line_number—[C Series] will be used in both [On] and [Off] states
WARNING @line line_number—[L Series] will be used in both [On] and [Off] states
WARNING @line line_number—[Lc Series] will be used in both [On] and [Off] states
WARNING @line line_number—[R Series] will be used in both [On] and [Off] states
WARNING @line line_number—[Rc Series] will be used in both [On] and [Off] states
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WARNING @line line_number—[Series Current] will be used only in the [Off] state
WARNING @line line_number—[Series MOSFET] will be used only in the [On] state.
Probable Cause: Separate sets of these [Model Spec] keywords can be specified for
the [On] state and [Off] state of an IBIS Series_switch. To support dynamic modeling of
the switch, SPECCTRAQuest allows only a single topology. A single circuit is
constructed containing all series elements. [Series MOSFET] elements are enabled only
in the [On] state, and [Series Current] elements are enabled only in the [Off] state.
Suggested Solution: Verify that the switch behavior will be as intended given these
conditions. Possibly reorganize the Series_switch elements in the IBIS file accordingly.
For example, if a 10 ohm resistor is used in the [On] state and a 1MOhm resistor is used
in the [Off] state, replace the [On] state resistor with an equivalent [Series MOSFET].
Error Messages from the Ibis2signoise Utility
ERROR @ line line_number—Syntax error The lexical token was
<character-string>.
Probable Cause: The IBIS file contains a syntax error at the specified line. Possible
lexical errors include misspelled keywords.
Suggested Solution: Edit the specified line in the IBIS file.
ERROR @line line_number—Rise_on_dly may not be negative
ERROR @line line_number—Fall_on_dly may not be negative
ERROR @line line_number—Rise_off_dly may not be negative
ERROR @line line_number—Fall_off_dly may not be negative
ERROR @line line_number—Rise_off_dly must be greater than
Rise_on_dly, if set
ERROR @line line_number—Fall_off_dly must be greater than
Fall_on_dly, if set
Probable Cause: Incorrect time values in a [Driver Schedule] section.
Suggested Solution: Edit the time values in the IBIS file.
ERROR @line line_number—IbisDevice 'MODEL' has no PackageModel
SeriesPinMapping skipped.
Probable Cause: An IBIS [Component] that has [Series Pin Mapping] references a
[Package Model], but no definition of the [Package Model] is found.
Suggested Solution: Either remove the [Package Model] reference, or include
the[Package Model] definition in the same IBIS file as the IBIS [Component].
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ERROR @line line_number—No SubCircuits in 'MODEL' CircuitModels SeriesPinMapping skipped.
ERROR @line line_number—PackageModel 'MODEL' has no CircuitModels SeriesPinMapping skipped.
Probable Cause: The [Package Model] referenced by an IBIS [Component] may be a
matrix style model. To implement [Series Pin Mapping] a CircuitModels PackageModel
with a valid SubCircuits section is required.
Suggested Solution: Correct the PackageModel so that it has a valid CircuitModels
section with SubCircuits. Optionally, the PackageModel reference may be removed from
the IBIS [Component] that has [Series Pin Mapping]. In this case a PackageModel
contain the [Series Pin Mapping] elements will be created automatically.
ERROR @line line_number—No data for package model.
Probable Cause: The dimension of an IBIS [Define Package Model] is absent.
Suggested Solution: Edit the IBIS file and add the correct dimension data.
ERROR @line line_number—No definition found for SeriesPin model.
'MODEL'
Probable Cause: A [Series Pin] section references a Series model, but the named
model is not found in the IBIS file.
Suggested Solution: Add the IBIS Series [Model] to the file containing the
n[Component] with [Series Pin] section.
ERROR @line line_number—PackageModel 'MODEL' for IbisDevice 'MODEL'
is not found
Probable Cause: The IBIS [Component] references a [Package Model] for which no
corresponding [Define Package Model] is found.
Suggested Solution: Add the [Define Package Model] to the same IBIS file that
contains the referencing [Component].
ERROR—Syntax error, position unknown.
Probable Cause: The ibis2signoise translator has encountered an unanticipated
problem.
Suggested Solution: Contact Cadence Customer Support.
ERROR @line line_number—Unable to create EBD <MODEL> component model
because component <MODEL> is not found.
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Probable Cause: An internal [Component] referenced in an EBD is not found.
It is required if the -ebdcomp option is given, so that the EBD can be implemented as a
PackageModel associated with the primary internal IbisDevice component.
Suggested Solution: Place the IBIS file for the [Component] in the same directory as
the EBD file. Make sure the component IBIS file has the filename as stated in the EBD
file.
ERROR @line line_number—Unable to create PackageModel for IbisDevice
'MODEL'
Probable Cause: Unexpected error.
Suggested Solution: Contact Cadence support.
ERROR @line line_number—Unable to identify component name for EBD
<MODEL_PKG> component model.
Probable Cause: The EBD does not contain exactly one internal component with driving
pins. The -ebdcomp option requires that the EBD contain one activecomponent that has
drivers. All other internal components must be passive, with no pins that can drive an
output.
Suggested Solution: Change the [Model] assignments of pins on internal components
that are not intended to be active drivers. If the EBD correctly contains multiple driving
components, then the -ebdcomp option can not be used.
ERROR @line line_number—Unrecognized [Model Spec] sub-parameter
<PARAM>
Probable Cause: A sub-parameter appearing after a [Model Spec] is not one of: Vinh,
Vinl, Vinh+, Vinl+, Vinh-, Vinl-, S_overshoot_high, S_overshoot_low,
D_overshoot_high, D_overshoot_low, D_overshoot_time, Pulse_high,
Pulse_low, Pulse_time, or Vmeas.
Suggested Solution: Check your spelling and edit the IBIS file at that line.
ERROR @line line_number—Use of [LC Series] with no [C Series]
ERROR @line line_number—Use of [RC Series] with no [C Series]
ERROR @line line_number—Use of [Rl Series] with no [L Series]
Probable Cause: A [C Series] or [L Series] section is missing from the IBIS file.
Suggested Solution: Add the required primary series element.
ERROR @line line_number—[Number of Pins] missing from package model.
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Probable Cause: A package model is not followed by a [Number Of Pins] line.
Suggested Solution: Add the required line, or move it so that it follows the beginning of
the package model.
ERROR @line line_number—[C Series] not allowed in pre-IBIS 3.0 file
ERROR @line line_number—[Driver Schedule] not allowed in pre-IBIS 3.0
file
ERROR @line line_number—[L Series] not allowed in pre-IBIS 3.0 file
ERROR @line line_number—[LC Series] not allowed in pre-IBIS 3.0 file
ERROR @line line_number—[Model Spec] not allowed in pre-IBIS 3.0 file
ERROR @line line_number—[Number of Sections] not allowed in pre-IBIS
3.0 file
ERROR @line line_number—[Off] not allowed in pre-IBIS 3.0 file
ERROR @line line_number—[On] not allowed in pre-IBIS 3.0 file
ERROR @line line_number—[R Series] not allowed in pre-IBIS 3.0 file
ERROR @line line_number—[RC Series] not allowed in pre-IBIS 3.0 file
ERROR @line line_number—[RL Series] not allowed in pre-IBIS 3.0 file
ERROR @line line_number—[Series Current] not allowed in pre-IBIS 3.0
file
ERROR @line line_number—[Series MOSFET] not allowed in pre-IBIS 3.0
file
Probable Cause: The [IBIS Version] of the file is incorrect.
Suggested Solution: Change [IBIS Version] to 3.2
QUAD to DML
Viewing VI and VT Curve Waveforms
Use the -curvedir option to have quad2signoise create waveforms for each VI curve and
VT curve found in the translated IBIS file. The waveforms are produced by dmlcheck, so they
will not be produced if you use the -d option with quad2signoise. If the curve directory does
not exist, it is created.
One waveform file is created for each VI curve and VT curve in the translated IBIS file.
Waveform filenames have the form IOCellName_CurveName.sim.
Each waveform file contains 6 waveforms -- the original minimum, typical, and maximum
curves and the repaired minimum, typical, and maximum curves.
Use SigWave to view the waveform files.
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In cases where quad2signoise has modified a curve to fix some problem, the change should
be apparent when you view the curve waveforms. The fixed waveforms are identical to the
original waveforms for unmodified curves.
Warning and Error Messages from quad2signoise
The quad2signoise translation utility displays warning and error messages that are
generated during the translation.
If warnings or errors are found, they are displayed in the shell window that you used to start
the application. The line numbers refer to lines in outfile.temp. An output file is not
created.
If there are only warning messages, the output file is generated. The reported problems exist,
but did not prevent the output file from being created. If there are error messages, the output
file cannot be generated until the reported problems are fixed. For details on warning and
error messages, their probable cause and suggested solution, see “Warning Messages from
the Quad2signoise Utility” on page 317and “Error Messages from the Quad2signoise Utility”
on page 317.
Warning Messages from the Quad2signoise Utility
WARNING: Unable to open the log file log_filename for writing.
quad2signoise.log will be taken as the default log file.
Probable Cause: A permission or some other system problem prevents the
quad2signoise translator from writing the log file that you specified. The translator writes
a log file named quad2signoise.log in the current directory.
Suggested Solution: Check permissions for the path you specified for the log file.
WARNING: Unable to open the log file quad2signoise.log for writing.
Log will be displayed on the standard output.
Probable Cause: A permission or some other system problem prevents the
quad2signoise translator from writing the quad2signoise.log file in the current
directory. Warning and error messages appear only in the window the utility is running in.
Suggested Solution: Check permissions for the current directory.
Error Messages from the Quad2signoise Utility
ERROR: Unable to open file output_dml_filename for writing.
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Probable Cause: A permission or some other system problem prevents the
quad2signoise translator from writing the DML device model library.
Suggested Solution: Check permissions for the path to the current directory or the
path you specified for the output file.
ERROR: Unable to allocate memory.
Probable Cause: The translator does not have enough memory.
Suggested Solution: Check your system.
ERROR: Unable to open file input_QUAD_filename for reading.
Probable Cause: A permission or some other system problem prevents the
quad2signoise translator from reading the QUAD file.
Suggested Solution: Check permissions for the path to the directory that contains the
QUAD file.
Translating ESpice Files to Generic Spice Files
You can use the spc2spc utility to translate a Cadence proprietary Spice (or ESpice) input
file to a generic Spice input file compatible with Spice2G, Spice3, or HSpice. Using spc2spc,
you can translate ESpice input file to a generic Spice format you can use for benchmarking.
To translate a ESpice file to generic Spice:
➤
Enter the spc2spc command at the operating system command line in the following
syntax:
Spc2spc [options] <input file>
The usual input file will be main.spc.
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Model Translation
Available options for this command are listed in the following tables
Table E-5 Spc2spc Output Options
Option
Function
-mapOut=<filename>
Create a connectivity map file with the specified name.
-spectreOut=<filename> Translate to Spectre language format.
-spiceOut=<filename>
Translate to Spice language format.
Table E-6 Spc2spc General Options
Option
Function
Copy comments from source file to output file.
-dir=<directory> Create sub-directory <directory> into which all output files will
be written. This is particularly useful when the welement option is
enabled, since a large number of output files may be created.
Add comments to the output file indicating the name of the source
-fileInfo
file and the line number for each translated statement.
-flatten
Flatten the circuit so no sub-circuits remain.
Send help text to stdout.
-h
Do not translate ESpice transmission line n elements. The default
-nelement
action is to translate ESpice n elements into resistor, capacitor,
inductor (RLC) ladder networks.
Rename nodes, elements or sub-circuits.The placeholder text,
-rename=
node, elem and subckt mustbe replaced by one of the following
<node,elem,
format codes:
subckt>
-commentInfo
alphanumTruncate name to 8 characters and add a numeric
uniquifier.
asisDo not change the name.
cleanChange non-alphanumeric characters to ’_’
numericChange identifier to a number.
-sourceInfo
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Table E-6 Spc2spc General Options
Option
Function
-version
Send software version text to stdout.
-welement
Translate finite length ESpice transmission line n elements
elements into w elements. This option creates a RLGC definition
file for each distinct n element type.
Modify processing of w element option so that only transmssion
lines greater than the specified length are translated to w elements.
Shorter transmission lines will be converted into RLC ladder
networks.The length may be specified with units (e.g. 12mils). If no
units are supplied, the length is assumed to be in meters.
-wminlen=
<length>
Table E-7 Spc2spc Options for Tuning RLC Ladder Generation
Option
Function
-s
Convert single-line transmission line n elements into Spice
t elements.
-t=
<Rise/Fall Time
in ps>
Set the minimum rise or fall time in picoseconds. RLC ladder
networks are only accurate in modelling transmission lines up to
a limited frequency. The frequency limit can be increased by
increasing the number of ladder elements, but this will slow
simulation speed. When this option is supplied, ladder network
generation will be optimized to work with edge rates up to that
specified.
Set the maximum RLC segment delay in picoseconds.This
option can be used instead of the -t option to ensure there are
sufficient ladder sections to accurately simulate up to the
frequency of interest.
-x=
<segment delay
in ps>
The spc2spc translator reads the specified input file, usually main.spc. It will also read files
#included into this file. In the case of a standard main.spc, it #includes the complete ESpice
circuit heirarchy for a test case. This includes the components file (comps.spc), the
interconnect file (intercon.spc), the stimulus file (stimulus.spc), and, when
transmission files are present, the RLGC model files (dlink_RLGC.inc,
comps_RLGC.inc, and ntl_RLGC.inc).
After translation, the complete ESpice file hierarchy is combined into one Spice input deck,
main_gen.spc.
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Spc2spc Translation Rules
■
spc2spc does not translate behavioral models. Upon encountering a behavioral model,
spc2spc comments out the call to the behavioral model and describes, within
comments, the node connections for the behavioral model.
■
If behavioral models are present in your comps.spc file, you must make the
appropriate model/stimulus connections to the behavioral model’s IO nodes. In most
cases you can accomplish this by connecting the stimulus sub-circuit node to the
behavioral model’s former IO node directly.
■
spc2spc models transmission lines as distributed lumped element models with the -s
option, or in the case of single-line transmission lines, as T-models. By default all
transmission lines are modeled as distributed RLC element lines. Coupled transmission
lines are modeled with mutual capacitances and inductor coupling coefficients (kfactors).
■
spc2spc determines the granularity of the distributed, lumped sections based on the
modal propagation velocities in the transmission lines and the minimum transmission tile
from the stimulus file. the propagation delay for a section is constrained to be 1/20th of
the minimum transmission time in the system. This limits the lumped element
approximation error to 4%. You can use a command line option (-x=tau) to override the
default per-section delay to any non-zero value. You can use another command line
option (-t=tr) to override the minimum rise and fall time used in the lumped section
delay calculations.
■
spc2spc breaks inductive resistors (resistive inductors) into two series elements. It
keeps skin-effect resistors as parallel elements to the series R-L elements when they are
present.
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Computations and Measurements
■
“Overview” on page 324
■
“Pre-Analysis Requirements” on page 324
■
“Reflection Simulations” on page 326
■
“Segment-Based Crosstalk Estimation” on page 326
■
“Crosstalk Simulations” on page 327
■
“Timing-Driven Crosstalk Analysis” on page 328
■
“Simultaneous Switching Noise (SSN) Simulations” on page 328
■
“Comprehensive Simulations” on page 329
■
“Delay Computations” on page 329
■
“Distortion Computations” on page 333
■
“Simultaneous Switching Noise Measurements” on page 335
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Overview
This appendix presents an overview of the analytical approach used in signal integrity
simulation. The intent is to provide a condensed explanation of how analysis results are
derived.
Using SigNoise, you can quickly examine, or scan, one or more signals by performing
reflection simulations and crosstalk estimations on entire designs or on large groups of
signals. You can also probe individual signals, or small groups of signals, where you want to
delve into specific signal behaviors in detail, to generate and view waveforms and text reports.
When generating text reports, you can sort the results by specific criteria (for example,
undershoot, noise margin, or crosstalk) in order to rapidly identify signals that violate
electrical constraints.
Pre-Analysis Requirements
Before running SigNoise, the design needs to be properly prepared with regards to
properties, constraints, stack-up definition, and device models. For details, see Chapter 2,
“Transmission Line Simulation Setup.” Assuming the board is set up correctly, it should pass
the Design Audit procedure in a satisfactory manner. Following is a brief summary of some
of the more important items.
Device Models
The libraries containing the required device models must be available in the Library Browser.
There are several different types of models that can be present:
■
IBIS device models - Assigned to IC’c and connectors.
■
ESpice models - Assigned to discrete passive components such as resistors and
capacitors.
Stack Up Definition
The stack up definition is very important. This provides the geometries SigNoise needs to
derive interconnect parasitics. The conductor/dielectric thicknesses and dielectric constants
give the Z-axis information, and the X- and Y-axis information are obtained from the routed
conductors in the design. This allows SigNoise to have a “2.5 D” database for characterizing
interconnect during signal analysis.
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Modeling Unrouted Interconnect
You do not have to route the design to run SigNoise. You can define how to model unrouted
interconnect in the Parameters form, including percent Manhattan distance, characteristic
impedance, and propagation velocity. This allows simulations to be run prior to routing, right
from the rats nest. Items such as reflections, termination, and delays can be evaluated at this
stage. For routed connections, the actual routed traces are used instead of the criteria
described above.
Field Solutions
When you select a net for simulation, a detailed geometry extraction is performed, including
the primary net, its neighbor nets (per the user-defined geometry search window), and the
mutual coupling between them. This generates a coupled network of multiple conductors.
The interconnect geometry comprising the network is broken up into its unique individual
cross sections. For example, if the primary net had 6 mil spacing to a neighbor net at one
point, and 12 mil spacing to a neighbor net at another point, these would be broken up into 2
different unique cross sections. Then SigNoise looks in the specified interconnect libraries for
the required trace models, based on geometry. If it finds the ones it needs, it plugs them into
the circuit. The various trace models are spliced together to build the complete simulation
circuit.
If a required trace geometry hasn’t been characterized, it is sent to the field solver. The field
solver uses 2-dimensional boundary-element techniques to break up the cross section into a
fine mesh. Charge distribution over the mesh is then solved to derive a capacitance matrix for
the conductors in the cross section. The capacitance matrix is then used to derive the
inductance matrix. Resistance and conductance matrices are also generated to take into
account conductor loss such as skin effect, and as dielectric losses.
The output of the field solver is frequency-dependent RLGC matrixes (resistance, inductance,
conductance, and capacitance) per unit length, which get stored along with the geometry as
a trace model in the interconnect library. Therefore, these results can be re-used across
multiple designs, so the number of field solutions required to characterize a particular layout
are minimized. When a trace model is called from the interconnect library, its matrices are
then multiplied by the length associated with that particular cross section to generate a unique
interconnect model for that specific instance.
When a section of an interconnect network is represented in a simulation circuit, the length
of the section is used together with the RLGC matrix in the trace model to derive the
impedance and propagation delay of the section, along with mutual couplings to other
sections.
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Vias are automatically modeled through closed-form algorithms, based on their padstack
geometry in the layout database. Vias can optionally be modeled in greater detail utilizing the
3D field solver in SigNoise.
Signal Integrity Simulations and Computations
After the interconnect parasitics are derived, the appropriate device models are retrieved and
plugged in. A complete simulation circuit is built based on the type of analysis that was
requested. The different analysis types are distinguished by what is included in the circuit,
and how stimulus is applied, as discussed below.
The tlsim Simulator and Simulations
SigNoise uses a proprietary simulator, tlsim. The tlsim simulator is essentially a clean subset
of public domain Spice with proprietary enhancements and extensions developed by
Cadence to optimize it for PCB and MCM applications. For example, tlsim uses proprietary
macromodels for transmission lines and IOCells.
Reflection Simulations
For a reflection simulation, SigNoise traces out the extended net (xnet), characterizes the
trace geometries, obtains the relevant device models, builds a single-line circuit (disregards
neighbor nets), and runs a transmission line simulation. The stimulus is applied to the driver
pin on the xnet. In the case of multiple drivers on a net, multiple simulations are run, with one
active driver stimulated in each simulation. Other drivers on the xnet are inactive during the
simulation.
The output of these transient simulations are waveforms and delay & distortion report data.
Waveforms are produced for all driver and receiver pins on the xnet. The waveform is a plot
of voltage vs. time, so the values for noise margin, overshoot, first switch delay, and final settle
delay are taken directly from the waveform data. The receiver waveforms are checked for
monotonicity during the low-to-high and high-to-low transition period. Non-monotonic edges
are flagged as violations.
Segment-Based Crosstalk Estimation
Segment-based crosstalk estimation is intended to support an interactive crosstalk
debugging/etch editing use model where rapid results and quick identification of worst
offenders are required. Rather than performing costly coupled-line time domain simulation in
real time, this technique performs the time domain simulation up front to sweep
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representative crosstalk circuits for the design. This generates tables of crosstalk data.
Closed-form algorithms are then employed that intelligently leverage these pre-existing tables
of crosstalk data in conjunction with the unique routed geometries of specific nets. This
rapidly predicts the magnitude of coupled crosstalk on a segment-by-segment basis in real
time. The results are available in report format and are also enforced by on-line DRC’s (design
rule checks) in the SPECCTRAQuest Floorplanner and Allegro environments as well as by
the SPECCTRA autorouter.
To obtain segment-based crosstalk results, the crosstalk tables need to be available. These
tables are automatically generated based on the IOCell’s, stackup, and spacing rules in the
design. Based on this information, crosstalk circuits are built and swept through all relevant
combinations using full-time domain simulation. Crosstalk magnitudes and saturation lengths
are recorded and crosstalk lookup tables generated for use during estimation. When a
crosstalk estimate is requested for a given signal, an Xnet walk is performed where each
coupled segment on the Xnet is identified along with the aggressor. Based on the geometry
for each of these unique coupled segments, and the fastest IOCell on the aggressor, the
magnitude of the crosstalk imposed on the victim for that specific coupled segment is rapidly
predicted. In addition to the individual coupled segment contributions, overall aggressor Xnet
contributions and total victim crosstalk data are algorithmically derived and presented in
report format.
Important
Segement-based crosstalk estimation does not take into account detailed
topological effects like reflections, wave cancellation or the plethora of unique
stimulus combinations that can occur in actual designs. To analyse these sorts of
effects, full-time crosstalk simulation should be utilized.
Crosstalk Simulations
In Crosstalk simulations, a multi-line circuit is built that includes the victim net, neighboring
aggressor nets and mutual coupling. The victim net is held at either the high or low state and
the aggressor nets are stimulated. Crosstalk is simulated in the time domain, producing
waveforms and report data.
The user can choose to stimulate the aggressor nets in groups, or one aggressor net at a time
to isolate the contributions from individual nets, identifying worst offenders. Crosstalk timing
properties can also be used to set up neighbor stimuli, as discussed in the following section,
“Timing-Driven Crosstalk Analysis.”
Note: Crosstalk simulation is intended to suport a post-route verification use model.
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Timing-Driven Crosstalk Analysis
Both segment-based crosstalk estimation and time domain crosstalk simulation in SigNoise
are capable of being timing-driven, which greatly increases real-world accuracy and helps
eliminate pessimistic crosstalk false alarms. The estimation algorithms use crosstalk timing
properties to determine when nets are active and sensitive, and only considers the aggressor
nets that have an active time overlap with the victim nets sensitive time as crosstalk
contributors. The XTALK_IGNORE_NETS property can be used to tell a net or a group of nets
to disregard other nets or group of nets as a source of crosstalk. An example would be when
you want to disregard crosstalk between bits on a synchronous bus.
The following crosstalk timing properties can be applied to nets in SPECCTRAQuest or
Allegro:
XTALK_ACTIVE_TIME
XTALK_SENSITIVE_TIME
XTALK_IGNORE_NETS
XTALK_SENSITIVE_TIME properties can also be assigned to specific receiver pins for an
even greater level of accuracy.
For Crosstalk simulations, the crosstalk properties above are used to determine how to
stimulate multi-line circuits for crosstalk analysis. For example, assume a victim net being
analyzed for crosstalk had 2 aggressor nets, and they had the following properties:
victim net - XTALK_SENSITIVE_TIME = 5-10
neighbor #1 - XTALK_ACTIVE_TIME = 7 - 15
neighbor #2 - XTALK_ACTIVE_TIME = 20-25
Neighbor #2 would not be stimulated in the circuit, since its active time does not overlap with
the victim net's sensitive time. In this case, stimulating both aggressor nets together would be
overly pessimistic, and not indicative of real-world behavior.
Simultaneous Switching Noise (SSN) Simulations
To understand how a circuit is built for SSN simulations, assume a simple net is selected that
has only one driver and one receiver. When the driver pin is found, SigNoise examines the
device model for that pin's component and determines which power and ground buses the
driving IOCell references. It identifies all other driver pins in the package that share the same
power and ground buses. Assume that SigNoise finds four other drivers like this in the
package, connected to nets A, B, C, and D respectively.
A circuit is then built to include the following:
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■
The device model containing the five driver pins, the power and ground pins on the buses
involved, and their package parasitics
■
Any power and ground pin escape traces and vias
■
The original net selected and nets A, B, C, and D
Voltage sources are applied in the circuit corresponding to the nodes at which the pin escape
vias contact the power or ground plane. A simulation will then be run in which the outputs at
the driving package are switched simultaneously. This produces waveforms at the internal
power and ground buses, (at the die itself) for the driving package.
Plane modeling can optionally be included for SSN simulations to account for power and
ground planes and decoupling capacitors. In this case, the power and ground planes in the
stackup are characterized in an LC mesh. Decoupling capacitors are extracted from the
design and attached to the appropriate locations in the mesh. Voltage sources in the circuit
are inserted into the circuit based on explicit VOLTAGE_SOURCE_PIN properties attached
to connector pins in the design. This detailed analysis not only increases accuracy, but
enables the user to view 3D animation of the electromagnetic wave propagation through the
design and explore what if scenarios with stackup and decoupling.
Comprehensive Simulations
In a Comprehensive simulation, a multi-line circuit is built similar to that used for crosstalk
analysis. Power and ground parasitics are taken into account similar to basic SSN analysis.
The victim net and the aggressor nets are all switched simultaneously. The user can control
whether odd or even mode switching between the victim and aggressors is used.
Delay Computations
During delay analysis, SigNoise performs the calculations and checks described in this
section. These include timing rule checks and pass/fail waveform checks.
Compensated Interconnect Delays
When measuring waveforms at a receiver against time zero in a SigNoise simulation, you
include the driving IOCell delay as well as the delay contributed by the interconnect. For the
purpose of timing analysis, the IOCell delay is already accounted for in the overall component
delay. In order that the IOCell delay is not counted twice when reporting first switch and final
settle delays, the assumed IOCell delay must be backed out of SigNoise simulation results.
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Since the actual topology to which each pin is attached is not available for up-front timing
analysis, a test load (or test fixture) is assumed to be attached to the IOCell in order to derive
the component delay. This test load appears as follows:
Vterm
Rref
Out
Cref
To derive the contributed IOCell delay, SigNoise hooks up the IOCell to its corresponding test
load circuit and runs simulations to capture the slow, typical, and fast IOCell delay values,
measured at a predefined measurement voltage threshold (Vmeasure) for rising and falling
edges.
These values are stored with the model in the device library. When a SigNoise simulation is
run on the design, the appropriate IOCell (or buffer) delay is backed out to properly
compensate first switch and final settle delays to represent interconnect contribution only.
SigNoise determines the delays described in the following table.
Delays Determined by SigNoise
Delay
Description
Propagation Delay
Transmission line delay, the time required for wave propagation from
driver to receiver.
First Switch Delay
This is determined by subtracting the associated buffer delay from a
simulation measurement. For example, on a rising (falling) edge,
the simulation measurement is from time zero to when the receiver
first crosses its Vil (Vih) switching threshold. The associated rising
(falling) buffer delay of the driving IOCell is subtracted from this
measurement value to produce the reported first switch delay.
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Delays Determined by SigNoise
Delay
Description
Final Settle Delay
This is determined by subtracting the associated buffer delay from a
simulation measurement. For example, on a rising (falling) edge,
the simulation measurement is from time zero to when the receiver
crosses its Vih (Vil) switching threshold the final time and settles
into the high (low) logic state. The associated rising (falling) buffer
delay of the driving IOCell is subtracted from this measurement
value to produce the reported final settle delay.
The following diagram illustrates buffer delay, propagation delay, first switch delay, and final
settle delay for a rising signal.
Receiver
Driver
Vih
Input
Switching
Thresholds
Vmeasure
Vil
Propagation Delay
First Switch
Final Settle
Rising Buffer Delay
Note: First switch and final settle delays can be optionally measured to the associated
IOCells Vmeasure threshholds, as opposed to the receiver’s logic thresholds.
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Timing Rule Checks
SigNoise checks the measured delay values against the following constraints:
Constraint
Item
DELAY_RULE
minimum propagation delay
maximum propagation delay
MIN_FIRST_SWITCH
minimum first switch delay
MAX_FINAL_SETTLE
maximum final settle delay
Note: You can set these constraints on a net or on a pin-to-pin connection.
Pass/Fail Checks
During delay analysis, the following applies:
■
First Incident Rule
Verifies that the receiver pin transition occurs approximately in sync with the propagation
delay plus the actual rise/fall time observed at the driver. Typically, if the transition does
not occur on this first transmission of the edge, it occurs much later with reflections
matching some odd multiple of the propagation delay (for example, 3x, 5x, and so on, the
length delay). The failure is flagged if the time is greater than 1.5 times the expected time
of propagation plus the rise or fall time.
■
Monotonic Rule
Checks for a smooth transition through the mid-range. This check is especially important
for nets which drive edge-triggered devices which could otherwise double clock due to
a nonmonotonic edge. Ringing that occurs exclusively outside of the mid-range, that is,
above the high logic threshold or below the low, is not a violation of this monotonic rule.
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The following illustration shows non-monotonic and non-first Incident rules violations.
Driver
Receiver
Input
Switching
Thresholds
Non-monotonic edge
reversal in midrange
Propagation
Delay
3x, 5x, ... Propagation Delay
for NOT First incident
Distortion Computations
SigNoise analysis is controlled by user-defined criteria that establish the thresholds for delay
and distortion analysis. SigNoise includes both timing-oriented rules and the following checks
for voltage-related signal noise. You can limit each source of signal noise to a maximum
voltage level to detect high levels of a particular source of noise. Distortion criteria measured
by SigNoise include:
■
Overshoot
■
Noise Margin
■
Crosstalk
■
Simultaneous switching noise (SSN)
■
Differential mode electromagnetic interferance (EMI) in near and far field.
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Reflection Measurements
Reflections become prevalent when the signal rise or fall time is relatively small compared to
the propagation delay of the signal through the interconnecting etch or when
tr < 2td
wheret r is the rise/fall time andt d the one-way propagation delay through the etch. When
this is the case, the driver does not see the load. Consequently the proportion between
electric and magnetic energy (between voltage and current) is primarily determined by the
impedance of the transmission line connected to the driver. As the signal encounters a load
or another transmission line with different impedance, the proportion between voltage and
current is readjusted. This readjustment is the type of signal distortion called reflection.
“Reflection Measurements” on page 334 illustrates waveform reflection measurements.
Figure F-1 Reflection Measurements
High State Overshoot
High State Noise Margin
Vih
Vil
Low State
Noise Margin
Low State Overshoot
Reflection analysis in SigNoise produces overshoot and noise margin values. For reflection
analysis of a circuit, a transient simulation is performed, and the voltage waveform at each
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receiver pin is analyzed producing overshoot and noise margin data as shown in the previous
figure. Overshoot values (OV) are reported in reference to ground.
Crosstalk Measurements
When crosstalk simulations are run, multi-line circuits are built. The field solver extracts self
and mutual parasitics for routed interconnect, allowing coupled networks to be simulated in
the time domain. Waveforms for receiver pins on the victim net are analyzed to produce
crosstalk report data. Measurements are taken as follows based on the logic state of the
victim. Crosstalk for the victim held in the low (high) state is taken as the magnitude of the
delta between the highest (lowest) excursion of the receiver waveform minus the victims
steady state voltage. This is shown in the figure below.
Figure F-2 Crosstalk Measurements
Steady State High
High State
Crosstalk
Low State
Crosstalk
Steady State Low
Simultaneous Switching Noise Measurements
To measure the simultaneous switching noise associated with the net, SigNoise will:
■
Use the waveforms generated at the die for the driver device’s ground node and measure
the low state SSN value in the same manner as described for low state crosstalk in
“Crosstalk Measurements” on page 335.
■
Use the waveforms generated at the die for the driver device's power node and measure
the high state SSN value in the same manner as described for high state crosstalk in
“Crosstalk Measurements” on page 335.
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Cadence Espice Language Reference
■
“Overview” on page 338
■
“About the Input Format” on page 339
■
“Espice Syntax Fundamentals” on page 344
■
“DC Path to Ground” on page 348
■
“Supported Circuit Elements” on page 352
■
“Basic Elements” on page 353
❑
“Passive Elements: Resistor, Capacitor, Inductor, Mutual Inductor” on page 353
❑
“Single Lossless Transmission Line” on page 353
❑
“DC Voltage Source” on page 354
❑
“Diodes” on page 357
■
“Controlled Source Elements” on page 358
■
“IBIS Behavioral Model Elements” on page 375
■
“Multi-Conductor Transmission Line Models” on page 388
■
“Control Statements” on page 391
■
❑
“END Statement” on page 391
❑
“ENDS Statement” on page 391
❑
“NODE_PARAM Statement” on page 391
❑
“NODE_PARM_DIFFERENTIAL Statement” on page 393
❑
“PRINT Statement” on page 393
“Creating Espice Models for use with SPECCTRAquest” on page 396
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Overview
This appendix describes the native language of the simulator tlsim and it’s input file format,
Espice. The tlsim simulator is a time domain circuit simulator and employs algorithms similar
and in many cases identical to generic Spice.
Tlsim native language models may be embedded in the DML simulation model used by
SPECCTRAQuest and SigXplorer. You can elect to do this where the standard DML syntax
is not flexible enough to describe the behavior of a special device.
The language syntax of Espice (formerly known as Kspice) is very much like the generic
Spice syntax. The key difference between Espice and generic Spice is that Espice does not
yet support transistor level models. On the other hand Espice supports model types for
devices described by IBIS behavioral data. Espice also supports novel types of controlled
sources and latches. This allows for easy, accurate and efficient modeling of timing, signal
integrity, and electro-magnetic incompatibility (EMI) circuits entirely in the analog domain.
The first sections of this appendix introduce Espice and tlsim, and describe the syntax for
basic elements (resistors, capacitors, sources) and for more specific advanced elements
particular to Espice (IBIS behavioral models). The last section describes how to embed
Espice in a DML model.
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About the Input Format
The syntax of Espice is a relaxed form of that used by the popular Berkeley Spice simulator.
Statements
An Espice netlist is composed of a set of statements. Each statement starts on a separate
logical line. A logical line is composed of a physical line with directly following continuation
lines. Continuation lines have a ‘+’ character in the first position on the line.
An example of a statement on a single physical line is:
R1 2 3 4.7k
The same example using a continuation line:
R1 2 3
+ 4.7k
Note: A “+” character in the first position (column zero) on a line is always interpreted as a
continuation character. In any other position, “+” is interpreted as the plus operator.
Statements consist of text elements separated by space characters. (Tab characters may also
be used for the same purpose, since tab characters are internally converted to space
characters.) The case of the text is not significant. For example, the following are treated as
equivalent:
“GND”, “Gnd” and “gnd”
Standard Spice requires statements to start at the first physical position on the physical line.
Espice allows the text of statements to be indented with one or more spaces to improve
readability.
Blank lines may also be inserted for readability, but may not be used before continuation lines.
The following is legal:
R1 2 3
+
4.7k
R2
4
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+
6.8k
This is not (blank line preceding a continuation line)
R1 2 3
+
4.7k
R2
+
4
5
6.8k
Node Names
Statements may contain node names. In standard Spice, node names must be numeric.
Espice allows alphanumeric node names.
Following is an example of alphanumeric node names.
R1 first_node second_node 4.7k
The node names “0” and “gnd” are special and are interchangeably used as the absolute
reference node.
Note: Node names are scanned as character strings. Leading zeros and trailing alphas on
numeric node numbers are not ignored.
All of the following are distinct node names:
“0”, “00”, “000”, “0a”
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Numeric Representation
Numbers in Espice can be represented in integer, floating point, scientific or engineering
format as shown in the following table.
Table G-1 Espice Numeric Examples
Format Type
Examples
Integer
“1”,“99”
Floating Point
“3.14”, “0.998”
Scientific
“1.23e-12”,” 5e12”
Engineering
“1.23m”, “1.0G”
The engineering scale factors that are recognized are shown in the following table.
Table G-2 Engineering Scale Factors
Scale Factor
Value
T
= 1e12
G
= 1e9
Meg
= 1e6
K
= 1e3
M
= 1e-3
U
= 1e-6
N
= 1e-9
P
= 1e-12
F
= 1e-15
Important
The case in engineering scale factors is not significant. This means that the
standard S.I. notation conventions are not strictly obeyed. In particular “M” is
interpreted as “milli” (i.e. 1e-3, not Meg = 1e6).
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Datapoint Sections
Datapoint sections are tables of values. They are used for controlled sources, IBIS models
and lossy transmission lines.
Datapoint sections start with a “DATAPOINT” statement and end with an “END” statement.
The usual Espice syntax rules do no apply within the context of a datapoint section, in
particular, continuation “+” characters are not allowed.
See “Datapoints Statements” on page 366 for more detail on datapoint sections.
Statement Types
The first significant letter of a statement (ignoring preceding spaces) is generally used to
determine the statement type. The following describes the recognized statement types.
Table G-3 Espice Statement Types
Statement Type
Description
B
Behavioral I/O buffer model.
C
Capacitor instance.
D
Diode instance (unless start of Datapoints).
Datapoints
Start of datapoint section.
E
Voltage controlled voltage source (expression, piecewise linear,
rational function or non-linear inductor model).
F
K
Current controlled voltage source (expression, piecewise linear,
rational function or non-linear capacitor model).
Voltage controlled current source instance (expression, piecewise
linear, rational function or non-linear capacitor model).
Current controlled current source instance (expression, piecewise
linear, rational function or non-linear inductor model).
Mutual Inductor instance.
L
Inductor instance.
N
Single or multi-conductor lossy transmission line instance.
R
Resistor instance (simple or skin effect).
T
Single (lossless) transmission line instance.
G
H
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Table G-3 Espice Statement Types
Statement Type
Description
V
Voltage source instance (simple, pulse, sinusoidal, exponential
or piecewise linear).
X
Sub-circuit instance.
.
Control Statement (see below).
*
Comment (unless followed by ‘|’).
*|
Proprietary simulator directive (do not use).
Note: Espice does not support the standard Spice transistor elements. The DML language
uses a semicolon “;” as a comment character.
Control Statements
The various Espice control statements are described in the following table.
Table G-4 Espice Control Statements
Control Statement
Description
.END
End of main circuit definition or datapoint section.
.ENDS
End of sub-circuit definition.
.INCLUDE
Include definitions from specified file to complete
circuit.
Specify common model parameters that can be applied
.MODEL
to one or more (diode) elements. See “Diodes” on
page 357 for an example.
Creates a parameter. See “PARAM Statement” on
.PARAM
page 391 for an example.
Assign measurements, logic thresholds, reference
.NODE_PARAM
node, node printing and node name for reports. See
“NODE_PARAM Statement” on page 391 for an
example.
.NODE_PARAM_DIFFERENTIAL Set node parameters for differential pairs. See
“NODE_PARM_DIFFERENTIAL Statement” on
page 393 for an example.
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Table G-4 Espice Control Statements
Control Statement
Description
.PRINT
Print voltage or current at node (Alternate, preferred
mechanism is to set .node_param print option).
Marks named node as being the reference node for
timing measurements. (Alternate, preferred
mechanisms to set .node_param refnode option).
Start of subcircuit definition.
.REF_NODE
.SUBCKT
Espice Syntax Fundamentals
An Espice circuit contains two types of objects that represent the electrical circuit. They are:
■
nodes
■
elements
Elements represent the electrical components. The nodes provide information regarding the
way the electrical components are connected. This is best illustrated using the following
example.
Figure G-1 Simple Circuit
R1
node_1
V1
node_2
C1
* Simple circuit
* 5 Volt DC voltage source with negative terminal grounded
V1 node_1 5 gnd
* 10uF capacitor with one terminal grounded
C1 gnd node_2 10u
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* 50 Ohm resistor between the non-grounded terminals on
* the capacitor and voltage source
R 1 node_1 node_2 50
* Mark the end of the main circuit
.end
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The full syntax for the simple resistor, capacitor and voltage source will be given in later
chapters. However, it can be seen from this example that one syntax for these two terminal
devices is:
<element identifier (type given by first character)>
<first node name>
<second node name >
<element value>
and where two or more elements have node names that match, the nodes are assumed to be
connected.
Representing complicated electrical circuits as a flat netlist as given in the previous example
can be tedious. For this reason Espice provides a way to partition circuit functionality into
modules known as subcircuits which can then be assembled into the final circuit. Again, this
can be best illustrated by an example.
* The same simple circuit
* 5 Volt DC voltage source with negative terminal grounded
V1 node_1 5 gnd
* An instance of a subcircuit containing the RC elements
Xsub1 gnd node_1 my_rc_subcircuit
* Mark the end of the main circuit
.end
* Define the subcircuit
.subckt my_rc_subcircuit node_a node_b
* 10uF capacitor with one terminal grounded
C1 node_a node_c 10u
* 50 Ohm resistor between the internal terminals on
* the capacitor and the second external port
R 1 node_c nodeb 50
* Mark the end of the subcircuit
.ends
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In this case, the subcircuit instance syntax is:
<element identifier (starting with an X)>
<list of nodes connecting subcircuit with main circuit>
<name of subcircuit that this element is an instance of>
In this case, the subcircuit definition syntax is:
.subckt
<name of subcircuit>
< list of nodes connecting subcircuit with main circuit>
The complete syntax for subcircuit instances and definitions will be presented later. However,
it can be seen that nodes in the subcircuit instance are connected to those in the subcircuit
definition by order, rather than by name.
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DC Path to Ground
Parameters and Expressions
Espice allows constants to be given names. This is often used to keep actual component
values as a circuit in a single place while keeping circuit descriptions general. Parameters can
be created in a number of ways including the.param statement written in the following
format.
.param name=value
Example
* Simple circuit
.param Rval=50
.param Cval=IOu
V1 grd node_1 5
R1 node_1 node_2 Rval
C1 grd node_2 Cval
.end
Note: The preferred syntax for the.param statement is .param key=value. The “=” is
presently optional. However, for consistency, should be used in all new models.
Expressions can also be used in Espice. They must be enclosed in single forward
quotation marks.
Example
*Simple resistor
.param Rbase=50
.param Rscale=1.25
R1 node_1 node_2 ‘Rbase*Rscale’
Parameters can also be created within subcircuit calls and definitions. This is covered in the
next section.
Note: The circuit cannot contain a loop of voltage sources and/or inductors. Each node must
have a DC path to ground.
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Subcircuits
Subcircuits are one of the most important constructs in Espice. Subcircuits enable you to
easily reuse portions of circuit. Espice extends the standard Spice subcircuit syntax to include
parameterized subcircuits. There are no limits on the size and complexity of subcircuits.
Subcircuits can be global (that is, beyond the circuit’s.end statement) or they can be locally
nested (hierarchical subcircuits).
Complex circuits can be partitioned and also can contain various levels of hierarchy. Espice
solves this problem by providing a powerful and compact construct called subcircuits. The
following figure illustrates the top level view of a Spice circuit.
Figure G-2 Spice Circuit Diagram
Top Level Main Circuit
Subcircuit partitions
Subcircuit hierarchy
(nested subcircuits)
*main ckt
....
x .....
.end
.subckt a ..
........
.subckt b ..
..
.ends b
.ends a
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Subcircuit Syntax
General Form
.param
Xyyyyyyy n1 n2 .... nk Subckt_Name param1=val1 param2=val2 ..
.........
.........
.END /* main or subckt definition ends here */
.SUBCKT Subckt_Name n1 n2 ... nk param1=default_val1 param2=default_val2
subckt description
.ENDS Subckt_Name
The keyword X identifies the element as a subckt with arbitrary number of external terminals
n1, n2 ..nk. The structure of the subckt is completely arbitrary and it is treated the same way
as the main circuit.
The parameters are very similar to function arguments in programming languages like C. The
best way to use them is to define them in the calling X statement. If it is not defined then the
parameters will be inherited by the following rule
Rules for determining parameter value:
1. If the parameter is defined in the calling X statement (or in a .param statement) then use
that value.
A simple example:
.subckt top 1 2
x1 node1 nested param1=60
.subckt nested 1
r1 1 0 param1
.ends nested
.ends top
A more complex example:
.subckt top 1 2
.param param1=50
x1 node1 nested param1=60
.subckt nested 1 param1=70
r1 1 0 param1
.ends nested
.ends top
The resistor r1 in both of these examples will be 60 ohms.
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2. Else inherit from the first definition of the parameter in the calling sequence
For example:
.subckt top 1 2
.param param1=50
x1 node1 nested
.subckt nested 1 param1=70
r 1 0 param1
.ends nested
.ends top
Here the param1 is defined in subckt top and is used without definition in the nested
subcircuit nested. Therefore, the resistor r1 will have a value of 50 ohms. The parameter
value will be inherited from the parent subcircuit “top”.
3. Else If 1 and 2 fail then the value is the default value defined in the.subckt statement line.
For example:
subckt top 1 2
x1 node1 nested
.subckt nested 1 param1=70
r 1 0 param1
.ends nested
.ends top
The resistor r1 in this example will be 70 ohms.
Parametrization of subcircuits
Tlsim gives you the ability to parameterize subcircuits. This is best illustrated with the
following example of a macromodel. In this subcircuit, the parasitics in the circuit are
parametrized subcircuit.
.subckt macromodel ibis_file=ibis_models.inc ibis_model=default_IO
. . . .
bmydrives 1 2 3 4 5 model= ibis_model file=ibis_file
. . . .
.ends
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Supported Circuit Elements
The major difference between generic Spice and Espice is that Espice does not yet support
transistor-level devices. However, Espice supports efficient behavioral models, novel
controlled sources and latches, and frequency-dependent, multi-conductor transmission
lines. These additional elements make it possible to perform timing and signal integrity
simulation entirely in the analog domain.
The following are the major classes of devices described in Espice and supported in tlsim.
■
■
Basic elements
❑
Passive elements: resistors, capacitors, inductors and mutual inductors
❑
Single lossless transmission lines
❑
Voltage sources: DC voltage sources, pulsed AC voltage sources, PWL voltage
sources, sinusoidal voltage sources, and exponential voltage sources
❑
Diodes
Controlled source elements:
❑
Voltage controlled current source (VCCS)
❑
Voltage controlled voltage sources (VCVS)
❑
Current controlled voltage source (CCVS)
❑
Current controlled current source (CCCS)
❑
Voltage and current controlled non-linear capacitors and inductors
■
Behavioral active devices defined by IBIS data
■
Frequency-dependent multi-conductor transmission lines
■
Latches: time controlled and voltage controlled latches and hysteresis type latches
■
Linear controlled sources driven by rational transfer functions
■
Controlled sources defined by arbitrary expressions
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Basic Elements
Basic Spice elements are described in this section.
Passive Elements: Resistor, Capacitor, Inductor, Mutual Inductor
General Forms
Rxxxxxxx
Cxxxxxxx
Lxxxxxxx
Kxxxxxxx
n1 n2
n1 n2
n1 n2
Lxxx1
value <L=value>
value
value
Lxxx2 value
The letters R, C, L are the keywords for resistor, capacitor and inductor, respectively. The
node numbers are n1 and n2. <..> indicates optional parameters
Examples
5 ohm resistance connected between nodes 1 and 2:
RS 1 2 5
5 pico farad capacitance connected between nodes 1 and 2:
C1 1 2 5PF
5 nano henry inductance connected between nodes 1 and 2:
L1 1 2 5NH
0.1 ohm resistance and 3n inductor connected between nodes 1 and 2
R 1 2 0.1 L=3n
Mutual Inductor driven by inductors LA and LB. The coupling coefficient should be 0<=k<=1.
K LA LB 0.8
Single Lossless Transmission Line
General Form
Txxxxxxx n1 n2 n3 n4 Z0=value TD=value
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N1 and n2 are the nodes at port 1 and n3 and n4 are the nodes at port 2. In signal applications
n2 and n4 are the reference nodes. They are usually set to 0, the absolute ground. Z0 is the
impedance in ohms. TD is the propagation delay of the transmission line.
Example
T1 2 0 3 0 Z0=50 TD=0.5NS
A 50 ohm, 0.5 nano second delay transmission line connected between 2 and 3 referenced
to ground.
DC Voltage Source
General Form
Vxxxxxxx n1 n2 value
The keyword V identifies in this case a DC voltage source connected between the positive
node n1 and negative node n2.
Example
VDC 5 0 -2
A -2 volt DC source connected between nodes 5 and 0.
Pulsed AC Voltage Source
General Form
Vxxxxxxx n1 n2 PULSE(V1 V2 TD TR TF PW PER)
The keyword PULSE specifies a pulsed AC voltage source with the following parameters:
■
V1 - Initial Value
■
V2 - Final Value
■
TD - Delay Time to Pulse Start
■
TR - Rise Time
■
TF - Fall Time
■
PW - Pulse Width
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PER - Period
■
Example
VIN 4 0 PULSE(0 3.5 0 1.7NS 1NS 10NS 30NS)
A 3.33 Mhz 3.5 volt pulsed source connected between positive terminal 4 and negative
terminal 0, with a rise time of 1.7ns and a fall time of 1ns. See the following figure.
Figure G-3 Pulsed AC Voltage Source
0
1.7n
1n
10 n
30
0
PWL Voltage Source
General Form
Vxxx n1 n2 PWL (T1 V1 <T2 V2 T3 V3......>)
Examples
vclk 7 5 PWL (0 -7 10n -7 11n -3 17n -3 18n -7 50n -7)
Vperiodic 7 5 PWL (0 -7 10n -7 11n -3 17n -3 18n -7 50n -7 ..)
The second statement shows that by adding two periods (..) at the end, the PWL statement
is made periodic. See the following figure. Also see “Controlled Source Elements” on
page 358 for a discussion of PWL (Piecewise Linear Tables).
Figure G-4 PWL Voltage Source
0
10 11
50
17 18
0V
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Sinusoidal Voltage Source
General Form
Vin n1 n2 SIN(VO VA FREQ TD THETA)
Example
VSIG 10 5 SIN (0 .01V 100KHz 1mS 1E4 45)
■
VO (offset) Volts
■
VA (amplitude) Volts
■
FREQ (frequency) Hertz
■
TD (delay) seconds
■
THETA (damping factor) 1/seconds
The shape of the wave form is given by:
0 to Td VO
TD to TSTOP VO +
VA exp (-(t-Td)THETA) sin(2πFREQ(t + TD))
Exponential
General Form
VIN n1 n2 EXP (V1 V2 TD1 TAU1 TD2 TAU2)
Example
VRAMP 10 5 EXP (0V .2V 2uS 20us 40uS 20uS)
■
V1 (initial value) Volts
■
V2 (pulsed value) volts
■
TD1 (rise delay time) default=0 seconds
■
TAU1 (rise time constant) seconds
■
TD2 (fall delay time) seconds
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■
TAU2 (fall time constant) seconds
The shape of the waveform is given by:
0 to TD1 V1
TD1 to TD2 V1 + (V2 - V1)(1 - exp(-(t -TD1)/TAU1)
TD2 to TSTOP V1 + (V2 - V1)(1 - exp(-(t -TD1)/TAU1)
+ (V1 - V2)(1 - exp(-(t -TD2)/TAU2)
Diodes
The statement starting with the keyword D locates the diode in the circuit and identifies which
diode model is used.
General Form
Dxxxxxxx n1 n2 Model_Name
......
......
.MODEL Model_Name Dyyyyyyy IS=value
Specifying a diode requires two statements. At the end of the circuit description a model
control description is entered. This starts with the keyword MODEL and identifies a diode
model as indicated by the key letter D. IS is the saturation current parameter of the diode
which is definable.
Examples
D6 3 4 CUTOFF_0.7V
....
....
.MODEL CUTOFF_0.7V D IS=1e-14
A diode connected between positive node 3 and negative node 4 with a saturation current of
1e-14amperes.
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Controlled Source Elements
Controlled source elements are fundamental to flexible and advanced multi-stage buffer
models, or macromodels. A skillful modeler can develop macromodels to accurately
represent devices containing hundreds or thousands of transistors. The key advantage of
macromodels is their computational efficiency which is an order of magnitude higher than that
of transistor-level models.
Espice has three major classes of controlled sources. Using these practically any engineering
system can be modeled. The three classes are:
■
Expression Driven Controlled sources
■
Controlled sources based on Expression Piecewise Linear Tables (PWL)
■
Based on Rational function with real coefficients
These will be described in the following sections.
Expression Driven Controlled Sources
Tlsim allows expression driven controlled sources for added flexibility. The expressions can
include arbitrary terminal voltages, element currents, symbolic parameters (which can be
passed through subcircuits). In additions expressions can be composed of differentials of any
order with respect of time. Expression can also contain special variables like TIME,
PrevTime, TimeStep.
Expressions can also include IF ELSEIF ELSE conditional statements, making them suitable
for implementation of complex equations.
General Form
Gxxx pos neg i=’<expression>’
Gxxx pos neg v=’<expression>’
In this case the key word can be G,E,H or F. The type of source is actually determined
by the key letters i or v in i=’<expression>’
The <expression> has to be contained within single quotes ‘’.
Let us examine a simple harmonic oscillator.
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Harmonic oscillator - the expression implementation
In the expression format we can directly describe the second differential equation
e 2 0 v=’v(1) - L * C * ddt_2(v(2)) - R * C * ddt_1 (v(2))’
v(i,j) is the voltage difference between nodes i and j (not used in this example)
ddt_i (<expr>) is the ith differential of expression <expr>.
Following are a list of allowed syntactical elements in expressions.
Operators
Both arithmetic and logic operators are supported. They are in the convention of programing
languages C or C++.
Table G-5 Arithmetic Operators
Operator
Function
+
Sum
-
Difference
/
Divide
*
Multiply
^
Exponent
%
Percent
Table G-6 Logical Operators
Operator
Function
&
And
=
Equal
!=
Not equal
|
Or
>
Greater than
<
Less than
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Table G-6 Logical Operators
Operator
Function
>=
Greater than or equal
<=
Less than or equal
Special functions
In general, the syntax for differentials and special function Prev is:
ddt_i ((<expr>) (ddtval_i ddtval_i-1.ddtval_1))
Prev_i ((<expr>)(prevval_i, prevval_i-1,..prevval_1))
The special function ddt_i and Prev_i can take either two or one argument in parenthesis.
ddt_i returns the ith derivative of the expression which should be the first argument. Prev_i
returns ith prev value of the expression. The second argument is optional and specifies the
initial values.
Special variables
The variable TIME returns the current time. The variable PrevTime returns the previous time.
TimeStep is a shortform for (Time - PrevTime).
The following example:
e pos neg v=’sin (2 * PI * Frequency * TIME)’
produces sinusoidal source.
Functions
Expressions can contain any of the following functions:
abs
acos
acosh
asin
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atan
atanh
cos
cosh
exp
ln
log
sin
sinh
sqrt
tan
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Conditional Expressions
The general format is:
IF (<expr1>) (<expr2>) ELSEIF (<expr3>) (<expr4>) ELSE (<expr5>)
If expr1 evaluates to greater or equal to 1, then expr2 is evaluated and so on. Expr1 and expr3
are logic expressions and C-like logic statements (i.e. IF, ELSE, ELSEIF) are allowed.
Examples
Following are few examples that give a flavor of expressions. While expressions can be used
for general circuit problems their generalized implementation makes it suitable for solving
variety of engineering and mathematical problems. Novel applications like solution of non
linear equations are entirely feasible.
Charge Storage Effects in IBIS behavior models.
IBIS 3.0 proposes to include a charge storage transit time parameter. This can be easily
retrofitted to even existing IBIS models using a macromodel subcircuit. A generic
implementation is shown. The transit time parameters are TT_pwr and TT_gnd.
* This is general subcircuit for bhvr model which implements charge storage
* effect defined by transit time parameters TT_pwr and TT_gnd
.subckt chargestoragebuff 1 2 3 4 5 6 7 ibis_file=ibis_models.inc
BUFF=myibisbuff TT_pwr=0 TT_gnd=0
* introduce current probes at the pwrclamp and gndclamp terminals
vpwrcl 60 6 0
vgndcl 7 70 0
* now attach the bhvr drvr - notice it is attched to nodes 60 and 70
bdrvr 1 2 3 4 5 60 70 Model=BUFF File=ibis_file
* now introduce charge storage cpacitor effect
gpwrcl 2 6 i='TT_pwr * ddt(vpwrcl)'
ggndcl 7 2 i='TT_gnd * ddt(vgndcl)'
.ends chargestoragebuff
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Implementation of diode with expression
The following example is a relatively complex subcircuit which implements a diode containing
charge storage effects using expressions and parameters.
.subckt diode pos neg IS=1e-14 RS=1e-4 TT=0 VJ=1 M=0.5 FC=0.5 CJ0=0
rs pos pos2 RS
vp pos2 pos3 0
gd pos3 neg i='IS * (exp (1.6e-19 * v(pos3,neg)/(1.38e-23 * 298)) - 1)'
modifynewton=diodenewton
*gq pos2 neg i='if(TT != 0) (TT * ddt(i(vp))) else (0)' forcecktpartition
gq pos2 neg i='TT * ddt(i(vp))' forcecktpartition
* current due to diffusion charge
vf1 f1 0 '((VJ/(1-M))*(1-(1-FC)^(1-M)))'
vf2 f2 0 '(1-FC)^(1+M)'
vf3 f3 0 '1 - FC*(1+M)'
vfcj fcj 0 'FC * VJ'
gcd pos2 neg i='if (CJ0 <= 0) (0) elseif (v(pos3,neg) < v(fcj))
+ (CJ0 * ((1-(v(pos3,neg)/VJ))^(0-M)) * ddt(v(pos3,neg))) else
+ ((CJ0/v(f2)) * (v(f3) + ((M*v(pos3,neg))/VJ)) *ddt(v(pos3,neg)))'
.ends diode
Notice the example includes the usage of IF ELSEIF conditional expressions. Also notice the
additional keywords modifynewton=diodenewton. This instructs the simulator to use special
newton algorithm diodenewton. Only this algorithm is available in this version. More
specialized algorithms may be available in the future.
Similarly, when the current variable i(v) is used the simulator turns on the circuit partitioning
algorithm. Since in the diode case, it is known that the controlling current is in the same circuit
partition, the special instruction forcecktpartition is invoked to force circuit partitioning which
is more efficient.
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Simple NMOS Transistor
* simple long channel mos device
* from Digital integrated circuits by Jan M. RabAey prentice hall 1996
.subckt mos_1 dr ga sr bu VT0=0.743 PHI=0.6 LAMDA=0.06 KP=2e-5 W=1u L=1u
GAMMA=0
eVT tvt 0 v='if (GAMMA <= 0) (VT0) else (VT0 + GAMMA * (sqrt (abs(v(sr,bu)PHI)) - sqrt(PHI)))'
gds dr sr i='if(v(ga,sr) < v(tvt)) (0) elseif(v(dr,sr) > (v(ga,sr) - v(tvt)))
((KP * W/(2 * L)) * ((v(ga,sr) - v(tvt)) ^ 2) * (1+LAMDA*v(dr,sr))) else ((KP
* W/L) *(((v(ga,sr) - v(tvt)) * v(dr,sr)) - ((v(dr,sr) ^ 2)/2)))'
modifynewton=diodenewton
.ends mos_1
Numerical Integrator
.subckt integ3 in out starttime=0 endtime=0e out 0
+v=’if (time <= starttime) (0)
+elseif ((endtime > 0) && (time > endtime)) (v(out))
+else (prev(v(out)) + (((prev(v(in)) + v(in))/2.0) * timestep))’.
ends integ3
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Table Driven Controlled Sources
An important class of controlled sources implemented in Espice are based on Piecewise
Linear Tables (PWL), they can capture arbitrary non-linearities.
The type of PWL data is captured in DATAPOINTS statements. The datapoints statement is
flexible and allows for different types of data points including v-i (voltage-current), general vv (voltage-voltage, current-voltage, and current-current), voltage-coefficient, and voltageimpedance tables.
General Form
VCCS (voltage controlled current source):
Gxxxx pos neg PWL[SUM] node1 node2 ..
VCVS (voltage controlled voltage source):
Exxxx pos neg PWL[SUM] node1 node2 ..
CCVS (current controlled voltage source):
Fxxxx pos neg PWL[SUM] V1 V2..
CCCS (current controlled current source):
Hxxxx pos neg PWL[SUM] V1 V2 ..
Note: When PWLSUM is used instead of PWL, the multiplication in the above equations is
replaced by summation.
The keywords G,E,F,H identify VCCS, VCVS, CCCS and CCVS respectively. These sources
are connected between positive terminal (pos) and negative terminal (neg). The keyword
PWL identifies that the source is piecewise linear.
For the voltage controlled sources (VCCS and VCVS, keywords G and E respectively), the
node pairs following the PWL keyword are the controlling voltages.
For the current controlled sources, (CCVS and CCCS, keywords F and H respectively), the
voltage sources V1 and V2 provide the controlling currents. For the PWL keyword the value
of the voltage or current is given by:
I/V = f1(V(c1-c2)) * f2(V(c3-c4)) * . . for G and E elements
or
I/V = f1 (I(V1)) * f2 (I(V2)) *
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Non-linear Capacitors
General Form
Gxxxx pos neg PWLSUM c1 c2 ..capacitor=1
Fxxxx pos neg PWL V1 V2..capacitor=1
The elements G and F can also be used to model non-linear capacitors. When used in this
way, the PWL table describes the capacitance value. The redirection to capacitor modeling is
effected by adding parameter capacitor=1 in the primary statement.
Non-linear Inductors
General Form
Exxxx pos neg PWL c1 c2 ... inductor=1
Hxxxx pos neg PWL V1 V2 ..inductor=1
The elements E and H can be used to model non-linear inductors. The redirection to inductor
modeling is effected by adding parameter inductor=1in the primary statement.
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Datapoints Statements
The functions f1, f2 and so on are described by tables of PWL data called DataPoints.
General Form
DATAPOINTS datapoints_type param1=val1 param2=val2 ..
.....
END [DATAPOINTS datapoints_type]
Note: The number of datapoints must be equal to the number of controlling voltages or
currents.
The datapoints_type can be:
■
IMPED - for impedance data
■
COND - admittance = 1.0/IMPED
■
VI - Voltage-current data
■
COEFF - coefficient table
■
VV - General voltage-voltage, current-voltage, current-current tables
■
TIMECOEFF - New dynamic time dependent coefficients which can be specified for
rising and falling states. The rise and fall states are determined by voltage threshold
parameters vlohi and vhilo.
Note: This new coeff should be used for latches and should supersede the following old
style (obsolete) latches.
■
COEFF_ON(OFF)_LATCH - voltage controlled latch
■
COEFF_ON(OFF)_LATCH_TIMECONTROLLED - time controlled latch
■
COEFF_HYSTLATCH - Latch with hysterisis
Non-embedded Datapoints
When the number of datapoints is very large, it may be convenient to keep them in a separate
file rather than in the main circuit description. Versions 13.0 and later allow such redirection
of datapoints.
e 5 0 pwl 1 0 2 0
datapoints vv VV file=dtapts.inc
datapoints coeff Cf file=dtapts.inc
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The VCVS uses datapoints in file dtapts.inc where they stored by name VV and Cf
datapoints vv VV
....
end vv
datapoints coeff Cf
..
..
end Cf
Examples of Controlled Source Elements
One Dimensional Voltage Controlled Impedance
GVI1 1 2 PWL 1 2
DATAPOINTS IMPED
-0.5 36
0 36
1.5 36
2.0 60
END DATAPOINTS IMPED
Figure G-5 One Dimensional Voltage Controlled Impedance
1
R
60
36
2
V
-0.5
1.5
2.0
The variable source is controlled by the voltage across it’s terminals. The v-z behavior of the
source is specified by the datapoints statement.
GVI 1 2 PWL 1 2
DATAPOINTS VI
-5 142ma
0 -132ma
2.5 -110ma
5 0
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6 64ma
8 118ma
END DATAPOINTS VI
Two Dimensional Voltage Controlled Impedance
GVI1 1 2 PWL 1 2 4 0
DATAPOINTS IMPED
-0.5 36
0 36
1.5 36
2.0 60
END IMPED
DATAPOINTS COEFF
1 0
1.25 0.3
5 1.0
END COEFF
Latches
Tlsim supports new timecontrolled coefficient which can be used to construct any kind of
dynamic latches. These are the preferred way to implement latches and other dynamic
effects.
Timecoeff
DATAPOINTS timecoeff vlohi=0.5 vhilo=3
rising
0 1
2n 2
falling
0 2
4n 1
end timecoeff
Timecoeff is the key word. Vlohi and Vhilo are parameters and at least one of them should be
present. The controlling voltage crossing vhilo with a positive slope will mark the beginning of
the rising edge and voltage crossing vlohi with a negative slope will mark the beginning of the
falling edge.Glitches (for example, crossing of vlohi followed by yet another crossing of vlohi)
will cause the time to be reset. The following figure shows the timecoeff (node 2) controlled
by input voltage (at node 1) assuming the previous example.
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Figure G-6 Timecoeff
1
2ns
4R
2
Threshold Controlled Source
The threshold modifiers vlohi and vhilo also can be used in standard datapoints statements.
This allows you to model various types of hysterisis effects. The controlled source has two
sets of tables one for rising and another for falling.
Example 1
datapoints coeff vlohi=0.5 vhilo=0.5
rising
0 0
0.5 0
1 1
falling
1 1
0.5 0.5
0 0
end coeff
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Example 2
* voltage controlled voltager source
* exhibiting hysterisis
vcntrl cntrl 0 pulse (0 1 0 2n 2n 3n 10n)
e 2 0 pwl cntrl 0
datapoints vv vlohi=0.2 vhilo=0.8
rising
0 -1
0.5 0
1 3
falling
1 2
0.5 -1
0 -1
end vv
Other Types of Latches
Latches are older style of datapoints and are superseded by the more general threshold
controlled sources. These are documented for backward compatibility. In a voltage (current)
controlled latch, the latch turn on (off) points are controlled by both the instantaneous value
and the slope. The shape of the latch is further controlled by additional parameters.
DATAPOINTS COEFF_ON(OFF)_LATCH <SWITCHONTIME=val> <SWITCHOFFTIME=val2>
<TRANSITIONINDEPENDENTLATCH=1 or 0> <DURATION=val3>
[Falling OR Rising]
* The first column specifies the controlling value at which the latch comes on.
The second on specifies the width of the on time
col1 col2
END COEFF_ON_LATCH
e_latch 1 2 pwl 3 4
DATAPOINTS COEFF_ON_LATCH SWITHCONTIME=0.1n SWITCHOFFTIME=0.2n
* This latch comes on only during falling transition
falling
* The first column specifies the controlling value at which the latch comes on.
The second on specifies the width of the on time
0.7 1n
end coeff_on_latch
This datapoint statement describes a latch which comes on when the controlling voltage
drops below 0.7 volt and which has a width of 1 nanoseconds. SWITCHONTIME,
SWITCHOFFTIME, and DURATION are optional parameters.
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If duration is specified, then the time value in the second column of the data is ignored. If the
flag TRANSITIONINDEPENDENTLATCH is set, then once the latch comes on it does not
turn off when the slope changes to its opposite value.
Time Controlled Latch
The time controlled latch is a special class of latch which turns on or off during falling and
rising transitions. A time controlled latch is sensitive only to the digital slope (that is rising or
falling) of the controlling voltage. For example:
datapoints coeff_on_latch_timecontrolled
rising
0 5n
end coeff_on_latch_timecontrolled
Both the values after the rising statement specify time. The relative time is reset to zero once
the controlling voltage starts falling.
Hysteresis Latch
The hysteresis latch is a VCVS (a voltage controlled voltage source). See “<Hot>General
Form‚” on page -364 for more information. The hysteresis latch comes on when the
controlling voltage crosses 0.2 volts and is rising. The VCVS reaches its maximum value of
1Volt after 2ns. It starts falling when the controlling voltage goes below 0.8 volt during the
falling transition and eventually reaches its minimum voltage of 0 after 0.5ns.
Ehyst 2 0 PWL 1 0
DATAPOINTS COEFF_HYSTLATCH RISETIME=2n FALLTIME=0.5n RISEVAL=1.0 FALLVAL=0.0
0.2 0.8
END DATAPOINTS COEFF_HYSTLATCH
Simple voltage controlled hysteresis is specified by the simple flag parameter. The datapoints
have both rising and falling sections. When the control value reaches the maximum in the
rising section, the controlling curve becomes a falling curve and vice versa.
Analog Hysterisis
During the rising section the transition from 0 to 2V is triggered at 0 volts while during falling
the transition is triggered at -0.5v.
ESS 2 0 PWL 3 0
DATAPOINTS VV HYSTERISIS=1
Rising
-2 0
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-1 0
0 0
0.499 2
0.5 2
Falling
2 2
0 2
-0.499 0
-2 0.5 0
END DATAPOINTS VV
* controlling voltage
vd 3 0 pwl(0 1 50n 1 60n 1m 80n 1m 90n 1 100n 1 120n -1 140n -1 150n -0.4 160n
-1 180n 0 200n -0.4 230n 1)
Figure G-7 Analog Hysterisis
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Rational Function Controlled Source
Solutions of many important linear circuit problems like filters can be easily represented in
frequency domain. In general circuit variables like voltage and/or current can be represented
as:
I(s) = [H(s)]V(s)
where I is a vector of currents V is a vector of voltages and H is the transfer function matrix
and in this particular case where it relates voltages to current is called the Y parameter. In
general each element of the matrix H(s) can be represented as a rational function.
Σ
H(s) =
ai si
/Σ bi
si
where ai and bi are real coefficients. The rational function form is the algebraic or Laplace
representation of ordinary time domain differential equation meaning that in this form it can
be directly integrated in the time domain simulator.
General Form
Gxxxx
Exxxx
Hxxxx
Fxxxx
pos
pos
pos
pos
neg
neg
neg
neg
RATIONAL
RATIONAL
RATIONAL
RATIONAL
c1
c1
v1
v1
c2
c2
v2
v2
c3 c4 ..
c3 c4 ..
..
..
The syntax is very similar to PWLSUM with the keyword RATIONAL replacing PWLSUM. The
controlled value is a sum. For example let us take the kth element of the current vector in our
general equation.
Ik = Hk1 V1 + Hk2 V2 + .........
where Hki is the transfer function in the kth row and ith column of the H matrix and [V1 V2...]
is the voltage vector. Ik can be directly implemented with a G element. Just like the pwl/
pwlsum each controlling quantity must have a datapoints statement.
DATAPOINTS RATIONAL
NUMERATOR
a0 a1 a2 ..
DENOMINATOR
b0 b1 b2 ...
END DATAPOINTS RATIONAL
RATIONAL,NUMERATOR and DENOMINATOR are key words.
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Harmonic Oscillator
Let us take the example of a second order harmonic oscillator. The oscillator contains resistor
R, inductor L and capacitor C connected in series. The transfer function between input
voltage and the output voltage at the capacitor is described by a second order differential
equation and its corresponding Laplace algebraic form
Figure G-8 Harmonic Oscillator
Vc(s)/Vo(s) = 1/(1 + sRC + s2LC)
R
1
Vo
L
R
2
C
Vo(s)
sL
1/sC
The implementation of the oscillator is:
e2 2 0 rational 1 0
datapoints rational
numerator
1
denominator
1 ‘R*C’ ‘L*C’
end datapoints rational
Notice that datapoints rational can accept parameters like R,L and C.
Y parameters
The rational controlled source is especially convenient for implementing Y parameters. With
general circuit order reduction techniques such as AWE, Complex Frequency Hopping (CFH)
and others large linear networks like power and ground structures can be reduced to Y
parameters where each element is represented by well behaved rational functions. Once
such an Y -parameter is available it is now straight forward to implement it in tlsim.
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IBIS Behavioral Model Elements
IBIS is an industry standard and captures essential performance data of buffers. Devices
containing hundreds of transistors can be accurately characterized in a few tables of data.
The data tables are:
■
Four DC v-i tables, one each for pulldown, pullup, power clamp and ground clamp.
■
v-t tables to capture transient behavior.
The basic behavioral model has 7 external terminals. (A more advanced 11 terminal model
can be used in conjunction with macromodels). This black box behavioral model is internally
implemented using the controlled sources. The following figure shows a schematic of the 7
terminal model
Figure G-9 The 7 Terminal IBIS Behavioral Model
Device
powerclamp putllup
Bdrvr
input
enable
output
V
V
pulldown
groundclamp
The pullup and pulldown sources are switched and turn on or off depending on the control
voltages at the input and enable terminals. The powerclamp and ground clamp are always
on. The switching from pullup to pulldown (or vice versa) is implemented by a switching
function. In the absence of voltage-time data, the shape of this function is fixed. Otherwise
the function is derived from the voltage-time data.
Behavioral Model Syntax
This section describes the operation of 7-terminal behavioral driver(receiver) models. You
can follow these model statements with data which describes the switching behavior: DC v-i
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data, rise/fall time data, logic low and high reference voltages, logic lo and hi state thresholds
(the crossing of these thresholds will be tracked by the simulator) and v-t data. Rather than
embed this much data in the main circuit file, it is recommended that you store the model data
in a separate file and that you specify the file name directly in the Bdrvr statement. (Note: This
differs from standard Spice practice where you insert the parameters for a model in a
separate Model statement)
Finally, please note the following:
■
The v-i tables are not required. If there are no v-i tables present, the device is a simple
capacitor or an open circuit.
■
Any number of v-t tables can be present. The recommended practice is to generate v-t
curves for resistive fixtures only (no reactive elements).
■
The number of datapoints is unrestricted. This is unlike IBIS which limits you to 100
datapoints per table.
General Form
BDRVR (terminals) Model=model_name
File=file_name
Note that when SPECCTRAQuest generates file_name from library data, the file is called
ibis_models.inc. Run any simulation, swing circuit files and you can see an example of
the file’s format and structure.
Note that the following format is permissible but not recommended.
BDRVR (terminals) Model=model_name
.....
.....
.....
.MODEL model_name BDRVR File=file_name
Both the driver and receiver models start with the keyword Bdrvr. Receivers can be modeled
with enable off which simply disables the pullup and pulldown sources.
BDRVRxxxxxxxx n1 n2 n3 n4 n5 n6 n7 [Model=Model_Name File=data_file]
* n1 - Vcc terminal
* n2 - device output
* n3 - Vgnd terminal
* n4 - device input
* n5 - device enable
* n6 - power clamp reference
* n7 - Ground clamp reference
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Figure G-10 The 7 Terminal BDRVR Element Nodes
n1
n6
n4
n2
n5
cn
n7
n3
Optionally, you can store the behavioral driver data under the Model_Name in a data-file:
* start the driver data
DATAPOINTS BDRVR MODEL_NAME
* the device statement has to be followed by data section
* Required version number MODEL_VERSION=2.0
* Required Ac parameters
DATAPOINTS AC_PARAM
VHI_REF=value
VLO_REF=value
RISE_TIME=value
FALL_TIME=value
ENABLE_ON_VOLT=value
ENABLE_OFF_VOLT=value
DVGATEOPEN=value
DVGATECLOSE=value
* optional threshold switching parameters
VIN_LO_THREHHOLD=value
VIN_HI_THRESHHOLD=value
END AC_PARAM
* Logic parameters (optional)
DATAPOINTS LOGIC_PARAM
VHI_MIN=value
VHI_MAX=value
VLO_MIN=value
VLO_MAX=value
END LOGIC_PARAM
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* Optional data which specifies the references voltages for the DC v-i curves
PullUpReference=5.0
PullDownReference=0.0
PowerClampReference=5.0
GroundClampReference=0.0
* Required pull up data
* the syntax is
*DATAPOINTS data_points_type ibis-data-keyword
DATAPOINTS VI PULL_UP
-10
-0.142
-2
-0.098
-0.5 -0.038
0
0
1
0.064
5
0.137
...
END VI PULL_UP
*optional power clamp data
DATAPOINTS VI POWER_CLAMP
...
...
END VI POWER_CLAMP
*optional pull_up switching function
DATAPOINTS COEFF PULL_UP
*optional rising statement
RISING
...
...
*optional falling statement
FALLING
...
...
END COEFF PULL_UP
* Required pull down data
DATAPOINTS VI PULL_DOWN
-1
-0.07
0
0
0.5
0.07
1
0.127
...
END VI PULL_DOWN
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*optional ground clamp data
DATAPOINTS VI GROUND_CLAMP
...
...
END VI GROUND_CLAMP
*optional pull_down switching function DATAPOINTS COEFF PULL_DOWN
...
...
END COEFF PULL_DOWN
* optional parasitics data
DATAPOINTS PARASITICS
* component parasitics
C_COMP=value
END PARASITICS
* ibis 2.0 v-t specifications.
* IBIS 2.0 version allows the insertion of non-linear ramp data .
* These data can be included as
* a set of t-v curves generated in a test fixture. The generation
* of tv data is done for fixed set of parameters for the
* Device Under Test (DUT) and the test fixture. These parameters are
* Rdut, Ldut and Cdut for the DUT and R_fixture L_fixture, C_fixture
* and V_fixture for the fixture. The parameters R_fixture and V_fixture
* are required while the others are optional.
DATAPOINTS RISINGWAVEFORM R_fixture=60 V_fixture=3.3
0.0ns 0.608
2.5ns 0.607
...
...
6.5ns 3.3
END RISINGWAVEFORM
DATAPOINTS RISINGWAVEFORM R_fixture=100 V_fixture=3.3
...
...
END RISINGWAVEFORM
DATAPOINTS FALLINWAVEFORM R_fixture=60 V_fixture=3.3
...
...
END FALLINGWAVEFORM
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Adding Terminators
You can add shunt terminators as described in IBIS 2.1
datapoints bdrvr mybuffer
..
Rpower=100000
Rgnd=100000
Rac=1000000
Cac=2
...
For a complete description refer to the IBIS specification.
Following is an example of a bdrvr model expressed in Espice. When using
SPECCTRAQuest version 14.0 or later, you can use this model in SigXplorer as an Ntermianl black box model or directly with an independant voltage source (contained in another
Espice black box).
Example
"e:\more_es_bdrvrs\es_bdrivers.dml"
(LibraryVersion 136.2 )
(PackagedDevice
(JB_ES_FAST
(ESpice ".subckt JB_ES_FAST 1 2 3 4 5 6 7
.node_param 1 print
.node_param 2 print
.node_param 3 print
.node_param 4 print
.node_param 5 print
.node_param 6 print
.node_param 7 print
*****************************************************
* driver
bdrvr2 101 102 103 104 105 106 107 Model=JB_IO_Fast thresholdswitch=1 vlohi=2.8
vhilo=2.0
.model JB_IO_Fast bdrvr
DATAPOINTS BDRVR JB_IO_Fast
MODEL_VERSION=2.0
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PullUpReference=5
PullDownReference=0
PowerClampReference=5
GroundClampReference=0
DATAPOINTS AC_PARAM
dVGateOpen=1
dVGateClose=0
ENABLE_ON_VOLT=1
ENABLE_OFF_VOLT=0
RISE_TIME=8e-10
FALL_TIME=8e-10
dVdtr=6.25e+09
dVdtf=6.25e+09
END AC_PARAM
DATAPOINTS LOGIC_PARAM
VHI_MIN=3.1
VLO_MAX=2.1
OUTPUT_VHI_MIN=4.5
OUTPUT_VLO_MAX=0.1
END LOGIC_PARAM
DATAPOINTS VI POWER_CLAMP
0 0
0.1 0
0.4 0.0001
0.5 0.0006
0.6 0.0012
0.7 0.0024
0.8 0.006
0.9 0.013
1 0.025
5 0.293
END VI POWER_CLAMP
DATAPOINTS VI ground_clamp
0 0
-0.1 0
-0.4 -0.0001
-0.5 -0.0005
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-0.6 -0.0012
-0.7 -0.0024
-0.8 -0.006
-0.9 -0.013
-1 -0.025
-5 -0.293
END VI ground_clamp
DATAPOINTS VI PULL_UP
-10 -0.147
-5 -0.142
-4.5 -0.138
-4 -0.133
-3.5 -0.128
-3 -0.123
-2.5 -0.115
-2 -0.103
-1.5 -0.088
-1 -0.069
-0.5 -0.043
0 0
1 0.069
2 0.103
3 0.123
4 0.131
5 0.142
END VI PULL_UP
DATAPOINTS VI pull_down
-5 -0.225
-4 -0.217
-3 -0.212
-2 -0.193
-1 -0.075
0 0
0.5 0.075
1 0.132
1.5 0.169
2 0.193
2.5 0.208
3 0.212
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3.5 0.215
4 0.217
4.5 0.219
5 0.22
10 0.225
END VI pull_down
DATAPOINTS PARASITICS
C_COMP=3e-12
END PARASITICS
END BDRVR JB_IO_Fast
Rpu 101 1 0.001
Rpkg 102 2 0.001
Rpd 103 3 0.001
Rin 104 4 0.001
Ren 105 5 0.001
Rpc 106 6 0.001
Rgc 107 7 0.001
*****************************************************
.ends JB_ES_FAST
" ) ) ) )
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Charge Storage Parameters
The IBIS 3.0 charge storage parameters can be included. For example:
TTpower=1n
TTgnd=1
Refer to the IBIS 3.0 for a description of these parameters.
Advanced Behavior models: 11 terminal model
You can specify 11 terminals for behavior bdrvs models. The voltages at the extra 4 terminals
(with reference to absolute ground) directly multiply the pullup, pulldown, power clamp and
ground clamp vi tables respectively making it possible to dynamically control and scale these
current sources.
For example - boost pullup by 20 % and pulldown by 30 %
Bdrvr 1 2 3 4 5 6 7 8 9 10 11 Model=buff File=ibis_file
v_pullupx 8 0 1.2
v_pulldownx 9 0 1.3
v_powerclamp 10 0 1
v_groundclamp 11 0 1
Behavior Models: Modifying Switching Function
One of the important aspect of a behavior model is its switching behavior. i.e how it switches
from pullup to pulldown and vice versa. The basic model with no v-t curves given the default
switching is implemented as VCCS with the input voltage value controlling the switching
function. During switching, the coefficient monotonically increases from 0 to1 during the
duration of rise time for the pullup and vice versa for the pulldown. By default the input voltage
zero means the pullup is completely shutoff and 1 means the pull down is completely shut off.
In the presence of vt curves the switching function is timecoeff based rather than being
dependent on input voltage value. By default the start of rising is denoted by positive slope at
voltage 0 and negative slope at input voltage 1. A drawback of this approach is numerical
instability and false switching that can arise if the input node voltage is not a simple source or
floating as during simultaneous switching. A robust way to solve this problem is to make
switching a truly a threshold driven timecoeff by forcing the bdrvr switching to be based on
input voltage thresholds vlohi and vhilo which are defined in the IBIS data. Note that in this
case the input voltage has to swing from vgnd to Vcc or the full logic swing rather than 0 to 1
as in the default case. The modification to threshold switching is enabled by specifying
threholdswitch parameter in bdrvr statement.
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bdrvr 1 2 3 4 5 6 7 Model=buff file=ibis_file
thresholdswitch=1
It is also possible to modify/change the threshold parameters vlohi and vhilo on an instant by
instant basis in conjunction with the thresholdswitch parameter.
bdrvr 1 2 3 4 5 6 7 Model=buff file=ibis_file
thresholdswitch=1 vlohi=0.5 vhilo=0.5
The internal C_comp also can be scaled with the switch C_compX
bdrvr 1 2 3 4 5 6 7 Model=buff file=ibis_file
C_compX=0
Behavior Models: Prescaling VI and TV curves
We have already seen how the VI curves can be dynamically scaled. This is important in
applications like simultaneous switching where VI degradation takes place. But in other
applications like buffer design you may need a convenient way to prescale an existing buffer.
The VI and Tv curves in Bdrvrs can be scaled on an instance basis.
bdrvr 1 2 3 4 5 6 7 Model=buff file=ibis_file VIScale_pullup=1.2
TVScale_rise1=0.8
The prefix VIScale should be followed with an underscore. The 4 VI curve scaling keywords
are:
VIScale_pullup, VIScale_pulldown,
VIScale_powerclamp, VIScale_groundclamp
Note that the scaling is for the current.
TVScale scales or stretches the time in tv. Unlike the vi curves you can have any number of
tv curves and they can be individually scaled. The curves are identified by a name. For
example, the modifier:
TVScale_rise1=0.8
slows the time in the tv by a factor of 0.8 curve identified as rise1.
The rise1 label should be in the bdrvr model data in the form of:
DATAPOINTS TV rise1 v_fixture=1.5 r-fixture=50
..
END TV
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VI and TV prescaling at the model level
Modifying the Bdrvr statement affects the Vi and Tv curves of the model buffer only for that
particular instance. The original model is unaltered. if scaling is required on a more global
model level, a scaling section can be introduce the Datapoints Bdrvr buff model statement.
DATAPOINTS BDRVR buff
..
datapoints vi_scalingfactors
pullup=0.5
pulldown=0.5
end vi_scalingfactors
datapoints tv_scalingfactors
rise_1=0.5
rise_2=0.5
fall_1=0.2
fall_2=0.2
end tv_scalingfactors
..
end bdrvr buff
VT curves and Switching: a discussion
It is commonly assumed that merely by placing v-t curves switching can be completely
specified and more accurate. However this is not true i.e. the switching coefficient does not
uniquely fall out of vt curves. To derive switching coefficient a priori assumptions about
switching have to be made. Many different switching coefficients can exactly reproduce
switching behavior at the specified test fixture load. By default the switching coefficient
computed by the bdrvr models satisfy the following:
1. For devices with either only pullup or pulldown, the switching coefficient is a function of
time and voltage. In case of only one vt data /rise and fall this will reduce to a function of
time alone.
2. In models with both pullup and pulldown the switching function will be a function of time
only for upto 4 vt curves (2 rise and 2 fall curves). For more than 4 vt curves the switching
coeff is function of both time and voltage. This algorithm ensures correct operation for
both devices with slew control (distinct turn off and turn on time for pullup and pulldown)
and without. This algorithm can be modified at a global level (at tlsim command line) to
make the switching coeff a function of both time ad voltage by specifying the switch BhvrTvPreferDomtimedepcoeffOff.
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In devices with less than 4 vt curves and containing both pullup and pulldown the switching
coefficient operates in such a manner that provides continuous and smooth transitions
between pullup and pulldown. This can be changed to more discontinuous switching by
adding the instance specific parameter pullUpOnRisepulldownOnFall. This will ensure that
during pulldown only pullup is completely shutoff and vice versa.
Finally there is a general notion that vt curves, since they are generated for a particular load,
switching to be load dependent. This notion is incorrect. The coefficient in these behavioral
models is mainly time (i.e. relative rise and fall times) dependent (this equivalent to saying
that the transient behavior is primarily determined by the changes the gate to source voltage).
So first, the selection of a load for vt curve generation is not that critical and secondly just
adding more vt curves generated for different loads does not add to accuracy. It simply adds
to the overhead.
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Multi-Conductor Transmission Line Models
The tlsim simulator implements advanced state of the art, multi-conductor, coupled
transmission line models. The following schematic shows the circuit model for a multiconductor line.
Figure G-11 Multi-conductorLine Circuit Model
Wa
Wb
G
Y
Y G
The internal implementation of the model consists of a frequency-dependent admittance
Matrix Y and a delayed controlled current source G at the input and output terminals.
The circuit parameters are derived from frequency-dependent RLGC parameters. These
parameters are specified in separate input files. Alternatively the RLGC parameters can be
embedded in the Spice file.
The syntax for a multi-conductor line follows:
Nxxxxxxxx (ni1 ni2 ....nri) (no1 no2 ..... nro)
L=length-in-meters [file=RLGC_input_file_name rlgc_name=data_name_tag
skin_cutoff_freq=fskin dielecloss_cutoff_freq=fdielec]
The optional parentheses separate the input and output terminals. The words nri and nro
denote the reference nodes. The field L= specifies the length of coupled transmission
line system in meters. If L=0 then the RLGC matrix will be treated as a lumped model.
Use the parameters skin_cutoff_freq and dielectric_cutoff_freq when only one RLGC
matrix (freq=0) is available but you need to model skin effect, or dielectric loss, or both.
Examples of Multi-Conductor Elements
NTL_2CONDUCTOR (1 2 0) (3 4 0) L=0.0005 [rlgc_name=Data-name-tag
file=RLGC_2COND_FILE ]
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RLGC_2COND_FILE entries
*Specify frequency in cycles/second
* Note: If the frequency statement is left out, it will be assumed that the
rlgc data is *frequency independent. In this case there SHOULD be only ONE set
of rlgc data
FREQUENCY=100HZ
* Now specify the matrix entries row by row
* Specify values per unit length
* for Rmatrix the value is in ohm/meter
* L = henries/meter
* c = farads/ meter
* G in Siemens (1/ohm)/meter
RMATRIX
1.2 0
0 1.2
LMATRIX
...
...
CMATRIX
...
...
GMATRIX
...
...
FREQUENCY=1000
....
....
Embedded ntl statements
An alternate way of entering the RLGC data is to embed it directly in the Spice file. In this
case the embedded data has to come after the n-conductor NTL statement. Note that the file
name is omitted from the NTL statement.
NTL_2CONDUCTOR (1 2 0) (3 4 0) L=0.0005
DATAPOINTS RLGC
FREQUENCY=1000
RMATRIX
1.2 0
0 1.2
LMATRIX
...
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...
CMATRIX
...
...
GMATRIX
...
...
FREQUENCY=100000
....
....
END RLGC
Optionally, you can specify frequency dependence using the keywords skin_cutoff_freq and
dielecloss_cutoff_freq. These become operational only if the number of frequency datapoints
in the DATAPOINTS section is 1.
The mathematical form for the skin_cutoff_freq keyword is the same as that in the skin effect
resistor. For example:
R = Rdc, where f <= fc
R = Rdc sqrt(f/fc), where f > fc
For the conductance, it is:
G = Gdc, where f <= fc
G = Gdc * f/fc, where f > fc
Lumped RLGC with L=0
The lumped RLGC matrix is a special case of multi-conductor line with the length of the multiconductor set to 0. The syntax is identical to that of a multi-conductor line with L=0.0
Nxxxxxxxx (ni1 ni2 ....nri) (no1 no2 ..... nro)
L=0.0 file=LC_input_file_name
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Control Statements
Tlsim also supports spice like control statements. The control statements start with a period
(.) character. The following statements are supported.
END Statement
The .END statement identifies the end of the main program.
SUBCKT Statement
The .SUBCKT statement identifies the start of a subcircuit. For more detail, see “Subcircuits”
on page 349.
ENDS Statement
The .ENDS statement identifies end of subckt statement.
PARAM Statement
The .PARAM statement creates a parameter. The syntax is:
.param name=value
For more detail, see “Parameters and Expressions” on page 348.
NODE_PARAM Statement
The .NODE_PARAM statement is used to (re)assign name and logic values to circuit nodes.
The syntax is:
.node_param nodeid param1=value1 param2=value2
Nodeid is the original node id. The allowed parameter keywords are NAME, VHI_MIN,
VHI_MAX, VLO_MIN, VLO_MAX, CYCLE, VMEAS.
Note: VHI_MIN and VLO_MAX are particularly important. They are reserved keywords.
Using these values tlsim can define cycle measurements. Please note that for nodes which
are the output of an IBIS buffer, the VHI_MIN and VLO_MAX are usually defined in the buffer
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data. When this is true, these values will override the values defined in the node_param
statement.
The value of NAME is a string, the other values are floating point voltage values.
In addition two boolean parameters are supported: PRINT and REFNODE. The parameter
PRINT says the node values have to be printed and REFNODE identifies the node as the
reference node from which simple “flight” propagation delay measurements have to be made.
The boolean parameters need not be followed by the equal (=) sign.
Cycle Measurements
You can insert special cycle measurement controls in node_param statement. For example:
.node_param 2 cyclecount=3 print
will cycle measurement for the 3rd cycle.
.node_param 2 cycle=(2 5)
will print cycle measurements for the 2nd and the 5th cycle.
With the above statement the simulator will try to simulate till node 2 passes its maximum
cycle. It will also output cycle measurement in the cycle file. (which is by default cycle.sim).
The cycle measurement consists of the following:
Figure G-12 Cycle Measurement
Rise
Fall
Vhi_MIN
Vlo_Max
1 cycle
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TimeWindowMeasurements
Minimum and maximum voltage measurements can also be made in named time windows.
For example:
.node_param 2 timewindowpairs=(a 9.04n 10.72n b 16.32n 17.52n)
This will output the maximum and min voltages in windows (between 9.04 nanoseconds and
10.72 nanoseconds) and window b (16.32 n to 17.52n).
Arbitrary voltage crossings
Measurements can be made of crossing points of arbitrary voltage. The one requirement is
that these crossings have names other than reserved names like vlo_hi. for example
.node_param 2 v1.1=1.1
will measure the time crossing points of 1.1volt and the measurements will appear under the
label ‘v1.1’.
NODE_PARM_DIFFERENTIAL Statement
This statement is very similar to.NODE_PARAM except it measures the differential voltages
between two nodes, a primary and a secondary one.
.node_param_differential node1 node2 param1=value1 param2=value2
PRINT Statement
.PRINT statement
The standard Spice print statement is used to print currents through special zero voltage
sources. For example:
V_probe 1 2 0
.print I(V_probe)
Specifying derived names in node param statement
In some instances it may be necessary to use node param statements inside a subcircuit. The
standard syntax allows you to specify only one name. However, this presents a problem when
the subcircuit is used multiple times. For example:
x 1 sckt
x2 2 sckt
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.subckt sckt 1
.node_param 1 name=sckt_name print
.ends sckt
In the above case the printed output will contain value for only node 2 in the main circuit.
Espice solves this problem by allowing derived names in node_param statements.
x 1 sckt
x2 2 sckt
.node_param 1 name=firstnode
.node_param 2 name=secondnode
.subckt sckt 1
.node_param 1 name=(name(1)_derived) print
.ends sckt
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Now two names will be created:
firstnode_derived and secondnode_derived. The statement name() acts like a function;
name(1) substitutes the name of node 1. The additional string “_derived” is merely appended.
(Naturally you can also prepend it).The enclosing parenthesis name=(..) is required to use
the name function.
Inheriting node parameters
You can also inherit parameters of another node, instead of repeating the same properties.
For example:
.node_param 2 inherit=(1)
.node_param_diff 2 3 inherit=(1 5)
The caveat is nodes 1 and 5 should have been defined first. The inherit will pull in all the cycle
values, and voltage values.
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Creating Espice Models for use with SPECCTRAquest
Before SPECCTRAQuest and SigXplorer can be used to simulate, you must populate their
library with DML format models for all the active and passive parts in the nets to be
simulated.You may choose to obtain simulation models from third parties in DML format, or
they can be obtained in IBIS format and translated to DML using the Cadence IBIS import
utility. Alternatively, you may opt to directly create your own DML models. Note that if your
models are already in the Spice format, it is often very simple to represent them in Espice.
The creation of models using standard DML features is described in the appendix “DML
Syntax” on page 277. Since you are reading this, it is assumed that you need to create a
simulation model that has some atypical behavior that requires building a description in
Espice.
Espice simulation models can be included into DML libraries in a number of ways. Two
methods are described bellow.
Espice Packaged Part
You can create a packaged part whose behavior is wholly described in Espice using the
syntax in the examples below:
Example 1 - Simple RC filter
(PackagedDevice
(MyEspiceRcFilter
(ESpice
". MyEspiceRcFilter 2 1
R1 1 2 22
C1 0 2 20p
.ends MyEspiceRcFilter”
)
)
)
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Example 2 - Simple Series Resistor
(PackagedDevice
(MyESpiceResistor
(ESpice
".subckt MyESpiceResistor 2 1
R1 2 1 22
.ends MyESpiceResistor
"
)
(PinConnections
(1 2 )
(2 1 )
)
)
)
This example includes a PinConnections section that indicates that this part is a series
element that can electrically connect two PCB nets to create an extended net. The pin
connections section includes pin pairs. Entries are directional from the first pin to the second,
so if the connection is bi-directional (which is usual for passive devices) two entries should
exist for each pin pair.
Note: The external node names in the Espice subcircuit are used as the pin names in the
library component and must match those in the PCB symbol. Also, the whole of the Espice
description must be within double quotation marks. Comments can be written inside the
double quotations by starting thew comment with an asterisk (*).
You are free to use any name for the Espice subcircuit since the tool uses the packaged
device name to locate the correct library entry. For ease of readability, the subcircuit name is
usually set to be the same as the packaged device name.
Example 3 - A Thevenin Terminator Package
(PackagedDevice
(MyEspiceTerminator
(ESpice
".subckt MyEspiceTerminator G1 S1 S2 G2
R1 S1 G1 220
R1a S1 G2 330
R2 S2 G1 220
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R2a S2 G2 330
.ends MyEspiceTerminator"
)
(PinConnections
(S1 G1)
(S2 G2)
(S2 G1)
(S2 G2)
)
)
)
Example 4 - Alternative Version of a Thelvin Terminator package
(PackagedDevice
(MyEspiceTerminator
(ESpice
".subckt MyEspiceTerminator G1 S1 S2 G2
X1 S1 G1 G2 MyResistors
X2 S2 G1 G2 MyResistors
.ends MyEspiceTerminator
.subckt MyResistors 1 C1 C2
R1 1 C1 220
R2 1 C2 330
.ends MyResistors"
)
(PinConnections
(S1 G1)
(S2 G2)
(S2 G1)
(S2 G2)
)
)
)
Note: The same functionality can be obtained using a DML terminator model.
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How to use Sources and Other Functions in SigXplorer using Espice
Devices
General Notes / Warning About Using Espice Devices
■
You can use any/all spice elements, but the first one in the netlist must be either an R, L,
or C.
■
The nodes used on the .subckt line must be 1 and 2 (you can use any alphanumeric
nodes in the subcircuit).
■
There is no post-checking/format on your circuit, as such, be sure your syntax is good
and all spice elements begin in column 1.
Voltage Source
When studying the behavior of a certain interconnect (or for other reasons), it is often
desireable to use a simple voltage source (or Thevenin source) to drive the system. This can
be easily done using an Espice device and Custom Stimulus.
Here’s how:
1. Build the desired source.
2. Add a disabled driver to the circuit.
Step 2 is required because the simulation will be aborted if there are no eligible drivers in the
topology, and SigXplorer is not smart enough to realize that there’s an active Vsource that
takes the place of a driver. You can fool the tool by adding an IO (tri-stateable) driver and then
holding its ENABLE line low (to a zero level) until just prior to the end of the simulation. Use
Custom Stimulus to do this.
Here’s examples of two Vsources you can use (be sure to connect node 2 to ground)
implemented as PULSE and PWL:
(“ideal_source”
(“ESpice”
“.subckt ideal_source 1 2
Rdud 1 3 0.00001
V1 3 2 PULSE (0 2.5 0n 1n 1n 8n 20n)
.ends ideal_source
“)
)
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(“thevenin_source”
(“ESpice”
“.subckt thevenin_source 1 2
R1 1 3 50
V1 3 2 PWL (0 1 2e-008 1.0 2.1e-008 0 4e-008 0 4.1e-008 1.0 6e-008 1.0 6.1e-008 0
1e-007 0)
.ends thevenin_source
“)
)
Table-Driven (VI) Diode
SPECCTRAQuest does have Generic Element Diodes, however they are mostly ideal and
hard-coded (you can only set the saturation current and threshold voltage). Here’s an
example of a table-driven diode that you might want to use (repleace with your VI table) that
also embeds series resistance and junction capacitance:
(“table_diode”
(“ESpice”
“.subckt table_diode 1 2
Rseries 1 anode 0.2
Cjunction anode 0 1.2p
G1 anode 2 PWL 1 2
datapoints vi
0
0
0.6
0
0.65
3e-3
0.7
6e-3
1.0
15e-3
2.3
300e-3
end datapoints vi
.ends table_diode”)
)
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IO Buffer Model using an Espice Macrocell
Example 1 - Macromodel Starter File
(“macromodel_starter.dml”
; this is the filename
;
; This is a “starter” file to use when you need to build a macromodel.
; It is as simple as the tool will allow. Any arbitrary/complex circuit
; could be created in the subcircuit section below. The “starter” model
; implemented here is very simple, just embedding an output resistor in
; the default IO cell. You must have the default library loaded for this
; to work.
;
; Some tips:
;
1) Watch your parenthesis matching, the tool is picky about these.
;
2) When debugging, look in tlsim.log for clues. An error message
;
to the screen like “cycle.msm does not exist” probably means
;
the simulator failed to compile your subcircuit.
;
3) When testing/modifying the file, be careful. You can remove/
;
re-add the library dml, delete and replace the component, but
;
still not get the updated change. Unfortunately, the safest thing
;
to do is exit and re-enter the tool.
;
4) For guidance/examples, consult an updated “Kspice Syntax Specification”
;
and cds/share/pcb/signal/cds_macromodels.dml.
;
; Everything down to ‘(Subcircuits “‘ is wrapper info for your macromodel
; to make sure the tool uses it correctly, and it is integrated into the UI.
;
(IbisIOCell
; this says we’re doing buffers, not packages etc
(starter
; This is the name that appears in the library browser
; and must match the name in the .subckt defined below.
(Model
(ModelType IO ) ; will decide which SigXp symbol is used
)
(Ramp
; The dt values below control the input stimulus edge speed.
; They are programmed to 1,2,3 ns rise/fall since tr/f = dt/0.6.
; These must be here, or you will get a divide by zero error.
(Rise
(minimum
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(dt 0.6n
(typical
(dt 1.2n
(maximum
(dt 1.8n
(Fall
(minimum
(dt 0.6n
(typical
(dt 1.2n
(maximum
(dt 1.8n
) )
) )
) ) )
) )
) )
) ) ) )
;
; Define the various “Thresholds” if they will be used for measurements
;
;
(LogicThresholds
;
(Input
;
(High
;
(typical 1.2 ) )
;
(Low
;
(typical 0.8 ) ) )
;
(Output
;
(High
;
(typical 1.4 ) )
;
(Low
;
(typical 0.6 ) ) ) )
;
; The following reference voltages will probably be needed
; to ensure that the correct voltages are used.
;
(PullUp
(ReferenceVoltage
(maximum 3 )
(minimum 1 )
(typical 2 ) ) )
;
(PullDown
;
(ReferenceVoltage
;
(maximum 0 )
;
(minimum 0 )
;
(typical 0 ) ) )
;
(GroundClamp
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;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
(ReferenceVoltage
(maximum 0 )
(minimum 0 )
(typical 0 ) ) )
(PowerClamp
(ReferenceVoltage
(maximum 1.5 )
(minimum 1.5 )
(typical 1.5 ) ) )
(MacroModel
(Parameters
(Buffers
; This section is mandatory, but can be faked if not needed.
(BUFF CDSDefaultIO)))
(NumberOfTerminals 7 )
; you can specify the # of terminals
(MacroType DiffIO )
; not clear on use/value of this - DiffI_SO
If there’s other terminals you want available for Custom Measurements
AND to be editable in the Stimulus Editor, add them here...
(PinTerminalsMap
(4 Data )
(5 Enable ) )
(SubCircuits “
The comment character inside the SubCircuits double quotes is a *.
*
*
* Handy bdrvr node cheat sheet:
*
power = 1
*
output = 2
*
ground = 3
*
input = 4
*
enable = 5
*
power-clmap_reference = 6
*
ground clamp reference = 7
* Node group 8-11 is optional:
*
scale factor: pullup = 8
*
scale factor: pulldown = 9
*
scale factor: powerclamp = 10
*
scale factor: groundclamp = 11
*
.subckt starter 1 2 3 4 5 6 7 ibis_file=ibis_models.inc BUFF=CDSDefaultIO
*
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bdrvr 1 20 3 4 5 6 7 model=BUFF file=ibis_file
Rout 2 20 30
*
* You can cause any node to be printed, and give it any name you like
* as shown here:
.node_param 4 name=(name(2).input) print
.node_param 20 name=(name(2).inside_resistor) print
*
.ends starter
“ ) ) ) ) )
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Glossary
A
AC impedance
The combination of resistance, capacitive reactance, and inductive reactance seen by AC
and/or time-varying voltage. (See alternating current.)
alternating current (AC)
A current that varies with time. This label is commonly applied to a power source that switches
polarity many times per second, such as the power supplied by utilities. May take a sinusoidal
shape, but could be a square or triangular wave shape.
amplitude
The height or magnitude of a voltage signal as measured with respect to a reference plane,
such as signal ground.
attenuation
Reduction in the amplitude of a signal due to losses in the media through which it is
transmitted.
B
backporching
A term used to describe the reflections that follow a fast rise or fall time signal traveling down
a long transmission line that has not been properly terminated. Looks like a stair step.
busbar
A large copper or brass bar used to carry high power supply currents onto a printed board or
backplane.
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C
capacitance
A measure of the ability of two adjacent conductors separated by an insulator to hold a charge
when a voltage is impressed between them. Measured in Farads.
characteristic impedance
A value at a given instance in time of a transmission line that appears to an electrical signal
as a resistance (a voltage to current ratio). The resistance, capacitance, and inductance of a
transmission line combine to impede the charge flow.
coaxial
A term used to describe conductors that are concentric about a central axis. Takes the form
of a central wire surrounded by a conductor tube that serves as a shield and ground. May
have a dielectric other than air between the conductors.
crosstalk
Signal transmission from one conductor to another by mutual coupling of electromagnetic
fields. In a PCB layout, parallel etch can generate significant crosstalk. Crosstalk can be
categorized as forward or backwards.
current
Electrons traveling in a conductor as the result of a voltage difference between its ends.
D
decoupling
Absorbing noise pulses generated in the power supply lines by switching logic so as to
prevent them from disturbing other logic on the same power supply circuit. Usually done with
capacitors.
direct current (DC)
A current produced by a voltage source that does not vary with time. Normally provided by
power supplies to power electronic circuits.
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dissipation factor
A factor used to express the tendency of insulators or dielectrics to absorb some of the energy
in an AC signal.
dual-strip line
A stripline signal conductor that is embedded between two ground planes, and is not centered
between them (closer to one ground plane than the other).
E
edge rate
The rate of change in voltage with time of a logic signal transition. Usually expressed in volts
per nanosecond.
edge transition attenuation
The loss in sharpness of a switching edge caused by absorption of the highest frequency
components by the transmission line.
electromagnetic interference (EMI)
Radiated electromagnetic energy that couples into conductors where it is not wanted.
F
fall time
Time required for a logic signal to switch from its high state to its low state. Commonly
measured between the 80% and 20% voltage levels.
final settle delay
This is determined by subtracting the associated buffer delay from a simulation
measurement. For example, on a rising (falling) edge, the simulation measurement is from
time zero in the simulation to when the receiver crosses its Vih (Vil) switching threshold the
final time and settles into the high (low) logic state. The associated rising (falling) buffer delay
of the driving IOCell is subtracted from this measurement value to produce the reported final
settle delay.
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first switch delay
This is determined by subtracting the associated buffer delay from a simulation
measurement. For example, on a rising (falling) edge, the simulation measurement is from
time zero in the simulation to when the receiver first crosses its Vil (Vih) switching threshold.
The associated rising (falling) buffer delay of the driving IOCell is subtracted from this
measurement value to produce the reported first switch delay.
flat conductor
A rectangular conductor that is wider than it is high. Usually refers to signal conductors in a
printed wiring board.
G
ground
A term used to describe the terminal of a voltage source that serves as a measurement
reference for all voltages in the system. Often the negative terminal of the power source, but
sometimes the positive terminal.
I
impedance
The resistance to the flow of current represented by an electrical network. May be resistive
or reactive, or both.
inductance
The property of a conductor that allows it to store energy in a magnetic field induced by a
current flowing through it.
L
line coupling
Coupling between two transmission lines caused by their mutual inductance and the
capacitance between them.
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load capacitance
The capacitance seen by the output of a logic circuit or other signal source. Usually the sum
of distributed line capacitance and input capacitances of the load circuits.
logic
A general term used to describe the functional circuits used in computers and other digital
electronics to perform computational functions.
Logic Family
A collection of logic functions or ICs using the same form of electronic circuit to perform
computation.
lossy
A transmission line that has resistance, causing it to dissipate some power as current passes
through.
M
multi-line simulation
A simulation of two or more coupled networks, for example in a comprehensive simulation.
N
noise immunity
The worst-case difference between the output voltages produced by a driver pin and the input
voltages that a receiver pin still interprets correctly when operated in an ideal environment.
This presumes equal junction temperatures and no other sources of signal noise other than
typical device manufacturing variations. This value is calculated and supplied by part
manufacturers for a given logic family. For example, the noise immunity for Motorola 10KH
ECL technology is 150mV.
noise margin
For a receiver in the high (low) state, the magnitude of the delta between the lowest (highest)
excursion in the negative (positive) direction, and the Vih (Vil) voltage threshold.
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O
overshoot
Voltage swing beyond the steady state voltage. Voltages that exceed the logic range of the
receiver (for example, voltages greater than the maximum or lower than the minimum) can
damage devices.
P
PCB
Printed Circuit Board
parallel pair
Two conductors that travel side-by-side at a controlled spacing over a long distance.
permeability
A general term used to express various relationships between magnetic induction and
magnetizing force.
pin-to-pin connection
A signal path from a particular driver pin to a particular receiver pin. For example, a network
with two drivers and three receivers has six possible pin-to-pin connections.
power dissipation
Energy used by an electronic device in the performance of its function.
propagation delay
The delay in wave propagation due to the transmission wire.
pulse
A logic signal that switches from one state to the other and back in a short period of time, and
remains in the original state most of the time. Usually used as clocks for logic devices.
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R
reflection
When a signal meets a sudden change in characteristic impedance, some of the signal is
reflected backward toward the driver. This is similar to the splash-back caused when a stream
of water passes through a mesh screen. For a signal routed on a PCB, multiple reflections
are possible, producing ringing and overshoot.
rise time
Time required for a logic signal to switch from its low state to its high state. Commonly
measured between the 20% and 80% voltage levels.
S
signal line
Any conductor used to transmit a logic signal from one circuit to another.
simultaneous switching noise (SSN)
Fluctuations in a device’s power and ground rails, typically caused by inductance in the paths
from a die to its power supply and ground.
stub
A branch of the main line of a signal net usually used to reach a load that is not on the direct
signal path.
T
thermal shift
A temperature-induced change in operating voltage caused by thermal drift. The junction
temperature difference between driver and receiver is responsible for thermal shift in logic
devices.
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transmission line
An electric conductor exhibiting series inductance and shunt capacitance distributed along its
length. A signal must charge up each chunk of inductance and capacitance before it is passed
along to the next chunk, thus reducing the propagation velocity.
U
undershoot
Voltage swing back into the midrange after the nominal steady state high or low level has
been crossed.
V
Vih
High state voltage threshold for a logic receiver.
Vil
Low state voltage threshold for a logic receiver.
W
waveform
Plot of voltage versus time for a given component pin.
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