JFET Application Note: Reset Transistor
Application Note 1003
Introduction
The Moxtek JFET chips include a secondary PNP “reset transistor” which
can be used to remove charge that accumulates on the JFET gate.
An example of this is in the front-end electronics of x-ray detectors.
Depending on the type of charge that accumulates on the gate (positive
or negative), a different reset mechanism is needed:
1. If negative charge accumulates on the gate (as is the case with x-ray
detectors that require negative biases, such as most silicon drift detectors
and Si(Li) detectors), the reset transistor needs to allow current to flow
onto the gate during the reset event.
2. If positive charge accumulates on the gate (as is the case with x-ray
detectors that require positive biases, such as most PIN diode detectors),
the reset transistor needs to allow current to flow away from the gate
during the reset event.
Drain
Gate
Source
Reset
Figure 1: Current Flows Onto Gate
During Reset Event
Configuration 1
In JFETs designed primarily for silicon drift detectors and Si(Li) detectors,
the reset transistor is configured as shown in Figure 1, with the base
shorted to the source, the collector shorted to the gate, and the emitter
connected to the reset pad. Since the gate-source JFET junction is
reverse-biased, so is the collector-base junction of the reset transistor.
When a negative bias is applied to the reset pad, both junctions are
reverse-biased and the transistor is in cutoff mode, with essentially no
current flowing between collector and emitter. When a positive bias is
applied to the reset pad, the emitter-base junction is forward-biased,
and the transistor is in active mode, with current flowing from emitter to
collector (from reset pad to JFET gate).
Substrate
Drain
Gate
Substrate
Source
Reset
Figure 2: Current Flows Away from
Gate During Reset Event
Configuration 2
In JFETs designed primarily for PIN diode detectors, the reset transistor
is configured as shown in Figure 2, with the emitter shorted to the gate,
the base shorted to the collector, and the collector connected to the
reset pad. With the base shorted to the collector, that junction can be
considered permanently reverse-biased (because the bias difference
is smaller than the forward voltage of the junction). When a positive
bias is applied to the reset pad, the emitter-base junction is reversebiased as well, and the transistor is in cutoff mode, with essentially no
current flowing between collector and emitter. When a negative bias
is applied to the reset pad, the emitter-base junction is forward-biased,
and the transistor is in active mode, with current flowing from emitter to
collector (from JFET gate to reset pad).
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