ICCAD91, Pages 2-5
A Cell-Replicating Approach to Mincut-Based Circuit Partitioning.
Chuck Kring and A. Richard Newton
Department of Electrical Engineering and Computer Sciences University of California,
Berkeley, Berkeley, CA. 94720
Abstract
An extension to the Fiduccia and Mattheyses mincut algorithm allows cells to be replicated in
both sides of the partition. This technique can substantially reduce the number of cut nets in a
partitioned network below what can be obtained without replication. The formulation of cell
gains is extended to model the effect of cell replication and the necessary modifications to the
algorithm are described
References
[1] Yen-Chenn Wei an Cheng-Kuan Cheng. Toward efficient hierarchical design by ratio cut partitioning. In
Proceedings of the International Conference on Computer-Aided Design, pages 298-301, November
1989.
[2] M. Beardslee, C. Kring, R. Murgai, H. Savoj, R. K. Brayton, and A. R. Newton. SLIP: A software environment for
system level interactive partitioning. In Proceedings of the International Conference on Computer-Aided
Design, pages 280-283, November 1989.
[3] C.M. Fiduccia and R. Mattheyses. A linear-time heuristic for improving network partitions. In Proceedings of
the 19 th Annual Design Automation Conference, pages 241-247, Jul 1982.
[4] B.W. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. The Bell System
Technical Journal, pages 291-307, Feb 1970.
[5] Balakrishnan Krishnamurthy. An improved min-cut algorithm for partitioning VLSI networks. IEEE
Transactions on Computers, c33(5):438-446, May 1984.
[6] Roy L. Russo, Peter H. Oden, and Peter K. Wolff. A heuristic procedure for the partitioning and mapping of
computer logic graphs. IEEE Transactions on Computers, c-20(12):1455-1462, Dec 1971.
ICCAD91, Pages 6-9
On Clustering for Minimum Delay/Area
Rajeev Murgai, Robert K. Brayton, Alberto Sangiovanni-Vincentelli
Department of EECS, University of California, Berkeley CA-94720
Abstract
We address the problem of clustering a circuit for minimizing its delay, subject to capacity
constraints on the clusters. We present an algorithm for combinational circuits and give sufficient
conditions under which it is optimum. In addition, we address the problem of minimizing the
number of clusters and nodes without increasing the maximum delay found by the algorithm.
Finally, we extend the clustering algorithm to minimize the clock cycle of a sequential
synchronous circuit.
References
[1] E. L. Lawler, K. N. Levitt, J. Turner, "Module Clustering to Minimize Delay in Digital Networks", IEEE
Transactions on Computers, Vol. C-18, No. 1, January 1969, pp 47-57.
[2] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: A Multiple-Level Logic
Optimization System", IEEE Transactions on CAD, November 1987.
[3] Herve Touati, "Delay Minimization in Technology Mapping", Ph.D. thesis, University of California, Berkeley,
1990.
[4] Rajeev Murgai, R. K. Brayton and A. Sangiovanni-Vincentelli, "On Clustering for Minimum Delay/Area",
Internal Report, University of California, Berkeley, 1991.
ICCAD91,Pages 10-13
Fast Spectral Methods for Ratio Cut Partitioning and Clustering
Lars Hagen and Andrew Kahng
UCLA Department of Computer Science, Los Angeles, CA 90024-1596
Abstract
The ratio cut partitioning objective function successfully embodies both the traditional
min-cut and equipartition goals of partitioning. Fiduccia-Mattheyses style ratio cut
heuristics have achieved cost savings averaging over 39% for circuit partitioning and
over 50% for hardware simulation applications [15]. In this paper, we (i) show a
theoretical correspondence between the optimal ratio cut partition cost and the second
smallest eigenvalue of a particular netlistderived matrix, and (ii) present fast Lanczosbased methods for computing heuristic ratio cuts from the eigenvector of this second
eigenvalue. Results are better than those of previous methods, e.g., by an average of
17% for the Primary MCNC benchmarks. An efficient clustering method, also based on
the second eigenvector, is very successful on the "difficult" input classes in the CAD
literature. The paper concludes with extensions and directions for future work.
References
[ 1 ] E. R. Barnes, "An Algorithm for Partitioning the Nodes of a Graph", SIAM J. Alg. Disc. Meth. 3(4) (1982),
pp. 541-550.
[2] R.B. Boppana, "Eigenvalues and Graph Bisection: An Average-Case Analysis", IEEE Symp. on Foundations
of Computer Science, 1987, pp. 280-285.
[3] T. N. Bui, S. Chaudhuri, F. T. Leighton and M. Sipser, "Graph Bisection Algorithms with Good Average Case
Behavior", Combinatorica 7(2) (1987), pp. 171-191.
[4] C.K. Cheng and T.C. Hu "Maximum Concurrent Flow and Minimum Ratio Cut", Technical Report CS88-141,
Univ. of California, San Diego, Dec. 1988.
[5] W.E. Donath, "Logic Partitioning", in Physical Design Automation of VLSI Systems, B. Preas and M.
Lorenzetti, eds., Benjamin f Cummings, 1988, pp. 65-86.
[6] W.E. Donath and A.J. Hoffman, "Lower Bounds for the Partitioning of Graphs", IBM J. Res. Dev. (1973),
pp. 420-425.
[7] C.M Fiduccia and R.M. Mattheyses, "A Linear Time Heuristic for Improving Network Partitions", ACM/IEEE
Design Automation Conf., 1982, pp. 175-181.
[8] J. Garbers, H. J. Promel and A. Steger, "Finding Clusters in VLSI Circuits" extended version of paper in
Proc. IEEE Intl. Conf. on Computer-Aided Design, 1990, pp. 520-523.
[9] G. Golub and C. Van Loan, Matrix Computations, Baltimore, Johns Hopkins University Press, 1983.
[10] L. Hagen and A. B. Kahng, "Fast Spectral Methods for Ratio Cut Partitioning and Clustering", UCLA CS
Dept. TR910012, April 1991.
[11] B.W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning of Electrical Circuits", Bell
System Technical J., Feb. 1970.
[12] T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout, Wiley-Teubner, 1990.
[13] A. Pothen, H. D. Simon and K. P. Liou, "Partitioning Sparse Matrices with Eigenvectors of Graphs", SIAM
J. Matrix Analysis and its Applications 11 (1990), pp. 430-452.
[14] G. Vijayan, "Partitioning Logic on Graph Structures to Minimize Routing Cost", IEEE Trans. on CAD
9(12) (1990), pp. 1326-1334.
[15] Y.C. Wei and C.K. Cheng, "Towards Efficient Hierarchical Designs by Ratio Cut Partitioning", IEEE Intl.
Conf. on Computer-Aided Design, 1989, pp. 298-301
ICCAD91, Pages 16-19
iMACSIM: A Program for Multi-level Analog Circuit Simulation
Jaidip Singh, Resve Saleh
Coordinated Science Lab, University of Illinois, Urbana, IL 61801
Abstract
This paper describes a new program called iMACSIM which allows multi-level, mixed-domain
simulation of analog integrated circuits. The program performs the simulation of different
subcircuits at the behavioral, functional and electrical levels concurrently. It also enables some
parts of the circuit to be simulated using discrete-time algorithms while other portions are
processed by continuoustime techniques. Simulations are presented to demonstrate the
functionality of the program.
References
[1] L.W. Nagel, "SPICE: A Computer Program to Simulate Semiconductor Circuits," Ph.D. Thesis, Univ. of California, Berkeley, 1975.
[2] R. Harr, A. Stanculescu, "Applications of VHDL to Circuit Design," Kluwer Academic Publishers, 1991.
[3] S.C. Fang,Y.P. Tsividis, O.Wing, "SWITCAP: A switched capacitor network analysis program," IEEE Circuits
Syst. Mag., vol. 5, no. 3, pp. 4-10, Sept. 1983.
[4] L.A. Williams, B.E. Boser, E.W.Y. Liu, B.A. Wooley, "MIDAS User Manual," Center for Integrated Systems,
Stanford University, 1989.
[5] R. Chadha, C. Visweswariah, C-F Chen, "M-cubed - A Multi-Level Mixed-Mode D/A Simulator," Proc. of ICCAD
1988, pp. 258-261.
[6] I. Getreu, "Behavioral Modeling of Analog Blocks Using the SABER Simulator," Proc. MWCAS, August 1989, pp.
977-980.
[7] PSPICE users manual, Micro Sim Corp., Jan. 1990.
[8] R.A. Saleh, A.R. Newton, "Mixed-Mode Simulation," Kluwer Academic Publishers, 1990.
[9] C.W. Ho, A.E. Ruehli, P.A. Brennan, "The Modified Nodal Approach to Network Analysis," IEEE Trans. Circuits and Systems, CAS-22, June 1975, pp. 504-509.
[10] Y-C Ju, V. Rao, R. Saleh, "Consistency Checking and Optimization of Macromodels," IEEE Trans. on CAD, Sept.
1991.
[11] M.P. Desai, and I.N. Hajj, "On the Convergence of Block Relaxation Methods for Circuit Simulation," IEEE
Trans. Circ. and Sys., vol. 36. no.7, pp. 948-958, July 1989.
[12] B.J. Hosticka, W. Brockherde, U. Kleine, R. Schweer, "Design of nonlinear analog switched-capacitor circuits
using building blocks," IEEE Trans. Circuits Systems., CAS-31, no.4, pp. 345-368.
[13] K. Suyama, "Analysis, Simulation, and Application of Linear and Nonlinear Switched-Capacitor and Mixed
Switched-Capacitor/Digital Networks," Ph.D. Thesis, Columbia University, 1989.
[14] C.T. Chen, "Linear System Theory and Design," Holt, Rinehart and Winston, 1984.
[15] J. Sherred, "A Phase-Locked Clock Generator for VLSI Applications," M. S. Thesis, Mass. Inst. of Tech, June
1988.
[16] C. Visweswariah, R. Chadha, C-F. Chen, "Model Development and Verification for High Level Analog Blocks,"
25th ACM/IEEE Design Automation Conference, pp. 376-382, June 1988.
ICCAD91, Pages 20-23
A Modified Envelope-Following Approach to Clocked Analog Circuit Simulation
Luis Miguel Silveira, Jacob White, Steven Leeb
Research Laboratory of Electronics, Dept. of Electrical Engineering and Computer Science, Massachusetts
Institute of Technology, Cambridge, MA 02139
Abstract
In this paper, a modified envelope following method for simulation of clocked analog
circuits is described. The modification makes the envelope-following algorithm more
e f ficient, as unnecessary numerical integration is avoided when computing the envelope
of "quasi-algebraic" components in the solution vector. An automatic method for
determining the quasialgebraic solution components is described, and experimental
results are given which demonstrate that this modified method reduces the number of
computed clock cycles needed to accurately determine the envelope.
References
[1] L. W. Nagel, "SPICE2: A computer program to simulate semiconductor circuits," Tech. Rep. ERL M520,
Electronics Research Laboratory Report, University of California, Berkeley, Berkeley, California, May 1975.
[2] J. Kassakian, "Simulating power electronic systems - a new approach," Proceedings of the IEEE, vol. 67,
October 1979.
[3] C. J. Hsiao, R. B. Ridley, H. Naitoh, and F. C. Lee, "Circuit-oriented discrete-time modeling and simulation for
switching converters," IEEE Power Electronics Specialists' Conf. Rec., 1987.
[4] S. C. Fang, et al, "Switcap: A switched-capacitor network analysis program - part 1: Basic features," IEEE
Circuits Syst. Mag., vol. 5, September 1983.
[5] L. Petzold, "An efficient numerical method for highly oscillatory ordinary differential equations," SIAM J.
Numer. Anal., vol. 18, June 1981.
[6] K. Kundert, J. White, and A. Sangiovanni-Vincentelli, "An envelope-following method for the efficient transient
simulation of switching power and filter circuits," in International Conference on Computer Aided-Design,
(Santa Clara, California), pp. 446-449, October 1988.
[7] J. White and S. Leeb, "An envelope-following approach to switching power converter simulation," IEEE Trans.
on Power Electronics, vol. 6, April 1991.
[8] T. Aprille and T. Trick, "Steady-state analysis of nonlinear circuits with periodic inputs," Proceedings of the
IEEE, January 1972.
[9] L. F. Casey and M. F. Schlecht, "A high frequency, low volume, point-of-load power supply for distributed
power systems," IEEE Power Electronics Specialists' Conf. Rec., 1987.
ICCAD91, Pages 24-27
An Accelerated Steady-State Method for Networks with Internally Controlled Switches
David Bedrosian and Jiri Vlach
Department of Electrical and Computer Engineering University of Waterloo Waterloo, Ontario,
Canada N2L 3G1
Abstract
A new accelerated computer oriented procedure, based on Newton's method, is presented to
determine the steady-state response of linear networks with internally and/or externally
controlled switches, The Jacobian matrix is computed concurrently with the d time-domain
response for all possible switching conditions, including changes in the switching times with the
initial conditions. The circuit response may be discontinuous and Dirac impulses are permitted at
the switching instants. Several examples show the speed and accuracy of the method.
References
1. K.S. Kundert et al, Steady-State Methods for Simulating Analog and Microwave Circuits, Kluwer Academic
Press, Boston, 1990.
2. AN Armanazi, "Steady-State Analysis of Piecewise-Linear Systems with Periodic Inputs," Proc. IEEE,
vol.61, pp. 789-790, June 1973.
3. E.A. El-Bidweihy and K. Al-Badwaihy, "SteadyState Analysis of Static Power Converters," IEEE Tr. Ind.
Appl., IA-18, pp. 405-410, July 1982.
4. R.C. Wong, "Accelerated Convergence to the Steady-State Solution of Closed-Loop Regulated SwitchingMode Systems as Obtained Through Simulation," PESC, pp. 682-692,1987.
5. Y. Kuroe et al, "Computation of Sensitivities with Respect to Conduction Time of Power Semiconductors and
Quick Determination of Steady State for Closed-Loop Power Electronic Systems," PESC, pp. 756-764,1988.
6. J. White and S.B. Leeb, "An Envelope-Following Approach to Switching Power Converter Simulation," IEEE
Tr. Power Elect., PE-6, pp. 303-307, April 1991.
7. D.G. Bedrosian, Analysis of Networks with Internally Controlled Switches, Ph.D. Dissertation, University of
Waterloo, Ontario, 1991.
8. D.G. Bedrosian and J. Vlach, "Time-Domain Analysis of Networks with Internally Controlled Switches,"
ISCAS,1991.
9. J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design, Van Nostrand Reinhold, New
York, 1983.
10. A. Opal and J. Vlach, "Consistent Initial Conditions of Linear Switched Networks," IEEE Tr. Circ. Syst.,
CAS-37, pp. 364-372, March 1990.
11. A.M. Luciano and A.G.M. Strollo, "A Fast TimeDomain Algorithm for the Simulation of Switching Power
Converters," IEEE Tr. Power Elect., PE-5, pp. 363-370, July 1990.
ICCAD91, Pages 30-33
Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths
James J. Kim*, Fadi J. Kurdahi*, and Nohbyung Park**
*Department of Electrical & Computer Engineering, University of California, Irvine, CA 92717
**Samsung Electronics, Seoul, Korea
Abstract
We address the problem of control synthesis for pipelined data paths. Two basic control schemes
are possible: data-stationary and time-stationary. In this work, we consider the latter approach.
We developed an approach to automatically synthesize time-stationary controllers for pipelined
data paths produced by high level synthesis tools. A highly optimized FSM controller is
implemented using either PLAs or Standard Cells. We compared our approach to published work
on FSM generation and optimization and the results indicate large savings in total controller
area.
References
[1] N. Park and A. Parker. Sehwa: a software package for synthesis of pipelines from behavioral specifications.
IEEE Trans. CAD, 7(3):356-370, March 1988.
[2] N. Park and F. Kurdahi. Module assignment and interconnect sharing in register-transfer synthesis of pipelined
data paths. In Proc. ICCAD-89,1989.
[3] P. M. Kogge. The Architecture of Pipelined Computers. McGraw-Hill, New York, N.Y., 1981.
[4] P. Paulin. Horizontal partitioning of PLA-based finite state machine. In Proc. 26th DAC, 1989.
[5] S. Hayati and A. Parker. Automatic production of controller specifications from control and timing behavioral
descriptions. In Proc. 26th DAC, 1989.
[6] C.Tseng et al. Bridge: a versatile behavioral synthesis system. In Proc. 25th DAC, 1988.
[7] A. Nagle, R. Cloutier, and A. Parker. Synthesis of hardware for the control of digital systems. IEEE Trans.
CAD, CAD1(4):201-212,1982.
[8] G. Goossens, J. Vandewalle, and H. De Man. Loop optimization in register-transfer scheduling for DSP systems.
In Proc. 26th DAC,1989.
[9] R. Potasman, J. Lis, A. Nicolau, and D. Gajski. Percolation based synthesis. In Proc. 27th DAC,1990.
[10] T. Villa and A. Sangiovanni-Vincentelli. NOVA: state assignment of finite state machines for optimal two-level
logic implementations. In Proc. 26th DAC, 1989.
[11] R. Brayton et al. Logic Minimization Algorithms for VLSI synthesis. Kluwer, 1985.
[12] G. De Micheli and M. Santomauro. Smile: a computer program for partitioning of programmed logic arrays.
Computer Aided Design, 89-97, March 1983.
[13] J. Kim and F. Kurdahi. Synthesis Algorithms for the PLAbased Time-stationary Control of the Pipelined Data
Path. Tech. Rep., ECE Dept., UC Irvine, 1990.
[14] R. Brayton et al. Multiple level logic optimization system. In Proc.ICCAD-86,1986.
[15] T. Chang. Application of Vertical-Horizontal Partitioning Algorithm for PLA-based Finite State Machine.
Master's thesis, ECE Dept., UC Irvine, 1990.
[16] L Compilers Users Guide. Silicon Compiler Systems, 1989.
[17] F. Kurdahi and C. Ramachandran. LAST: a Layout Area and Shape function esTimator for high level
applications. In Proc. EDAC-91, 1991.
ICCAD91, Pages 34-37
Layout-Area Models for High-Level Synthesis
Allen C-H Wu, Viraphol Chaiyakul, Daniel D. Gajski
Department of Information and Computer Science, University of California, Irvine, CA, 92717
Abstract
Traditionally, the number and size of functional units, registers and interconnect units,
are used as quality measures in high level synthesis. However, these design quality
measures may not reflect the real physical design. To establish such quality measures, we
propose a simple layout area model for two commonly used datapath and control layout
architectures. The results show that this simple model predicts on selected benchmarks,
the final layout accurately within 10%. The results also show that traditional cost functions are not good indicators for optimization in high level synthesis.
References
[1] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: A Multiple-Level Logic
Optimization System", " IEEE Transactions on CAD, November 1987.
[2] S. Devadas et al, "MUSTANG: State Assignment for Finite State Machines for Multi-Level Logic
Implementations," Proc. ICCAD pp. 16-19,1987.
[3] C. M. Fiduccia and R. M. Mattheyses, "A Linear-Time Heuristic for Improving Network Partitions," Proc. 19th
DAC, pp. 175-181,1982.
[4] K. H. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," Bell System Technical
Journal, vol. 49, no. 2, pp. 291-307, February, 1970.
[5] Allen C-H Wu, Viraphol Chaiyakul, and D. D. Gajski "Layout-Area Models for High-Level Synthesis," Tech.
Report. No. 91-31, ICS Dept., UC Irvine, 1991.
[6] "Data Path Library," VLSI Technology, INC., 1988.
ICCAD91, Pages 38-41
Efficient Microcode Arrangement and Controller Synthesis for Application Specific
Integrated Circuits
Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu
Department of Computer Science, University of California, Riverside, CA 92521
Abstract
In this paper, we present a controller synthesizer for application specific multifunction-unit
processors. We first describe the data path, control path and timing scheme of our design. We
then discuss the optimization problems for this architecture including the translation of a
controller independent schedule into a microprogram to fit our timing scheme and the address
assignment of micro-words. We verify our designs using a function simulator and a timing
simulator. The synthesized results are proved to be correct by simulation and a design with 22 ns
for each phase, which corresponds to 23 MHz, has been obtained.
References
[1] D. D. Gajski and D. E. Thomas(editors), Silicon Compilation, Addison-Wesley, 1988.
[2] M. C. McFarland, A.C. Parker and R. Camposano, '"The High-Level Synthesis of Digital System," Proceedings
of the IEEE, pp. 301-318, Feb. 1990.
[3] D. C. Ku and G. D. Micheli, "Optimal Synthesis of Control Logic from Behavioral Specifications," Journal of
VLSI Integration, pp. 271-298, Feb. 1991.
[4] Cheng-Tsung Hwang, J. H. Lee, Y. C. Hsu, "A Formal Approach to the Scheduling Problem in High Level Synthesis," IEEE Transactions on CAD, April, 1991.
[5] Fur-Shing Tsai and Y. C. Hsu, "Data Path Construction and Refinement," ICCAD-90, pp. 308-311, 1990.
[6] Manolis G.H. Katevenis, Reduced Instruction Set Computer Architectures for VLSI.
[7] J. Zegers, P. Six, J.Rabaey and H. De Man., "CGE: Automatic Generation of Controllers in the CATHEDRAL-II
Silicon Compiler," EDAC-90, pp. 617-621,1990.
[8] R. Amann and U. G. Baitinger, "New Sate Assignment Algorithms For Finite State Machines Using Counters
and Multiple-PLA/ROM Structure," ICCAD-87, pp. 20-23, 1987.
[9] L. Gerbaux and G. Saucier, "Optimized Synthesis of Large Controllers on a ROM Based Architecture," High
level Synthesis Workshop 91, pp.134-140,1991.
ICCAD91, Pages 44-47
A New Performance Driven Placement Algorithm
Tong Gao, P. M. Vaidya, C. L. Liu
Department of Computer Science, University of Illinois at Urbana-Champaign
Abstract
In this paper, we present a new performance driven placement algorithm. We first use
a convex programming algorithm to compute a set of upper-bounds on the net wire
lengths. We then use a modified min-cut algorithm to generate a placement with the
objective of minimizing the number of nets the wire lengths of which exceed their
corresponding upper bounds. We then address the situation in which the modified
min-cut algorithm fails to generate a placement that satisfies the timing requirements.
We employ an iterative approach to modify the set of upper-bounds making use of
information from previous placements.
References
[1] R.. B. Hitchcock, G. L. Smith, and D. D. Cheng, "Timing Analysis of Computer Hardware," IBM Journal of
Research and Development, 1982, vol. 28, no. 1, pp. 100-105.
[2] M. Burstein and M. N. Youssef, "Timing Influenced Layout Design, Proc. 22th DAC, 1985, pp. 124-130.
[3] W. E. Donath et. al., "Timing Driven Placement Using Complete Path Delays," Proc. 27th DAC, 1990, pp.
84-89.
[4] M. A. B. Jackson and E. S. Kuh, "Performance-Driven Placement of Cell Based IC's," Proc. 26th DAC, 1989,
pp. 370-375.
[5] P. S. Hauge, R. Nair, and E. J. Yoffa, "Circuit Placement for Predictable Performance, Proc. ICCAD, 1987, pp.
88-91.
[6] A. E. Dunlop et. al., "Chip Layout Optimization Using Critical Path Weighting,” Proc. 21st DAC, 1984, pp.
133-138.
[7] M. Marek-Sadowska and S. P. Lin, "Timing Driven Placement," Proc. ICCAD, 1989, pp. 94-97.
[8] Y. Ogawa et. al., "Efficient Placement Algorithms Optimizing Delay for High-Speed ECL Masterslice LSI's",
Proc 23rd DAC,1988, pp. 404-410.
[9] W. M. Dai et. at., "BEAR: A New Building-Block Layout System," Proc. ICCAD, 1987, pp. 34-38.
[10] S. Teig, R. L. Smith, and J. Seaton, "Timing Driven Layout of Cell-Based IC's," VLSI System's Design, pp
83-73, May 1986.
[11] M. Terai, K. Takahashi, and K. Sato, "A New Min-Cut Placement Algorithm for Timing Assurance Layout
Design Meeting Net Length Constraint," Proc. 27th DAC, 1990, pp. 98-102.
[12] P. M. Vaidya, A New Algorithm for Minimizing Convex Functions Over Convex Sets," Proc. 30th Annual
IEEE Symposium on Foundations of Computer Science, 1989, pp. 332-337.
[13] C. M. Fiduccia and R. R. Mattheyses, "A Linear-Time Heuristic for Improving Network Partitions," Proc.
19th DAC, 1982, pp. 175-181.
ICCAD91, Pages 48-51
RITUAL : A Performance Driven Placement Algorithm for Small Cell Ics
Arvind Srinivasan, Kamal Chaudhary, E. S. Kuh
Electronics Research Laboratory, Dept. of EELS, University of California, Berkeley.
Abstract
In this paper we describe an efficient algorithm for obtaining a placement of cell-based ICs
subject to performance constraints. Using sophisticated mathematical techniques, we are able
to solve large problems quickly and effectively. The algorithm is very simple and elegant,
making it easy to implement. In addition, it yields good results as we show on a set of real
examples. On the average, we are able to make 25% improvement in the wire delay of these
examples compared to TimberWolf S.6 with a small impact on the chip area. The acronym
RITUAL represents the key idea of our technique: Residual Iterative Technique for Updating
All Lagrange multipliers.
References
[1] M. A. B. Jackson and E. S. Kuh., Performance-driven placement of cell-based ic's., IEEE Proceedings of the
26th Design Automation Conference, pages 370--375,1989.
[2] R. S. Tsay, E. S. Kuh, and C. P. Hsu, Proud: A sea-of-gates placement algorithm, IEEE Design and Test of
Computers, pages 318--323, December 1988.
[311. Lin and D. Du , Performance-driven constructive placement, IEEE Proceedings of the 27th Design
Automation Conference, pages 103-105,1990.
[4] Shapiro, Jeremy F., Mathematical programming: structures and algorithms, New York: Wiley, c1979.
[5] Luenberger, David G., Introduction to linear and nonlinear programming, Reading, Mass., Addison-Wesley
Pub. Co. [1973].
[6] J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich, GORDIAN:VLSI placement by quadratic
programming and slicing optimization, IEEE Trans. on CAD, Volume 10, No. 3, pages 356-365,1991.
[7] A. Srinivasan, K. Chaudhary and E.S. Kuh, RITUAL: An Algorithm for Performance-Driven Placement, UCB
ERL Technical Memo M91/47, Electronics Research Laboratory, University of California, Berkeley, CA 94720.
[8] Octools, Release notes V. 5.0, EECS Industrial Liaison Program, University of California, Berkeley, CA
94720.
[9] C. Sechen and K. W. Lee, An improved simulated annealing algorithm for row-based placement, Proc.
ICCAD, pp. 478-481, 1987.
ICCAD91, Pages 52-55
Wafer Packing for Full Mask Exposure Fabrication
Ching-Ting Wu, Andrew Lim, David Du
Dept. of Computer Science, University of Minnesota, Minneapolis, Mn 55455
Abstract
Advancements in fabrication technology result in the decrease of the unit length (feature
size) of designs from microns to sub-microns and the increase of the wafer diameter. As a
result, more chips can be made from a single wafer. Increasing demands of manufacturing
ASIC chips in small quantities made traditional ways of implementing a single design on a
wafer very cost ineffective. In this paper, we formulate and classify the various models of the
Wafer Packing Problem for Full Mask Exposure technique. Since wafer packing problem is
shown to be NP-hard [1], we propose a good heuristic for it. Our experiments, on real test
data, indicate that our heuristic is very effective as it provides considerable cost reduction
when compared with the traditional way of producing chips.
References
[1] C.-T. Wu, Several Optimization problems for CAD in VLSI. PhD thesis, University of Minnesota, 1991.
In Preparation.
[2] S. Muroga, VLSI system design. Wiley, 1982.
[3] C. Mead and L. Conway, Introduction to VLSI systems. Addison-Wesley, 1980.
[4] D. Du, I. Lin, and K. Chang, "On Wafer Packing Problem," Tech. Rep. TR-30, University of Minnesota,
Computer Science Department, 1989.
[5] B. Bengtsson, "Packing Retangular Pieces - A Heuristic Approach," The Computer Journal, vol. 25, no.
3, 1982.
ICCAD91, Pages 56-59
A Floorplanning Algorithm Using
Rectangular Voronoi Diagram and Force-Directed Block Shaping
Sang-Gil Choi and Chong-Min Kyung
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, P. 0. Box 150,
Cheongryang, Seoul, Korea
Abstract
We propose a new floorplanning algorithm which handles a mixture of fixed-shaped and
variable-shaped blocks in a chip having a chip aspect ratio within a given range. This
algorithm consists of two stages. In the first stage, overlapped blocks in the initial
placement obtained using FDR(Force Directed Relaxation) are spread out uniformly over
the whole chip area using the so-called Ratioed Rectangular Voronoi diagram such that
each block finds enough space without significant overlap with its neighboring blocks. In
the second stage, each block is reshaped or moved by the independent move of each block
edge according to the attractive force and repulsive force exerted on it due to the overlap
and the dead space, respectively. Experimental results were obtained on ami33
benchmark circuit with varying conditions on the aspect ratio of blocks and chip.
Significant improvement of the chip utilization factor has been obtained, compared to the
earlier works.
References
[1] D. F. Wong and C. L. Liu, "A New Algorithm for Floorplanning Design " Proc. 23th Design Automation
Conference, pp. 101-107,1986.
[2] David P. La Potin and Stephen W. Director "Mason A Global Floorplanning Approach for VLSI Design," IEEE
Trans. on CAD, Vol. CAD-5, No. 4, pp. 477489, Oct. 1986.
[3] Thomas Lengauer and Rolf Muller "A Robust Framework for Hierarchical Floorplanning with integrated Global
Wiring,” Proc. Internationa l Conference on Computer Aide Design, pp. 148-151,1990.
[4] Badri Lokanathan and Edwin Kinnen "Performance Optimized Floorplanning by Graph Planarization " Proc.
26th Design Automation Conference, pp. 116-121, 1989.
[5] Kazuhiro Ueda, Hitoshi Kitazawa and Ikuo Harada "CHAMP : Chip Floor Plan for Hierarchical VLSI Layout
Design " IEEE Trans. on CAD, Vol.
CAD-4, No. 1, pp. 12-22, Jan. 1985.
[6] Yu-Chin Hsu and William J. Kubitz, "A Procedure for Chip Floorplanning,” Proc. ISCAS, pp. 568-571, 1987.
[7] Suphachai Sutanthavibul, Eugene Shragowitz and J. Ben Rosen, "An Analytical Approach to Floorplan Design
and Optimization " Proc. 27th Design Automation Conference, pp. 187-192, 1990.
[8] G. Vijayan and R. S. Tsay, “Floorplanning by TopologicaI Constraint Reducton,” Proc., International
Conference on Computer Aided Design, pp. 106-109, 1990.
[9] F.P. Preparata and M.I. Shamos, Computational Geometry : An Introduction, Springer-Verlag, New
York, 1985.
ICCAD91, Pages 62-65
An Impulse-Response Based Linear Time-Complexity Algorithm for Lossy
Interconnect Simulation
Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley
Abstract
In this paper, a linear time-complexity algorithm for lossy transmission line simulation within
arbitrary nonlinear circuits is presented. The method operates by storing information about the
state of the line at dynamically selected internal points and using an analytical formulation based
on impulse responses to predict the line's future behaviour accurately. Previous approaches using
impulse responses (based on time-domain convolution) possess quadratic time-complexity,
which can lead to long computation times for simulations with many time-points. In the
proposed method, integration over space with fixed limits replaces time-domain convolution,
eliminating the quadratic time-complexity. The method does not require rational or other
approximations of transfer -functions to achieve linear time-complexity nor does it increase the
size of the simulator's matrix by more than 2 for each transmission line. Experimental results on
industrial circuits indicate that for equivalent or superior accuracy, the state-based method can be
faster for simulations of one or more clock or data pulses, with speedups of more than 10 and 50
over the convolution and lumped-RLC methods for the longer simulations.
References
[1] C.A. Neugebauer et. al. High Performance Interconnections between VLSI Chips. Solid State Tech., June 1988.
[2] J.E. Schutt-Aine and R. Mittra. Analysis of Pulse Propagation in Coupled Transmission Lines. IEEE Trans.
Ckts. Sys., CAS-32(12), December 1985.
[3] H.W. Dommel. Digital Computer Solution of Electromagnetic Transients in Single and Multiphase Networks.
IEEE Trans. Power App. Sys., PAS-88(4):388, April 1969.
[4] A.J. Gruodis. Transient Analysis of Uniform Resistive Transmission Lines in a Homogeneous Medium. IBM J.
Res. Dev., 23(6), November 1979.
[5] Omar Wing. Time-Domain Models of VLSI Interconnects. Talk at U.C. Berkeley, Apr. 1991.
[6] R. Wang and O. Wing. Analysis of VLSI Multiconductor Systems by Bi-Level Waveform Relaxation. In Proc.
ICCAD 90, pages 166-169, 1990.
[7] A.R. Djordjevic et. al. Analysis of Lossy Transmission Lines with Arbitrary Nonlinear Terminal Networks.
IEEE Trans. Microwave Th. Tech., MTT-34(6):660, June 1986.
[8] J.E. Schutt-Aine and R. Mittra. Nonlinear Transient Analysis of Coupled Transmission Lines. IEEE Trans. Ckts.
Sys., 36(7), July 1989.
[9] J.S. Roychowdhury and D.O. Pederson. Efficient Transient Simulation of Lossy Interconnect. Proc. 28th
ACM/IEEE Design Automation Conference, June 1721 1991, San Francisco.
[10] A. Deutsch et. al. High-speed signal propagation on lossy transmission lines. IBM J. Res. Dev., 34(4): 601-615,
July 1990.
[11] J.S. Roychowdhury and A. R. Newton. Algorithms for the Transient Simulation of Lossy Interconnect. In
preparation.
[12] J.S. Roychowdhury, A.R. Newton, and D.O. Pederson. State-Based Simulation of Frequency-Varying Lossy
Line Models. To appear.
ICCAD91, Pages 66-69
Delay and Crosstalk Simulation of High-Speed
VLSI Interconnects with Nonlinear Terminations
Dong H. Xie and Michel Nakhla
Department of Electronics, Carleton University Ottawa, Ontario, Canada K1S 5B6
Abstract
A method is presented for analysis of VLSI interconnects which contain both lossy coupled
transmission lines and nonlinear components. An equivalent time domain macromodel is
derived for the lossy coupled transmission line. The macromodel takes the form of a set of
ordinary differential equations. The method takes full advantage of the Asymptotic Waveform
Evaluation technique which offers two to three orders of magnitude speedup relative to other
methods with comparable accuracy.
References
[1] R. Sainati and T. Moravec, "Estimating high speed interconnect performance," IEEE Trans. Circuits Syst., Vol.
CAS-36, pp.533-541, Apr. 1989.
[2] H. Hasegawa and S. Seki, "Analysis of interconnection delay on very high-speed LSI/VLSI chips using an MIS
microstrip line model," IEEE Trans. Electron Devices, Vol. ED-31, pp. 1954-1960, Dec. 1984.
[3] M. Nakhla, " Analysis of pulse propagation on highspeed VLSI chips," IEEE Journal of Solid-State Circuits,
pp.490-494, Apr. 1990.
[4] M. Cases and D. Quinn, "Transient response of uniformly distributed RLC transmission lines," IEEE Trans.
Circuits Syst., Vol. CAS-27, pp. 200-207, Mar. 1980.
[5] S. S. Gao, A.Y. Yang and S. M. Kang, "Modelling and simulation of interconnection delays and crosstalks in
high-speed integrated circuits," IEEE Trans. Circuits Syst., Vol. CAS-37, pp. l-9, Jan. 1990.
[6] J. E. Schutt-Aine and R. Mitra, "Nonlinear transient analysis of coupled transmission lines," IEEE Trans.
Circuits Syst., Vol. CAS-36, pp. 959-967, Jul. 1989.
[7] A. J. Groudis, "Transient analysis of uniform resistive transmission lines in a homogeneous medium," IBM J.
Res. Develop., Vol. 23, pp. 675-681, Nov. 1979.
[8] A. J. Groudis, and C. S. Chang, "Coupled lossy transmission line characterization and simulation," IBM J. Res.
Develop., Vol.25, pp. 25-41, Jan. 1981.
[9] A. R. Djordjevic, T. K. Sarkar, and R. F. Harrington, "Time-domain response of multiconductor transmission
lines," Proceedings IEEE, Vol. 75, pp. 743-764, June 1987.
[10] L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. on Computer-Aided Design, Vol. 9, pp. 352-366, April 1990.
[11] L. T. Pillage, Asymptotic Evaluation for Timing Analysis, Carnegie-Mellon University, Research Report No.
CMUCAD-89-34.
[12] T. Tang and M. Nakhla, "Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation
technique," in Proc. IEEE ICCAD-90, pp. 542-545, Nov. 1990.
[13] T.Tang and M. Nakhla, "Analysis of high-speed VLSI interconnects," accepted for publication in the IEEE
Trans. on Computer-Aided Design.
[14] C. W. Ho, A. E. Ruehli and P. A. Brennan, "The modified nodal approach to network analysis," IEEE Trans.
Circuits Syst., Vol. CAS-22, pp. 504-509, June 1975.
[15] R. Griffith and M. Nakhla, "Time-domain analysis of lossy coupled transmission lines," IEEE Trans. Microwave Theory and Techniques, Vol. MTT- 38, pp. 1480-1487, Oct. 1990.
ICCAD91, Pages 70-73
Retarded Models for PC Board Interconnects - or How the Speed
of Light Affects Your SPICE Circuit Simulation
Hansruedi Heeb and Albert Ruehli
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
E-Mail: heeb@watson.ibm.com
Abstract
The electrical modeling of the interconnects for computer chips and packages is a topic
which is receiving much attention at present. The three dimensional modeling of such
structures has been successfully accomplished using the partial element equivalent circuit
(PEEC) approach. In this paper we show that retardation effects, due to the finite speed of
electromagnetic interactions, play a significant role for PC-board interconnects. We
demonstrate that in some cases errors of more than an order o f magnitude result in some frequency components when retardation is neglected. We introduce extensions to a circuit
simulator that allow us to do retarded circuit simulation. Comparisons with analytical
equations, the method of moments and with measurements show good agreement.
References
[1] A. E. Ruehli, "Equivalent circuit models for three dimensional multiconductor systems," IEEE Trans. on
MTT, vol. 22, pp. 216-221, Mar. 1974.
[2] L. W. Nagel, "SPICE2: A computer program to simulate semiconductor circuits," Electr. Res. Lab. Report ERL
M520, UC Berkeley, May 1975.
[3] W. T. Weeks, A. J. Jimenez, G. W. Mahoney, D. Mehta, H. Quasemzadeh and T. R. Scott, "Algorithms for
ASTAP - a network analysis program," IEEE Trans. on Circ. Th., vol. CT-20, pp. 628-634, Nov. 1973.
[4] H. Heeb, A. Ruehli, J. Janak and S. Daijavad, "Simulating electromagnetic radiation of printed circuit boards," in
ICCAD, pp. 392-395,1990.
[5] R. F. Harrington, Field Computation by Moment Methods. Macmillan, 1968.
[6] H. Heeb and A. Ruehli, "Approximate timedomain models of three-dimensional interconnects," in ICCD, pp.
201-205,1990.
[7] B. J. Rubin and S. Daijavad, "Radiation and scattering from structures involving finite-size dielectric regions," in
IEEE APS Int. Symp., 1990.
ICCAD91, Pages 74-77
Evaluating RC-Interconnect Using Moment-Matching Approximations
Nanda Gopal, Dean P. Neikirk and Lawrence T. Pillage
Department of Electrical & Computer Engineering, The University of Texas at Austin, Austin, Texas 78712
Abstract
Moment-matching approximations for linear(ized) circuit analysis, particularly
Asymptotic Waveform Evaluation (AWE), can efficiently evaluate the delays and the
loading effects due to resistance and capacitance of interconnect in terms of large,
lumped, RC-circuit models. This paper describes a relation for specifying the
"optimal" number of lumped RC sections needed to approximate a distributed RC
element for an estimated digital-signal bandwidth. The bandwidth approximation also
aids in determining the order of the AWE approximation for the driving-point and
transfer function models. Since moving to arbitrarily high orders of approximation to
meet the bandwidth requirements is complicated by moment-matching instability
problems, a constrained mapping from moments to dominant time constants is used
which guarantees stability for RC interconnect models.
References
[1] G. A. Baker, Jr., "Essentials of Pade Approximants," Academic Press, 1975.
[2] R. F. Brown, "Model stability in use of moments to estimate pulse transfer functions," Electron. Lett., 7, 1971.
[3] M. S. Ghausi and J. J. Kelly, "Introduction to Distributed-Parameter Networks," R. E. Krieger Pub. Co., 1968.
[4] N. Gopal and L. T. Pillage, "Evaluation of on-chip RC interconnect using moment-matching approximations,"
Tech. Rep. UT-CERC-TR-LTP-91-02, Comp. Emg. Res. Ctr., U. Texas Austin), Apr 1991.
[5] N. Gopal, C. Ratzlaff and
. T. Pillage, "Constrained approximation of dominant time- constant (s) in RCcircuit delay models," Proc. 18th IMACS World Congress Comp. Appl. Math, July 1991.
[6] X. Huang, "Pade approximation of linear(ized) circuit responses," PhD Diss., Carnegie Mellon Univ., Nov 1990.
[7] S. Kumashiro, R. Rohrer and A. Strojwas, "A new efficient method for the transient simulation of 3D
interconnect structures," IEDM Tech. Dig., 1990.
[8] D. D. Ling and A. E. Ruehli, "Interconnect Modeling: Lumped Circuit Element Models," in Ckt. Anal. Sim.
Des., v.2, Elsevier Science Pub. B. V., 1987.
[9] S. P. McCormick, "Modeling and simulation of VLSI interconnections with moments," PhD Diss., Mass. Inst.
Tech., Jun 1989.
[10] P. R. O'Brien and T. L. Savarino, "Modeling the driving-point characteristic of resistive interconnect for
accurate delay estimation," Proc. Int'l. Conf. Computer-Aided Des., Nov 1989.
[11] L. T. Pillage and R. A. Rohrer, "Asymptotic Waveform Evaluation for timing analysis," IEEE Trans.
Computer-Aided Des., 9, 1990.
[12] C. L. Ratzlaff, N. Gopal and L. T. Pillage, "RICE: Rapid Interconnect Circuit Evaluator," Proc. 28th
ACM/IEEE Des. Auto. Conf., Jun 1991.
[13] T. Sakurai, "Approximation of wiring delay in MOSFET LSI," IEEE J. Solid-State Ckt., 18(4), 1983.
ICCAD91, Pages 80-83
The Effects of False Paths in High-Level Synthesis
Reinaldo A. Bergamaschi
IBM Research Division - T. J. Watson Research Center Yorktown Heights, NY 10598
Abstract
This paper discusses the effects of false paths and their consequences in scheduling and
allocation during high-level synthesis. False paths through the control-flow graph may occur due
to sequences of conditional operations. The detection of false paths during scheduling may result
in smaller number of states, improved operator sharing and smaller control logic. An heuristic
algorithm is presented for the detection and elimination of false paths during path-based
scheduling. Results for benchmark examples are presented. For the designs which contained
false paths, the percentage of false paths varied from 5% to 83%. A reduction of 15% in the final
cell count for one benchmark was obtained by eliminating false paths.
References
[1] P. G. Paulin and J. P. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASICs", IEEE
Transactions on Computer Aided Design, vol. CAD-8, no. 6, pp. 661-679, June 1989.
[2] F. J. Kurdahi and A. C. Parker, "REAL: a Program for Register Allocation", in Proceedings of the 24th
ACMIIEEE Design Automation Conference, ACM/IEEE, June 1987.
[3] R. A. Bergamaschi, R. Camposano, and M. Payer, "Data Path Synthesis Using Path Analysis", in Proceedings of
the 28th ACM/IEEE Design Automation Conference, ACM/ IEEE, June 1991.
[4] R. Camposano, R. A. Bergamaschi, C. Haynes, M. Payer and S-M Wu, "The IBM High-Level Synthesis
System", in R. Camposano and W. Wolf, editors, High-Level VLSI Synthesis, Kluwer Academic Publishers, 1991.
[5] R. Camposano, "Path-Based Scheduling for Synthesis", IEEE Transactions on Computer Aided Design, vol.
CAD-10, no. l, pp. 85-93, January 1991.
[6] P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Kluwer
Academic Publishers, 1991.
[7] R. A. Bergamaschi, R. Camposano, and M. Payer, "Area and Performance Optimizations in Path-Based
Scheduling", in Proceedings of the European Conference on Design Automation, The Netherlands, February 1991.
[8] "Benchmarks for the Fifth International Workshop on HighLevel Synthesis", 1991. Available through EMail at
HLSW @ics.uci.edu (InterNet).
[9] J. Darringer, D. Brand, J. V. Gerbi, W. Joyner, and L. Trevillyan, "LSS: A system for production logic
synthesis", IBM Journal of Research and Development, vol. 28, September 1984.
ICCAD91, Pages 84-87
A Scheduling Algorithm For Conditional Resource Sharing
Taewhan Kim, Jane W.S. Liu, C. L. Liu
Department of Computer Science, University of Illinois at Urbana-Champaign
Abstract
A new scheduling algorithm for dataflow graphs with nested conditional branches is
presented. The algorithm employs a bottom-up approach to transform a data flow graph with
conditional branches into an "equivalent" one that has no conditional branches. A schedule is
then obtained for the latter, using a conventional scheduling algorithm, from which a
schedule for the former is derived. Experimental results demonstrated that such an approach
was quite effective.
References
[1] C.-J. Tseng, R. W. Wei, S. G. Rothweiler, M. Tong and A. K. Boe, "Bridge: A Versatile Behavioral Synthesis
System," Proc. 25th DAC., pp.415-420, 1988.
[2] K. Wakabayashi and T. Yoshimura, "A Resource Sharing Control Synthesis Method for Conditional Branches,"
Proc. ICCAD'89, pp.62-65, 1989.
[3] R. Camposano, "Path-Based Scheduling for Synthesis," IEEE Trans. CAD, vol.10, no.1, pp.85-93, Jan. 1991.
[4] K. S. Hwang, et al., "Constrained Conditional Resource Sharing in Pipeline Synthesis", ICCAD'88, pp.52-55, 1988.
[5] A. C. Parker, J. Pizarro and M. J. Mlinar, "MAHA:A Program for Datapath Synthesis," Proc. 23rd DAC., pp.461466, 1986.
[6] P. G. Paulin and J. P. Knignt, "Force-Directed Scheduling for the Behavioral Synthesis of ASIC's", IEEE Trans.
CAD, vol.8, no.6, pp.661-679, June, 1989.
ICCAD91, Pages 88-91
Optimizing Resource Utilization using Transformations
Miodrag Potkonjak, Jan Rabaey
Department of EECS University of California, Berkeley
ABSTRACT
The goal of the high level synthesis for real time applications is to minimize the implementation
cost, while still satisfying all timing constraints. We present how a combination of two transformations, being retiming and associativity, can help to further this goal. Since the minimization
problem, associated with those transformations, is NP complete, a new fast, globally optimal iterative improvement probabilistic algorithm has been developed. The effectiveness of the proposed
algorithms and the transformations will be demonstrated using standard benchmark examples, with
the aid of statistical analysis and through a comparison with estimated minimal bounds.
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[2] M.R. Garey, D.S. Johnson, "Computers and Intractability: A Guide to the Theory of NP-Completeness",
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[4] B.S. Haroun, M.I. Elmasry: "Architectural Synthesis for DSP Silicon Compilers", IEEE Trans. on CAD, Vol.
8, No. 4, pp. 431-447.
[5] R Hartley, A. Casavant: "Tree-height Minimization in Pipelined Architectures", IEEE CAD, pp.112-115,
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1988.
[9] C.E. Leiserson, et.al., "Optimizing synchronous circuits by retiming", Proceedings of Third Conference on
VLSI, pp. 23-36,1983.
[10] S. Malik, et.al: "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational
Technique", IEEE Trans. on CAD, Vol. 10, No. l, pp. 74-84,1991.
[11] M.C.McFarland, et.al: "The High-Level Synthesis of Digital Systems"", Proceedings of the IEEE, Vol. 78,
No. 2, pp. 301-317., 1990.
[12] D. Messerschmitt, "Breaking The Recursive Bottleneck", in Performance Limits in Communication Theory
and Practice, 1988.
[13] G.L.Miller, et.al: "Efficient Parallel Evaluation of Straight-Line Code and Arithmetic Circuits," SIAM
Journal on Computing, Vol. 17, No 4, pp. 687-695,1988.
[14] N.Park, A.C.Parker: "Sehwa: A Software Package for Synthesis of Pipelines from Behavioral
Specifications", IEEE Transaction on CAD for IC, Vol 7, No. 3, pp. 356-370,1988.
[15] M. Potkonjak and J. Rabaey, "Retiming for Scheduling", VLSI Signal Processing Workshop, pp. 23-32, San
Diego, Nov. 1990.
[16] M. Potkonjak, "High Level Synthesis: Resource Utilization Approach", Ph.D. Thesis, University of
California, Berkeley, 1991.
[17] J. Rabaey, and M. Potkonjak, "Resource Driven Synthesis in the HYPER system," ISCAS-90, vol. 4, pp.
2592-2595, May 1990.
[18] Trickey, H.: "Flamel: A high-Level Hardware Compiler", IEEE Transaction on CAD, Vol. 6, No. 2, pp. 259269,1987.
[19] Valiant, et.al: "Past Parallel Computation of Polynomials Using Few Processes,", SIAM J. on Comp, Vol.
12, No 4, pp. 641-644, 1983.
[20] R.A.Walker, D.E.Thomas,: "Behavioral Transformation for Algorithmic Level IC Design" IEEE Trans on
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ICCAD91, Pages 92-95
An Algorithm for Component Selection in Performance Optimized Scheduling
Loganath Ramachandran and Daniel D. Gajski
Department of Information and Computer Science, University of California, Irvine, CA, 92717
Abstract
This paper describes a new algorithm that combines the Hardware Scheduling and Component
Selection phases for High Level Synthesis. The algorithm improves on previous work in
scheduling, by being able to simultaneously select components from a given library. This
enlarges the design space resulting in better optimized designs. Experimental results on the
elliptic filter benchmark demonstrate that exploiting all available components in the library
result in designs with smaller area compared to designs produced by scheduling with single
implementation for each component type.
References
[1] B. Pangrle and D. Gajski, "State Synthesis and Connectivity Binding for Microarchitecture Compilation," in Proc. o
f the IEEE Conf. on Computer Aided Design., pp. 210-213, IEEE, November 1986.
[2] P. G. Paulin and J. P. Knight, "Scheduling and Binding Algorithms for High-Level Synthesis," in Proc. of the 26th
Design Automation Conf., pp. 1-6, ACM/IEEE, June 1989.
[3] C.Tseng and D. Siewiorek, " Automated Synthesis of Datapaths in Digital Systems," IEEE Transactions on
CAD, pp. 379-395, July 1986.
[4] P. G. Paulin and J. P. Knight, " Force-Directed Scheduling for the Behavioral Synthesis of ASIC's," IEEE
Transactions on CAD, pp. 661-678, June 1989.
[5] R. Cloutier and D. E. Thomas, "The Combination of Scheduling, Allocation and Mapping in a Single Algorithm,"
in Proc. of the 27th Design Automation Conf., ACM/IEEE, June 1990.
[6] A. P. Rajiv Jain and N. Park, "Module Selection for Pipelined Synthesis," in Proc. of the 25th Design Automation Conf., pp. 542-547, IEEE/ACM, June 1988.
[7] R. Jain, "MOSP: Module Selection for Pipelined Designs with Multi-Cycle Operations," in Proc. of the IEEE
Conf. on Computer Aided Design., pp. 212-215, IEEE, September 1990.
[8] L. Ramachandran and D. D. Gajski, "CHASSIS: A Combined Hardware Selection and Scheduling Technique for
Performance Driven Synthesis," tech. rep., ICS Dept, University of California, Irvine, February 1991. 91-20.
[9] J. Lis and D. Gajski, "Synthesis from VHDL," in Proc. of the IEEE Conf. on Computer Design., IEEE,
March 1988.
[10] H. J. W. S.Y Kung and T. Kailath, VLSI and Modern Signal Processing. Prentice Hall Information and
Systems Sciences Series, 1985.
ICCAD91, Pages 98-101
Optimal Module Implementation and Its Application to Transistor Placement
T. W. Her and D. F. Wong
Department of Computer Sciences University of Texas at Austin, Austin, TX 78712
Abstract
In this paper we present an algorithm for selecting implementations for rectangular modules
given a placement of the modules in multiple rows. A module is a rectangle with terminals
located on the top and the bottom edges. An implementation of a module is specified by its
dimension and a placement of the terminals along the top and bottom edges of the module. Our
algorithm accepts as input a placement of the modules and a set of possible implementations of
each module, and selects an implementation for each module to minimize the total height of
the layout. The time complexity of our algorithm is 0(NrKr+K2(NL+LIogL)), where K is the
maximum number of implementations for each module, r is the number of rows, N is the total
number of modules, and L is the channel length. We also present two extensions of the
algorithm. Our algorithm can be applied to the CMOS transistor placement and has been
implemented in the Custom Cell Synthesis System of the MCC Physical Satellite. We tested
the algorithm on cells selected from the MCNC benchmarks and industry, reductions of up to
19% in layout area were obtained.
REFERENCES
[DoLe89] A Domic, S. Levitin, N. Phillips, C. Thai, T. Shiple, Bhavsar, and C. Bissell, "CLEO: A CMOS
Layout Generator", Proc. IEEE International Conference on Computer-Aided Design, Nov 1989.
[GuWo91] M. Guruswamy, and D.F. Wong, "A General Multi-Layer Area Router", Proc. 28th ACM/IEEE
Design Automation Conference, Jun 1991.
[HeWo90] T.W. Her, D.F. Wong, and T.H. Freeman, "Optimal Orientations of Transistor Chains", Proc. IEEE
International Conference on Computer-Aided Design, Nov 1990.
[HsHw91] Y.C. Hsieh, C.Y. Hwang, Y.L. Lin and Y.C. Hsu, "LiB: A CMOS Cell Compiler", IEEE
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[HwHs90] C.Y. Hwang, Y.C. Hsieh, Y.L. Lin and Y.C. Hsu, "A Fast Transistor-Chaining Algorithm for
CMOS Cell Layout", IEEE Transaction on Computer-Aided Design of ICAS, Vol. CAD-9, No. 7,1990.
[KeLi70] B.W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", Bell System
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[NaSt88] R. Nair and A. Stauffer, "Optimal Transistor Orientation in CMOS cell layout", Research Report RC
13419, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, January 1988.
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vanCleemput, "Optimal Layout of CMOS Functional Arrays", IEEE Transacton on Computers, Vol. C-30, No.
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[WiPi87] S. Wimer, R.Y. Pinter, and J.A. Feldman, "Optimal Chaining of CMOS Transistors in a Functional
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ICCAD91, Pages 102-105
Track Assignment in the Pathway Datapath Layout Assembler
Amnon Baron Cohen, Michael Shechory
National Semiconductor (I.C.) Ltd., PO. Box 3007, Herzlia B. 46104, ISRAEL
ABSTRACT
This paper presents a new dynamic programming algorithm for optimizing the assignment of
signals to metal2 tracks, in datapaths. The algorithm is part of the Pathway datapath layout
assembler, which was used in the design of the NS32SF641 microprocessor ([1]). Using this
system, the chip design team at National Semiconductor produced layout as compact as hand
crafted layout, in a fraction of the time.
References
[1] R. Talmudi et el., A 100 MIPS, 64-bit Superscalar Microprocessor with DSP Enhancements, ISSCC TAM5.6,
February 14, 1991.
[2] T. Marshburn et al., Datapath: A CMOS datapath silicon assembler, Proc. of 23rd DAC., pp722-729, 1986.
[3] R. Jamier and A.A. Jerraya, APOLLON, A Datapath Silicon Compiler, Proc. of ICCD, pp308-311, 1985.
[4] D. Curry, Schematic Specification of Datapath Layout, Proc. of ICCD, pp28-34,1989.
[5] H. Cai, S. Note, P. Six and H. De Man, A Data Path Layout Assembler for High Performance DSP Circuits,
Proc of 27th DAC, pp306-311,1990.
ICCAD91, Pages 106-109
Flexible Block-Multiplier Generation
H.M.A.M. Arts, J.T.J. van Eijndhoven and L. Stok*
Design Automation Section, Eindhoven University of Tech, Eindhoven, The Netherlands *Computer Science
Department, IBM TJ Watson Research Center, Yorktown Heights, NY 10598
Abstract
In a high level synthesis environment there is a strong need for flexible module generators. For the
generation of regular structures efficient dedicated module generators can be built. This paper
describes the structure of a 'block-multiplier', which features a wide range of area-time trade-o f f s
m a i n t a i n i n g efficiency. The structure makes it possible to implement a fully serial or a fully
parallel multiplier and many combinations in between. A new concept for the Carry-Hold circuitry
plays a key role. The theoretically derived formulas which describe the relations between the area,
timing and bitwidth of this multiplier structure are verified by a large number of experiments.
References
[1] De Man H., J. Rabaey, and L. Claesen, "Cathedral-II A siliconcompiler for digital signal processing", Computer,
December 1986. pp.13-25.
[2] Camposano, R. and R.K. Brayton, "Partitioning before logic synthesis", Proc. of the IEEE International
Conference on Computer Aided Design 1987. pp. 324-326.
[3] Brayton, R.K., et al."MIS: A multiple level logic optimization system", IEEE Trans. on comp. aided design, Vol.
6, 1987.
[4] DeMicheli, G. and D.C. Ku, "HERCULES: a system for high level synthesis", Proceedings of the 25th Design
Automation Conference, June 1988. pp. 483-488.
[5] Davio, M. and J.-P, Deschamps, A. Thayse, "Digital Systems with algorithm implementation", John Wiley, New
York, 1983.
[6] Hill, F and G. Peterson, "Digital Systems hardware organization and design", John Wliley, New York, 1987. pp.
542-550
[7] Chu, Y, "Digital Computer Design Fundamentals", McGraw-Hill, New York, 1962
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[9] Maden, B. and C.G. Guy, "Parallel Architectures for High Speed Multiplication", IEEE International Symposium
on Circuits and Systems„ 1989. pp. 142-145.
ICCAD91, Pages 112-115
Transient Three-Dimensional Mixed-Level Circuit and Device
Simulation: Algorithms and Applications
Kartikeya Mayaram, Ping Yang, and Jue-Hsien Chern
Semiconductor Process and Design Center Texas Instruments, Dallas TX 75265
Abstract
This paper describes algorithms for transient mixed-level circuit and device simulation using a
two-carrier three-dimensional (3D) device simulator SIERRA and the circuit simulator SPICE3.
Algorithms well suited to two-dimensional mixed-level circuit and device simulation cannot be
successfully used. The memory and CPU time requirements in 3D device simulation necessitate
the use of iterative solution techniques at the device level, which impose an additional constraint
in developing efficient algorithms. An application of 3D mixed-level simulation to the study of
single-event upset of SRAM cells is presented.
References
[1] W. L. Engl, R. Laur, and H. K. Dirks, "MEDUSA - A Simulator for Modular Circuits," IEEE Trans. CAD, pp. 8593, April 1982.
[2] M. S. Mock, Analysis of Mathematical Models of Semiconductor Devices, Boole Press, pp. 171-193,1983.
[3] J. G. Rollins and J. Choma, "Mixed-Mode PISCES-SPICE Coupled Circuit and Device Solver," IEEE Trans.
CAD, pp. 862-867, Aug. 1988.
[4] K. Mayaram "CODECS: A Mixed-Level Circuit and Device Simulator," Memo. No. UCB/ERL M88/71, ERL,
University of California, Berkeley, Nov. 1988.
[5] J. R. F. McMacken and S. G. Chamberlain, "CHORD: A Modular Semiconductor Device Simulation Development
Tool Incorporating External Network Models," IEEE Trans. CAD, pp 826-836, Aug. 1989.
[6] J. S. Fu, C. L. Axness, and H. T. Weaver, "Memory SEU Simulations Using 2-D Transport Calculations," IEEE
Elec. Dev. Letters, pp. 422-424, Aug. 1985.
[7] A. Ochoa, Jr., C. L. Axness, H. T. Weaver, and J. S. Fu "A Proposed New Structure for SEU Immunity In SRAM
Employing Drain Resistance," IEEE Elec. Dev. Letters, vol. pp. 537-539, Nov. 1987.
[8] J. H. Chern, J. T. Maeda, L. A. Arledge, and P. Yang, "SIERRA: A 3-D Device Simulator for Reliability Modeling," IEEE Trans. CAD, pp. 516-527, May 1989.
[9] T. L. Quarles, " The SPICE3 Implementation Guide," Memo. No. UCB/ERL M89/44, ERL, University of
California, Berkeley, April 1989.
[10] K. Mayaram, P. Yang, J. Chern, R. Burch, L. Arledge, and P. Cox, "A Parallel Block-Diagonal Preconditioned
Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations," Proc. ICCAD-90, pp. 446-449, Nov.
1990.
[11] R. A. Rohrer, "Circuit Partitioning Simplified," IEEE Trans. Circuits and Systems, pp. 2-5, Jan. 1988.
ICCAD91, Pages 116-119
Conjugate Direction Waveform Methods for Transient
Two-Dimensional Simulation of MOS Devices
Andrew Lumsdaine, Mark Reichelt, Jacob White
Research Laboratory of Electronics, Dept. of Electrical Engineering and Computer Science, Massachusetts Institute
of Technology, Cambridge, MA 02139
Abstract
In this paper, a conjugate-direction based acceleration to the waveform relaxation
algorithm is derived and then applied to solving the differential-algebraic system
generated by spatial discretization of the time-dependent semiconductor device equations.
In the experiments included, the conjugate-direction waveform methods are up to 15
times faster than ordinary WR
References
[1] W. Engl, R. Laur, and H. Dirks, "MEDUSA - A simulator for modular circuits," IEEE Trans. CAD, vol. 1, pp.
85-93, April 1982.
[2] M. Reichelt, J. White, and J. Allen, "Waveform relaxation for transient two-dimensional simulation of MOS
devices," in International Conference on Computer Aided-Design, (Santa Clara, California), pp. 412-415,
November 1989.
[3] S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer-Verlag,1984.
[4] R. Bank, W. Coughran, Jr., W. Fichtner, E. Grosse, D. Rose, and R. Smith, "Transient simulation of silicon devices
and circuits," IEEE Trans. CAD, vol. 4, pp. 436-451, October 1985.
[5] K. Mayaram and D. Pederson, "CODECS: A mixed-level device and circuit simulator," in International
Conference on Computer Aided-Design, (Santa Clara, California), pp. 112-115, November 1988.
[6] E. Lelarasmee, A. E. Ruehli, and A. L. Sangiovanni-Vincentelli, "The waveform relaxation method for time domain
analysis of large scale integrated circuits," IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. 1, pp. 131-145, July 1982.
[7] H. C. Elman, Iterative Methods for Large Sparse Nonsymmetric Systems of Linear Equations. PhD
thesis, Computer Science Dept., Yale University, New Haven, CT, 1982.
[8] J. K. White and A. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits.
Engineering and Computer Science Series, Norwell, Massachusetts: Kluwer Academic Publishers, 1986.
[9] R. Saleh and J. White, "Accelerating relaxation algorithms for circuit simulation using waveform-newton and stepsize refinement," IEEE Trans. CAD, vol. 9, no. 9, pp. 951-958, 1990.
[10] D. Erdman and D. Rose, "A newton waveform relaxation algorithm for circuit simulation," in International
Conference on Computer Aided-Design, (Santa Clara, California), pp. 404-407, November 1989.
[11] P. Brown and Y. Saad, "Hybrid Krylov methods for nonlinear systems of equations," SIAM J. Sci. Statist.
Comput., vol. 11, pp. 450-481, May 1990.
[12] Y. Saad and M. Schultz, "GMRES: A generalized minimum residual algorithm for solving nonsymmetric linear
systems," SIAM J. Sci. Statist. Comput., vol. 7, pp. 856-869, July 1986.
[13] R. Kress, Linear Integral Equations. New York: SpringerVerlag, 1989.
ICCAD91, Pages 120-123
Transient Sensitivity Computation for Waveform Relaxation-Based Timing Simulation
Chun-Jung Chen, Jyuo-Min Shyu*, Wu-Shiung Feng
Dept. of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C
*Computer & Communication Research Laboratories, Industrial Technology Research Institute, Hsinchu,
Taiwan, R.O.C
Abstract
Transient sensitivity computation is very important in many areas. In this paper, we present a
method to compute the transient sensitivities for Waveform Relaxation (WR)-based circuit
simulation. By partitioning the circuit into subcircuits, we compute the transient sensitivities
for each "active" subcircuit and then propagate the calculated results to the succeeding
subcircuits to iterate for the entire sensitivities. Experimental results are shown to demonstrate
the effectiveness of our proposed method.
Reference
[1] S. W. Director and R. A. Rohrer, "The generalized adjoint network and network
sensitivities," IEEE Trans. on Circuit Theory, vol. CT-16, pp. 318-323, Aug. 1969.
[2] D. A. Hocevar, P. Yang, T. N. Trick, and B. D. Epler, "Transient sensitivity computation for
MOSFET circuits, " IEEE Trans. on Computer-Aided Design, vol. CAD-4, pp. 609-620, Oct.
1985.
[3] E. Lelarasmee, A. E. Ruehli, A. L. Sangiovanni-Vincentelli, "The Waveform Relaxation
method for time-domain analysis of large scale integrated circuits," IEEE Tran. on ComputerAided Design, vol. CAD-1 , pp. 131-145, Aug. 1982.
[4] T. V. Nguyen, P. Feldmann, S. W. Director and R. A. Rohrer, "SPECS simulation validation
with efficient transient sensitivity computation," ICCAD, pp. 252-255, 1989.
[5] W. T. Nye, D. Riley, A. Sangiovanni-Vincentelli, and A. L. Tits, "DELIGHT.SPICE: an
optimization-based system for the design of integrated circuits," IEEE Trans. on ComputerAided Design, vol. CAD-7, pp. 501-519, Apr. 1988.
[6] Jyuo-Min Shyu and A. Sangiovanni-Vincentelli, "ECSTASY: a new environment for IC
design optimization," ICCAD, pp. 484-487,1988.
[7] Chun-Jung Chen, "MOSTIME-a MOS timing simulator," Master Thesis, Department of
Electrical Engineering, National Taiwan University, 1989.
ICCAD91, pages 126-129
Heuristic Minimization of Multiple-Valued Relations
Yosinori Watanabe and Robert K. Brayton
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Abstract
A multiple-valued relation is a relation in which the input variables can assume more than two
discrete values. Multiple-valued relations arise quite naturally in many contexts. Using
characteristic functions to represent relations, we can handle the problem of minimizing
multiple-valued relations as a generalization of the conventional minimization problem of
regular logic functions. Our approach is based on a state-of-the-art paradigm for the two level
minimization of regular functions. We clarify some special properties of relations, in contrast to
functions, which must be carefully considered in realizing a high quality procedure for solving
the minimization problem. An efficient heuristic method to find an optimal sum-of-products
representation is proposed and implemented in the program GYOCRO.
References
[1] R. K. Brayton, G. D. Hachtel, C. McMullen, and A. SangiovanniVincentelli. Logic Minimization Algorithms for
VLSI Synthesis. Kluwer Academic Publishers, Boston, 1984.
[2] A. Ghosh, S. Devadas, and A. R. Newton. Heuristic Minimization of Boolean Relations using Testing Techniques.
In ICCD, September 1990.
[3] B. Lin and F. Somenzi. Minimization of Symbolic Relations. In ICCAD, 1990.
[4] F. Somenzi and R. K. Brayton. An Exact Minimizer for Boolean Relations. In ICCAD,1989.
[5] A. Srinivasan, T. Kam, S. Malik, and R. K. Brayton. Algorithms for Discrete Function Manipulation. In
ICCAD,1990.
[6] Y. Watanabe. Minimization of Multiple-Valued Relations. Technical Report UCB/ERL M91/48, UC Berkeley,
1991.
ICCAD91, pages 130-133
LSAT - An Algorithm for the Synthesis of Two Level Threshold Gate Networks
Arlindo L. Oliveira,
Dept. of EECS, UC Berkeley, Berkeley CA 94720
Alberto Sangiovanni-Vincentelli
Dept. of EELS, UC Berkeley, Berkeley CA 94720
Abstract
We present an algorithm for the synthesis of two-level threshold gate networks inspired
in techniques used in classical two-level minimization of logic circuits. We specifically
address a restricted version of the problem where the on and off set minterms are explicitly listed. Experimental results show that a simple branch and bound algorithm can
be used to obtain solutions close to the absolute minimum in a set of standard problems,
outperforming other minimizers even when restricted to use only classic logic gates as
building blocks.
References
[1] K. Y. Siu & J. Bruck "On the Power of Threshold Circuits with Small Weights", to appear in SIAM J. Discrete
Math.
[2] K. Y. Siu & J. Bruck "Neural Computation of Arithmetic Functions" Proc. IEEE, 78, No. 10:1669-1675, October
1990.
[3] A. Blumer, A. Ehrenfeucht, D. Haussler & M. Warmuth "Occam's Razor", Information Processing Letters, vol
24, pp. 377-380, North-Holland, 1987.
[4] R. Brayton, G. Hachtel, C. McMullen & A. Sangiovanni-Vincentelli "Logic Minimization Algorithms for VLSI
Synthesis", Kluwer Academic Publishers, 1984.
[5] R. Brayton, G. Hachtel & A. Sangiovanni-Vincentelli "Multilevel Logic Synthesis", Proceedings of the IEEE,
vol. 78:2, pp. 264-300, February 1990.
[6] S. Muroga "Threshold Logic and its Applications", Wiley-Interscience, 1971.
[7] A. Oliveira "Logic Synthesis Using Threshold Gates", Internal Memo, UC Berkeley, 1990.
[8] G. Pagallo & D. Haussler "Boolean Feature Discovery in Empirical Learning", Machine Learning, 5:71-99,
1990.
ICCAD91, pages 134-137
Layout Driven Logic Restructuring/Decomposition
Massoud Pedram and Narasimha Bhat
Department of Electrical Engineering and Computer Science, University of California, Berkeley CA 94720
Abstract
As feature sizes decrease and chip sizes increase, the area and performance of chips become
dominated by the interconnect. In spite of this trend, most existing synthesis systems relegate the
interconnect optimization to physical design. Physical design is, however, too far down in the
design pipeline to meet the performance specifications by itself. Therefore, it is necessary for
synthesis tools to share part of this optimization. In this paper, we present techniques to integrate
interconnection optimization with logic restructuring and technology decomposition phases of
logic synthesis. Our approach is based on a point placement of a Boolean network which is used to
guide the synthesis process by providing accurate estimates on wiring area and delay. The
placement solution is incrementally updated as intermediate Boolean nodes are extracted or
eliminated during the decomposition or elimination procedures. Combining these techniques with
layout-driven technology mapping enables us to to produce a synthesis solution and a "companion"
placement solution for a given combinational logic circuit simultaneously. Using these techniques,
we are able to generate circuits with smaller area and higher performance.
References
[1] P. Abouzeid, K. Sakouti, G. Saucier and F. Poirot, "Multilevel synthesis minimizing the routing factor," Proc.
27th ACM/IEEE Design Automation Conf., pages 365-368,1990.
[2] R.
Murgai,
Y. Nishizaki,
N.
Shenoy, R. K. Brayton and A. Sangiovanni-Vincentelli,
"Logic synthesis for programmable gate arrays," Proc. 27th ACM/IEEE Design Automation Conf., pages 620625,1990.
[3] R. K. Brayton and C. McMullen, "The decomposition and factorization of boolean expressions," Proc. Int.
Symp. Circuits and Systems, Rome, May 1982.
[4] R. K. Brayton, "Algorithms for multilevel synthesis and optimization," G. De Micheli, A. SangiovanniVincentelli and P. Antognetti, Editors, Design Systems for VLSI Circuits: Logic Synthesis and Silicon
Compilation, Martinus Nijhoff,1987.
[5] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli and A. Wang, "MIS: a multiple-level logic optimization
system," IEEE Trans. on Computer-Aided Design, Vol. CAD-6, No. 6, pages 1062-1081, November 1987.
[6] R. Rudell, "Logic synthesis for VLSI design," Ph.D. dissertation, University of California, Berkeley, 1989.
[7] J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, "GORDIAN: VLSI placement by quadratic
programming and slicing optimization," IEEE Trans. on Computer-Aided Design, Vol. 10, No. 3, pages 356-365,
March 1991.
[8] A. Srinivasan, K. Chaudhary and E. S. Kuh, "RITUAL: an algorithm for performance-driven placement of
cell-based ICs," Proc. Third Physical Design Workshop, May 1991.
[9] M. Pedram and N. Bhat, "Layout driven technology mapping," Proc. 28th ACMIIEEE Design Automation
Conf., pages 99-105,1991.
[10] R.E. Burkhard and U. Derigs, "Assignment and matching problems: solution methods with Fortran
programs," Springer Verlag, 1980.
[11] H. Savoj, H. -Y. Wang, "Improved scripts in MIS-H for logic minimization of combinational circuits," Proc.
Int. Workshop on Logic Synthesis, Vol. 3,1991.
ICCAD91, Pages 140-143
Data Framework for VLSI Design
Amir Milo, Smadar Nehab
Motorola Semiconductor Israel Ltd., POB 32288, Tel-Aviv, Israel 61322
email: milo@msil.sps.mot.com
Abstract
In this paper we present a design automation framework (DAF) implementation that was
developed in an advanced full custom IC design environment at Motorola Semiconductor Israel.
This framework, named TDF (Tools and Data Framework) operates in a large-scale multi-user,
multi-node environment. TDF successfully supports all the necessary requirements of a VLSI
design framework: data hiding, versioning, atomicity and recovery of mass files operations;
concurrency control and data sharing for design-team work. In addition to the extensive data
management services, TDF provides an open environment for tool integration.
We emphasize two aspects of TDF: the data model and the dynamic configuration mechanism.
The data model directly reflects the data partitioning of IC designs, thereby allowing efficient
navigation in the design database. The dynamic configuration mechanism is a simple and
powerful format for the definition of ad-hoc configurations, such as: design integration, revisions
freeze, and mixed-view.
References
[1] E. Aurand, T. Shavit: Architecture of a computer Integrated Engineering System, VLSI System Design, June 1986, pp.
58 - 66.
[2] M. L. Bushnell, S. W. Director. VLSI Cad Tool Integration Using the ULYSSES Environment, Proc. 23th ACM/ IEEE
Design Automatation Conference, 1986, pp. 55-61.
[3] J. Daniell, S. W. Director: An Object Oriented Approach to CAD Tool Control Within a Design Framework, Proc. 26th
ACM/IEEE Design Automation Conference, 1989, pp. 197-202.
[4] -, Using PowerFrame, Digital Equipment Corporation.
[5] D. Gedye, R. H. Katz: Browsing the Chip Design Database, Proc. 25th ACM/IEEE Design Automation Conference,
Anaheim 1988, pp. 269 - 274.
[6] D. S. Harrison, P. Moore, R. L. Spickelmier, and A. R. Newton: Data Management and graphics editing in the Berkeley
Design Environment, IC Computer Aided Design 1986, pp. 24-27.
[7] R.H. Katz: Information Management for Engineering Design, Springer-Verlag, Berlin Hiedelberg New York Tokyo 1985.
[8] R. H. Katz, M. Anwarrudin, E. Chang: A Version Server for Computer-Aided-Design Data, Proc. 23rd IEEE Design
Automation Conference, Las Vegas 1986, pp. 27 - 33.
[9] P. Kollaritsch, S. Lusky, D. Matzke, D. Smith, P. Stanford: A Unified Design Representation Can Work, Proc. 26th
ACM/IEEE Design Automation Conference, 1989, pp. 811- 813.
[10] E. Siepmann: A Data Management Interface as part of the Framework of an integrated VLSIDesign System, IC
Computer Aided Design 1989, pp. 284 - 287.
[11] M. Silva, D. Gedye, R. Katz, R. Newton: Protection and Versioning for OCT, Proc. 26th ACM/IEEE Design Automation
Conference, 1989, pp. 264 - 269.
[12] A. Singhal, N. Parikh, D. Dutt, C. Lo: A Data Model and Architecture for VLSI/CAD Databases, IC Computer Aided
Design 1989, pp. 276 - 279.
[13] E. Siepmann, G. Zimmermann: An Object-Oriented Datamodel for the VLSI Design System PLAYOUT, Proc. 26th
ACM/IEEE Design Automation Conference, 1989, pp.814-817.
[14] W. Wolf, An Object-Oriented, Procedural Database for VLSI Chip Planning, Proc. 23rd IEEE Design Automation
Conference, Las Vegas 1986, pp. 744 - 751.
ICCAD91, Pages 144-147
SLIM : A System for ASIC Library Management
Mahesh Mehendale, P Murugavel, Poornima M.,
Chandra Mohan Nibhanupudi, Arunabha Ghose
Texas Instruments (India) Pvt. Ltd., 71 Miller Road, Bangalore, INDIA 560 052
Abstract
The paper presents SLIM, a System for ASIC Library Management, which provides an Integrated
environment for managing ASIC library development flows and data at various levels of
abstractions such as functional, physical, generic and workstation specific. The salient features of
the system include i. parallel distributed flow execution, ii. multi-layered, hierarchical
configuration management, iii. dynamic status tracking and iv. multi-user environment. These
along with the data and project management capabilities help in improving the library quality and
reducing the cycle time. Implementation details are presented in terms of an innovative architecture
and a systems engineering approach using DSEE,( Domain Software Engineering Environment - a
CASE tool from Apollo-HP). Two library development flows for which SLIM has been
successfully used are also described.
References
[1] TSC500 series, 1 µm CMOS standard cells - Data Manual, Texas Instruments Inc.
[2] Bushnell M.L. and Director S.W.,"VLSI CAD Tool Integration using the ULYSSES Environment", Proceedings of
23rd Design Automation Conference, pp 55-61
[3] Mehmood Z., Singhal A., Srinivas N. C., Taylor S. L., Wu K., "IDEAS - An Integrated Design Automation
System", Proceedings of ICCD-1987, pp 407-412
[4] Arding Hsu and Liang-Hua Hsu, "HILDA: An Integrated System Design Environment", Proceedings of ICCD1987, pp 398-402
[5] Brouwers J. and Gray M, "Integrating the Electronic Design Process", VLSI Systems Design, June 1987, pp 38-47
[6] Mehendale M. and
Krishna M.G., "PRIDE: PRogrammable user Interface for a Design Environment", VLSI
DESIGN, Proceedings of the Third International workshop on VLSI Design, Tata McGraw-Hill, India, January 1990,
pp 211-218
[7] Engineering in the DSEE environment, Apollo Computer Inc, 1988
[8] Domain Software Engineering Environment (DSEE) call reference manual, Apollo Computer Inc., 1988
ICCAD91, Pages 148-151
Estimating Essential Design Characteristics to Support Project
Planning for ASIC Design Management
K.D. Müller-Glaser, K. Kirsch, K. Neusinger
Institute of Computer-Aided Circuit Design, University of Erlangen-Nürnberg,
Wetterkreuz 13, D-8520 Erlangen, Germany
Abstract
To enhance project planning and feasibility study for ASIC design a Chip Estimation
System (CES), tightly coupled with a Projectplan Generator System (PGS) has been
developed. The Chip Estimation System calculates chip area, speed and power dissipation
from data of a knowledge based data acquisition system which gathers basic design
characteristics, requirement specification data and information about complexity and
problems of a design. The resulting data are transferred to the Project-Plan Generator
System which generates alternative projectplans based on a design style specific
knowledge base. In using vendor and technology specific cost factors, estimation of
design time and design-, production- and testcosts are calculated. The Project-Control
System controls execution of a selected projectplan.
References
[1] Müller-Glaser, K.D.; Bortolazzi, J.: An Approach to Computer-Aided Specification, J. SSC, Vol.25, No.2,
1990
[2] Miller, J. et al.: The Object-Oriented Integration Methodology of the Cadlab Work Station Design
Environment, 26th ACM/IEEE DAC 1989
[3] UNIX Product Directory 1990
[4] Zimmermann, G.: A new area and shape function estimation technique for VLSI layouts, 25th IEEE/ACM
DAC 1988
[5] Kurdahi, F.J., Parker, A.C.: Techniques for area estimation of VLSI layouts, IEEE Trans. on CAD, Vol.8, Jan.
1989
[6] Bakoglu, H.B.: Circuits, Interconnections and Packaging, Addision-Wesley Publishing Company 1990,
[7] Najm, F.; Burch, R.; et al.: Crest - A current estimator for CMOS circuits, IEEE Int. Conf. on CAD 1988
[8] Lin,Tzu-Mu; Mead, Carver A.: Signal Delay in General RC Networks, IEEE-Trans. on CAD, 1984, pp 331337
[9] Schmitt, F.: Synthesis- and analysis problems in computer aided VLSI Design, Ph.D. Thesis Univ. of
Saarbrücken 1988
[10] Ruehli, A. E.: Circuit Analysis, Simulation and Design, North-Holland, Amsterdam, 1987
[11] Donath, Wilm E.: Equivalence of Memory to Random Logic, IBM Journal of R&D (1974)
[12] Donath, Wilm E.: Wire Length Distribution for Placements of Computer Logic, IBM J. of R&D (1981),Vol.
25
[13] K. Kirsch, B. Koch, K.D. Müller-Glaser: Fast chip area and power estimation in early ASIC design phases,
SMT/ASIC/Hybrid 90 Int. Conf, Nürnberg, May 1990
ICCAD91, Pages 152-155
Rapid-Prototyping of Hardware and Software in a Unified Framework
Mani B. Srivastava, Robert W. Brodersen
EECS Department, University of California at Berkeley
ABSTRACT
ASICs alone do not make a system, which necessarily has a mix of custom and off-shelf
hardware, and requires both hardware and software components. Experience with real-time
dedicated systems has shown that as much time is spent in designing the boards and the software
to drive and integrate the hardware as is spent in the design of custom chips used in the system.
These issues have largely been ignored by the current CAD systems. In this paper we describe a
CAD framework that has been developed and used for the design of several dedicated multiboard real-time systems using dedicated hardware modules as well as software processes running
on programmable hardware modules. The main contribution of this work is the handling of board
level module generation, system software generation, and hardware-software integration in a
unified framework.
References
[1] C. S. Shung, et al. An Integrated CAD System for Algorithm-Specific IC Design. IEEE Transactions on CAD of
ICs and Systems, April 1991.
[2] C. M. Chu, et al. HYPER: An Interactive Synthesis Environment for Real Time Applications. Proceedings of
ICCD 1989, October 1989.
[3] L. Thon, et al. From C to Silicon with LagerIV. IEEE/ACM Physical Design Workshop, May 1989.
[4] J. Rabaey, et al. Cathedral-II: A synthesis system for multiprocessing DSP systems. Silicon Compilation,
Addison-Wesley, 1988.
[5] Stuart Bennett. Design of Real-Time Systems. Chapter 5 of Real-Time Computer Control: An Introduction,
Prentice-Hall, 1988.
[6] H. Gomaa. A Software Design Method for Real-Time Systems. Communications of the ACM, Sept. 1984.
[7] Rudy Lauwereins, et al. GRAPE: A CASE Tool for Digital Signal Parallel Processing. IEEE ASP Magazine,
April 1990.
[8] E. A. Lee, et al. GABRIEL: A Design Environment for Programmable DSPs. IEEE Design Automation
Conference, June 1989.
[9] Michael Brady. The Problems of Robotics. Chapter 1 of Robotics Science, The MIT Press, 1989.
[10] M. B. Srivastava, and R. W. Brodersen. High-Level Mixed-Mode System Simulation in VHDL. Proceedings of
the VHDL User's Group Spring 1991 Conference, April 1991.
[11] W. B. Baringer. A Radon Transform Image Processing System. Ph. D. Thesis, EECS Department, U. C.
Berkeley.
[12] Gautam Doshi. Design and Implementation of a Six-Axis Robot Controller. M. S. Report, EECS Department,
U. C. Berkeley, 1989.
[13] J. S. Sun, et al. SIERA: A CAD Environment for Real-Time Systems. 3rd IEEE/ACM Physical Design
Workshop, May 1991.
[14] B. Richards. SDL Language Manual. U. C. Berkeley.
ICCAD91, Pages 158-161
Improved Methods for IC Yield and Quality Optimization using Surface Integrals
Peter Feldmann
AT&T Bell Labs
Murray Hill, NJ
Stephen W Director
Electrical and Computer Engineering
Carnegie Mellon University
Abstract
A novel formulation of the parametric yield as a surface integral on the boundary of the
disturbance space acceptability region is introduced. This formulation allows the accurate and
efficient estimation of yield via a Monte Carlo method which can also produce yield gradients
with minimal overhead. Under mild assumptions, the surface integral based yield estimate is
continuous and practically twice differentiable almost everywhere, therefore it is ideally suited
for use with powerful gradient based optimization algorithms. A general IC quality optimization
method, significantly more efficient than Taguchi's method, is also introduced. This method can
handle multiple performances and handles yield maximization as a special case.
References
[1] P. Feldmann and S.W. Director, "Accurate and efficient evaluation of circuit yield and yield gradients," ICCAD,1990.
[2] P. Feldmann, Statistical Integrated Circuit Design. Ph.D. thesis, Carnegie Mellon University, Pittsburgh, PA, Jan.
1991.
[3] H.M. Edwards, Advanced Calculus. Boston: Houghton Mifflin Company, 1969.
[4] R.Y. Rubinstein, Simulation and the Monte Carlo Method. New York: John Wiley Sons, Inc., 1981.
[5] P.Feldmann and S.W. Director, "A macromodeling based approach for efficient IC yield optimization," ISCAS,1991.
[6] P. Gill, W. Murray, M. Saunders, and M. Wright, "User's guide for NPSOL (version 4.0)," Tech. Rep. SOL 86-2,
Systems Optimization Laboratory, Stanford University, Jan. 1986.
[7] J. Bandler, S. Chen, S. Daijavad, K. Madsen, "Efficient optimization with integrated gradient approximations," IEEE
Trans. on Microwave Theory and Techniques, vol. 36, Feb. 1988.
[8] M. S. Phadke, Quality engineering using robust design. Englewood Cliffs, New Jersey: Prentice Hall, 1989.
[9] L. Opalski and M. Styblinski, "Generalization of yield optimization problem: The maximum income approach," IEEE
Trans. on CAD-ICAS, vol. CAD-5, pp. 346-60, Apr. 1986.
[10] W. Welch, T. Yu, S. Kang, and J. Sacks, "Computer experiments for quality control by parameter design," Journal of
Quality Technology, vol. 22, pp. 15--22, Jan. 1990.
[11] P. Feldmann, T. V. Nguyen, S. W. Director, and R. A. Rohrer, "Sensitivity computation in piecewise approximate
circuit simulation," IEEE Trans. on CAD-ICAS, vol. 10, Feb. 1991.
ICCAD91, Pages 162-165
New Simulation Methods for MOS VLSI-Timing and Reliability
Y.-H. Shih, Y. Leblebici, and S. M. Kang
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois 61801
Abstract
A new approach to incorporating the channel length modulation in a direct-equation solving fast
timing simulator is presented along with a mixed event-driven and waveform relaxation
algorithm to handle MOS VLSI circuits with feedbacks. Simulation speedup of 3N, over SPICElike simulators, has been observed, where N is the number of transistors. The simulator is able to
simulate circuits as large as 235,000 transistors in 10 minutes real time. Also presented in the
paper is a new approach to fast hot-carrier reliability simulation. These new methods make it
possible to achieve accurate and fast hot-carrier reliability simulation of MOS circuits each with
as many as hundreds of thousands of MOS transistors in workstation environment.
References
[1] Y.-H. Shih and S. M. Kang. ILLIADS: A new fast MOS timing simulator using direct-equation solving
approach. In Proceeding of the ACM/IEEE Design Automation Conference, pages 20-25, June 1991.
[2] Y. Leblebici and S. M. Kang. An integrated hot-carrier degradation simulator for VLSI reliability analysis. In
Proceeding of the IEEE International Conference on Computer-Aided Design, pages 400-403, Nov 1990.
[3] Y. Leblebici, P. C. Li, S. M. Kang, and I. N. Hajj. Hierarchical simulation of hot-carrier induced damages in
VLSI circuits. In Proceeding of the IEEE Custom Integrated Circuits Conference, pages 29.3.1-29.3.4, May 1991.
[4] E. Acuna, J. P. Dervenis, A. J. Pagones, F. L. Yang, and R. A. Saleh. Simulation techniques for mixed
analog/digital circuits. IEEE Journal of Solid-State Circuits, 25(2):353-363, April 1990.
[5] A. T. Yang and S. M. Kang. A novel circuit simulation program with emphasis on new device model
development. In Proceeding of the ACMIIEEE Design Automation Conference, pages 630-633, Jun 1989.
ICCAD91, Pages 166-169
Circuit Optimization Driven by Worst-Case Distances
Kurt J. Antreich, Helmut E. Graeb
Institute of Electronic Design Automation, Technical University of Munich, D-8000 Munich 2, Germany
Abstract
In this paper, a new method for circuit optimization in face of manufacturing process
variations is presented. It is based on the characterization of the feasible design space by
worst-case points and related gradients. The expense for this characterization is linear with
the number of circuit performances. On the contrary, the complexity of other geometric
approaches to tolerance oriented circuit design increases exponentially with the dimension of
the design space. A deterministic optimization procedure based on the so-called "worst-case
distances" will be introduced, combining nominal and tolerance design in a single design
objective. The entire optimization process with regard to performance, yield, and robustness
uses sensitivity analyses and requires a much smaller number of simulations than the Monte
Carlo based approaches. Moreover, the new method takes account of the partitioning of the
parameter space into deterministic and statistical parameters, which is an inherent property of
integrated circuit design.
References
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[2] K. J. Antreich and H. E. Graeb. A unified approach towards nominal and tolerance design. Proc. IMACS World
Congress on Applied Mathematics, 1991.
[3] K. J. Antreich and R. K. Koblitz. Design centering by yield prediction. Trans. IEEE CAS, 29, 1982.
[4] K. J. Antreich, P. Leibner, and F. Poernbacher. Nominal design of integrated circuits on circuit level by an
interactive improvement method. Trans. IEEE CAS, 35:1501-1511,1988.
[5] J. W. Bandler and S. H. Chen. Circuit optimization: The state of the art. Trans. IEEE MTT, 36:424-442,1988.
[6] R. K. Brayton, G. D. Hachtel, and A. L. Sangiovanni-Vincentelli. A survey of optimization techniques for
integrated-circuit design. Proc. of the IEEE, 69:1334-1363,1981.
[7] S. W. Director, W. Maly, and A. J. Strojwas.
VLSI Design for Manufacturing: Yield Enhancement.
Kluwer Academic Publishers, USA, 1990.
[8] P. Feldmann and S. W. Director. Accurate and efficient evaluation of circuit yield and yield gradients. Proc.
IEEE ICCAD, pages 120-123,1990.
[9] D. E. Hocevar, P. F. Cox, and P. Yang. Parametric yield optimization for MOS circuit blocks. Trans. IEEE
CAD, 7:645-658, 1988.
[10] G. Kjellstroem and L. Taxen. Stochastic optimization in system design. Trans. IEEE CAS, 28:702-715,1981.
[11] M. R. Lightner, T. N. Trick, and R. P. Zug. Circuit optimization and design. In A. E. Ruehli, editor, Circuit
Analysis, Simulation and Design, Part 2, North-Holland, 1987.
[12] W. Maly. Computer-aided design for VLSI circuit manufacturability. Proc. of the IEEE, 78:356-392,1990.
[l3] G. E. Mueller-L. Limit-parameters: the general solution of the worst-case problem for the linearized case. Proc.
IEEE ISCAS, 1990.
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9:645-658,1979.
[15] R. Spence and R. S. Soin. Tolerance Design of Electronic Circuits. Addison-Wesley, England, 1988.
[16] M. A. Styblinski and L. J. Opalski. Algorithms and software tools for IC yield optimization based on
fundamental fabrication parameters. Trans. IEEE CAD, 5:79-89,1986.
[17] E. Wehrhahn and R. Spence. The performance of some design centering methods. Proc. IEEE ISCAS, 1984.
ICCAD91, Pages 170-173
Circuit Performance Variability Reduction:
Principles, Problems, and Practical Solutions
M. A. Styblinski and J. C. Zhang
Department of Electrical Engineering, Texas A & M University, College Station, TX 77843
Abstract
This paper presents several novel results in the area of variability minimization. We develop
variability gradient formula, give the theoretical conditions for variability minimization, and
outline the principles and practical solutions of factor screening for variability. A multi-stage
procedure is described for "on target" design, based on variability gradient information, "dynamic"
screening, performance variance minimization, and separate "on target" tuning. This methodology
was successfully applied to the variability minimization of a practical CMOS delay circuit, after
several direct methods of "on target" oriented methods failed.
References
[1] G. Taguchi, "Off-line and On-line Quality Control Systems", Proc. of International Conference on Quality
Control, Tokyo, Japan, 1957.
[2] P. J. Ross, Taguchi Techniques for Quality Engineering, McGraw-Hill Book Company, 1958
[3] P. Cox, P. Yang, S. S. Mahant-Shetti, P. Chatterjee, "Statistical Modeling for Efficient Parametric Yield
Estimation of MOS VLSI Circuit", IEEE Trans. Electron Device, vol. ED-32, no. 2, pp. 471-475, Feb. 1955
[4] Aloke Dey, Orthogonal Fractional Factorial Design, Halsted Press. 1985.
[5] J. C. Zhang and M. A. Styblinski, "Design of Experiments Approach to Gradient Estimation and its
Application to CMOS Circuit Stochastic Optimization" IEEE Proc. ISCAS'91, Singapore, June 1991.
[6] T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, "iEDISON: A Interactive Statistical Design Tool for
MOS VLSI Circuits", IEEE Proc. ICCAD'88, pp 20-23.
[7] M. A. Styblinski and J. C. Zhang, "The Theoretical and Practical Problems of Circuit Performance
Variability Reduction", submitted to IEEE Trans. on CAD.
[8] M. A. Styblinski and S. A. Aftab "Efficient Circuit Performance Modeling Using a Combination of
Interpolation and Self Organizing Approximation Techniques", IEEE Proc. ISCAS'90, New Orleans, May,
1990.
ICCAD91, Pages 176-179
Delay Computation in Combinational Logic Circuits: Theory and Algorithms
Srinivas Devadas
Kurt Keutzer
Sharad Malik
MIT
Cambridge, MA
Synopsys
Mountain View, CA
Princeton University
Princeton, NJ
Abstract
It is well known that using the length of the topologically longest path as an estimate of circuit
delay may be pessimistic since this path may be false. This paper presents the theory and
algorithms for delay analysis that ignores these false paths. Unlike previous work in this area,
these algorithms do not require explicit path enumeration.
References
[1] D. B. Armstrong. On finding a nearly minimal set of fault detection tests for combination logic nets. IEEE
Transactions on Computers, EC-15(2), February 1966.
[2] R. Bergamaschi. The effects of false paths in high-level synthesis. In Proc. of the ICCAD, November 1991.
[3] H. C. Chen and D. H. Du. Path sensitization in critical path problem. In Proceedings, Tau 90: 1990 ACM
Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 1990.
[4] P. C. McGeer and R. K. Brayton. Integrating functional and temporal domains in logic design. Kluwer
Academic Publishers, 1991.
[5] J. P. Roth. Diagnosis of automata failures: A calculus and a method. IBM Journal of Research and
Development, 10:278-291, July 1966.
ICCAD91, Pages 180-183
Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions
Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli
University of California - Berkeley CA
Abstract
Functional analysis of paths through combinational logic circuits has recently emerged as a
critical problem in timing analysis and various forms of test generation. In this paper, we introduce an efficient method for generating the functional forms of path analysis problems. We
demonstrate that the resulting function is linear in the size of the circuit. The functions are then
tested f or satisfiability either using a Boolean network satisfiability algorithm suggested in [5] or
through the construction of BDD's [1]. The effectiveness of the proposed approach is shown for
timing analysis and robust path delay fault test generation. This method also holds promise for
both static and dynamic hazard analysis, and for test generation using all other delay fault
models, τ-irredundant fault models, and stuck-open fault models.
References
[1] K. Brace, R. Rudell, and R. Bryant. Efficient implementation of a BDD package. In The Proceedings of the Design
Automation Conference, pages 40-45, June 1989.
[2] D. Brand and V. Iyengar. Timing analysis using functional analysis. IEEE Transactions on Computers,
37(10):1309-1314, October 1988.
[3] S. Devadas and K. Keutzer. Necessary and sufficient conditions for robust delay-fault testability of combinational
logic circuits. In The Proceedings of the 6th MIT Conference on Advanced Research in VLSI, pages 221-238, April
1990.
[4] S. Devadas, K. Keutzer, and S. Malik. Path sensitization conditions and delay computation in combinational logic
circuit. In The Proceedings of the International Workshop on Logic Synthesis, May 1991.
[5] T. Larrabee. Efficient generation of test patterns using Boolean difference. In The Proceedings of the International
Test Conference, August 1989.
[6] C. Lin and S. Reddy. On delay fault testing in logic circuits. IEEE Transactions on Computer-Aided Design, C6(5):694703, September 1987.
[7] P. McGeer. On the interaction of functional and timing behavior of combinational logic circuits. Ph.D. Thesis,
University of California - Berkeley, November 1989.
[8] P. McGeer and R. Brayton. Provably correct critical paths. In The Proceedings of the Decennial Caltech VLSI
Conference, 1989.
[9] M. Schulz, K. Fuchs, and F. Fink. Advanced automatic test pattern generation techniques for path delay faults. In
The Proceedings of the International Fault Tolerant Computing Symposium, pages 44-51, June 1989.
[10] G. Smith. Model for delay faults based upon paths. In The Proceedings of the International Test Conference,
pages 342-349, August 1985.
ICCAD91, Pages 184-187
Performance Enhancement through the Generalized Bypass Transform
Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
EECS Dept., University of California, Berkeley
Sartaj K. Sahni
Dept. of CS, University of Florida
Abstract
Conventional methods of logic circuit acceleration assume the delay of the circuit is equal to
the delay of the longest path, and so act to reduce this quantity. In this paper, we introduce a
new method for the acceleration of general logic circuits based on the assumption that the
delay of a circuit is its longest sensitizable (non-false) path. Hence, we accelerate circuits not
by reducing path length but by making paths false. We prove that a circuit realizing any
function can be accelerated in this manner, give a general algorithm, and prove bounds on the
size of the gain expected.
References
[1] J. P. Fishbum. A depth-decreasing heuristic for combinational logic, or how to convert a ripple-carry adder into a
carry lookahead adder or anything in between. In Design Automation Conference, 1990.
[2] D. Hathaway, L. H. Trevillyan, C. L. Berman, and A. S. LaPaugh. Efficient techniques for timing correction. In
IEEE International Symposium on Circuits and Systems, 1990.
[3] John L. Hennessy and David A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann
Publishers, 1989.
[4] Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. Timing
optimization of combinational logic. In IEEE International Conference on Computer-Aided Design, 1988.
ICCAD91, Pages 188-191
Delay Optimization of Combinational Logic Circuits by Clustering and Partial Collapsing
Herve J. Touati, Hamid Savoj, Robert K. Brayton
Electrical Engineering and Computer Sciences Department, University of California, Berkeley, CA 94720, USA
Abstract
This paper proposes a new technology independent algorithm to minimize circuit delay. The
algorithm works in two steps. The first step performs a partial collapse of the circuit based on a
delay-driven clustering. The second step factorizes and simplifies the circuit without increasing
the number of levels of logic. The computational cost of the algorithm is dominated by the
simplification step. To estimate circuit delay, we use a state-of-the-art technology mapper,
incorporating fanout optimization and tree covering for delay minimization. On average over a
representative set of benchmarks, we obtain a delay reduction of 18% for an area increase of
11%.
References
[1] C. L. Berman, D. J. Hathaway, A. S. LaPaugh, and L. H. Trevillyan. Efficient techniques for timing correction. In
ISCAS, pages 415-419, 1990.
[2] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang. MIS: A multiple-level logic optimization
system. IEEE Transactions on Computer Aided Design, CAD-6(6):1062-1081, November 1987.
[3] K. C. Chen and S. Muroga. Timing Optimization for Multi-Level Combinational Networks. In Proceedings of the
27th ACM/IEEE Design Automation Conference, pages 339-344,1990.
[4] J. P Fishburn. A Depth-Decreasing Heuristic for Combinational Logic: or How to Convert a Ripple-Carry Adder
into a Carry-Lookahead Adder or Anything In-Between. In Proceedings of the 27th ACM/IEEE Design Automation
Conference, pages 361-364,1990.
[5] M. C. Golumbic. Combinatorial Merging. IEEE Transactions on Computers, 25(11):1164-1167, November 1976.
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[7] R. Lisanke. Logic Synthesis and Optimization Benchmarks User Guide Version 2.0. Technical report, MCNC, PO.
Box 12889, Research Triangle Park, NC 27709, December 1988.
[8] H. Savoj, H. Touati, and R. K. Brayton. Extracting Local Don't Cares for Network Optimization. In ICCAD-91 (in
this volume), November 1991.
[9] K. J. Singh, A. R. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli. Timing Optimization of Combinational
Logic. In ICCAD-88, pages 282--285. IEEE, 1988.
[10] I. E. Sutherland and R. F. Sproull. Logical Effort: Designing for Speed on the Back of an Envelope. In C. H.
Sequin, editor, Advanced Research in VLSI Conference. MIT Press, 1991.
[11] H. Touati. Performance-oriented Technology Mapping. PhD thesis, UC Berkeley, 1990. UCB/ERL M90/109.
[12] J. Vasudevamurthy and J. Rajski. A Method for Concurrent Decomposition and Factorization of Boolean
Expressions. In IEEE International Conference on Computer-AidedDesign, pages 510-513, November 1990.
[13] D. Wallace. High-Level Delay Estimation for Technology-Independent Logic Equations. In ICCAD, pages 188191,1990.
ICCAD91, Pages 194-197
DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits
Torsten Grüning, Udo Mahlstedt, Hartmut Koopmeiners
Institut für Theoretische Elektrotechnik Universität Hannover, Appelstr. 9A, W-3000 Hannover 1, Germany
Abstract
This paper presents an efficient algorithm for the generation of diagnostic test patterns which
distinguish between two arbitrary single stuck-at faults. The algorithm is able to extend a given
set of test patterns which is generated from the viewpoint of fault: detection to a diagnostic test
pattern set with a diagnostic resolution down to a fault equivalence class. The difficult problem
of identifying the equivalence of two faults - analogous to the problem of redundancy
identification in ATPG - has been solved The efficiency of the algorithm is demonstrated by
experimental results for a set of benchmark circuits. DIATEST, our implementation of the algorithm, either generates diagnostic test patterns for all distinguishable pairs of faults or identifies
pairs of faults as being equivalent for each of the benchmark circuits.
References
[1] Galey, J.M. et al: "Techniques for the diagnosis of switching circuit failures", IEEE Trans. Communications and
Electronics, Vol. 83, pp. 509-514, September 1964
[2] Kautz, WH.: "Fault Testing and Diagnosis in Combinational Digital Circuits", IEEE Trans. on Computers, pp. 352366, April 1968
[3] Chang, H.Y.: "A distinguishability criterion for selecting efficient diagnostic tests", Proc. Spring Joint Computer
Conference, pp. 529-534, 1968
[4] Su, S.Y.H., Cho, Y.C.: "A New Approach to the Fault Location of Cominational Circuits", IEEE Trans. on
Comput., Vol. C-21, No.1 , pp. 21-30, January 1972
[5] Breuer, MA., Friedman, A.D.: "Diagnosis & Reliable Design of Digital Systems", Computer Science Press, 1976
[6] Abramovici, M., Breuer, MA.: "Fault Diagnosis Based on Effect-Cause Analysis: An Introduction", Proc.17th
Design Automation Conference, pp. 69-76,1987
[7] Cox, H., Rajski, J.: "A Method of Fault Analysis for Test Generation and Fault Diagnosis", IEEE Trans. on
Computer-Aided Design, Vol. 7, No. 7, pp. 813-833,1988
[8] Roth, J.P. et al: "Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic
Circuits", IEEE Trans. on Electronic Computers, Vol. EC16, No. 5, pp. 567-580, October 1967
[9] Savir, J., Roth, J.P.: "Testing for, and Distinguishing between Failures", Proc. of the 12th Fault Tolerant
Computing Symposium, pp. 165-172, June 1982
[10] Camurati, P. et al: "A Diagnostic Test Pattern Generation Algorithm", Proc. of the International Test Conference,
pp. 52-58,1990
[11] Goel, P.: "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic", IEEE Trans. on
Comput., Vol C-30, No. 3, pp. 215-222,1981
[12] Sellers, E.F. et al: "Analyzing errors with the Boolean Difference", IEEE Trans. on Comp., Vol. C-17, No. 7, pp.
676-683,1968
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Vol. C-20, No. 11, pp. 1286-1293, November 1971
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[15] Fujiwara, H., Shimono, T.: "On the Acceleration of Test Generation Algorithms", Proc.13th Int. Symp. on Fault
Tolerant Computing, pp. 98-105,1983
[16] Kirkland, T., Mercer, M.R.: "A Topological Search Algorithm for ATPG", Proc. 24th Design Automation
Conference, pp. 502-508,1987
[17] Schulz, M.H., Auth, E.: "Advanced Automatic Test Pattern Generation and Redundancy Identification
Techniques", Proc.18th Int. Symp. on FTCS, pp. 30-35,1988
[18] Mahlstedt, U., Grüning, T., Daehn, W., Özcan, C.: "CONTEST: A Fast ATPG Tool for Large Combinational
Circuits", Proc. IEEE Int. Conf. on Computer Aided Design, pp. 222-225,1990
[19] Muth, P.: "A Nine-Valued Logic Model for Test Generation", IEEE Trans. Comput., Vol. C-25, pp. 630-636,1976
[20] Brglez, F. et al: "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran",
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1985
ICCAD91, Pages 198-201
Knowledge-Based Debugging of ASICs: Real Case Study and Performance Analysis
1
M. Marzouki1, F. L. Vargas1,2
TIM3/IMAG-INPG, 46 Av. Félix Viallet - 38031 Grenoble Cedex - France
2
Federal University of Rio Grande do Sul - Brazil
Abstract
Automatic prototype validation of VLSI circuits is achieved making a joint use of an
Electron-Beam Tester and a Knowledge-Based System.
The paper describes a real case study, as well as the analysis of the system performances.
References
[1]
G. Bourgeon, Electron-beam tester : a tool for VLSI components analysis, The Microelectronic
Engineering Journal,7, 2-4 (1987), 327-332.
[2]
J. P. Collin, D. Conard, B. Courtois, P. Denis & D. Savart, Failure analysis using e-beam, The
Microelectronic Engineering Journal, 12,1-4 (1990), 305-324.
[3]
S. Concina & N. Richardson, IDS 5000 : an integrated diagnostic system for VLSI, The
Microelectronic Engineering Journal, 7, 2-4 (1987), 339-342.
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S. Concina & N. Richardson, Workstation-driven e-beam prober,18th IEEE ITC, Washington,
Sep.1987, 554-560.
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S. Gorlich, H. Harbeck, P. Kebler, E. Wolfgang & K. Zibert, Integration of CAD, CAT and electronbeam testing for IC - internal logic verification, 18th IEEE ITC, Washington, Sep. 1987, 566-574.
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F. Komatsu, M. Miyoshi, T. Sano & K. Okumura, An electron beam test system linked with a CAD
database, The Microelectronic Engineering Journal,7, 2-4 (1987), 339-342.
[7]
N. Kuji & T. Tamama, An automated e-beam tester with CAD interface: FINDER, 17th IEEE ITC,
Washington, Sep.1986, 857-863.
[8]
M. Melgara, M. Battu, P. Garino, F. Boland, J. Dowe, M. Marzouki & Y. J. Vernay, Automatic
location of IC design errors using an electron beam system, 19th IEEE ITC, Washington, Sep. 1988, 898-907.
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M. Marzouki, J. Laurent & B. Courtois, Coupling ElectronBeam Probing with Knowledge-Based Fault
Localization, 22nd IEEE ITC, Nashville, Oct. 1991.
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M. Marzouki, J. Laurent & B. Courtois, A unified use of deep and shallow knowledge in an expert system
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Press, Paris, Apr. 1989,184-191.
ICCAD91, Pages 202-205
BETA : Behavioral Testability Analysis
Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab
Center for Reliable and High-performance Computing, Coordinated Science Laboratory, University of Illinois at
Urbana-Champaign, Urbana, Illinois 61801
Abstract
Testability measurement is crucial in test generation. In this paper an approach, Beta, for
computing testability is presented. This approach is based on analyzing the circuit's behavior
description Data Flow Graph (DFG). It first analyzes each path in the DFG to find the set of
paths to justify and propagate each data register. Then, register classification is followed to
diagnose every register's controllability and observability and classifies them into several
groups. For those most controllable and observable registers, unlike other testability measure
which computes only testability, Beta also tries to derive the exact sequence for justifying and
propagating each register. Register classification is also useful in pointing out hard-tocontrol
and hard-to-observe area of the circuit. This approach has been implemented in a computer
program and applied to several examples. These results are verified by a DFG-based test
generator and proven to be successful.
References
[1] L. Goldstein and E. Thigpen, "SCOAP:Sandia Controllability/Observability Analysis Program," Proc. of
DAC, pp. 190-196, June 1980.
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Intl. Symp. Fault Tolerant Computing, pp. 101-107, June 1976.
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CAMELOT Program," Proc. IEEE Int. Conf. Circuits Comput., pp. 1162-1165, October 1980.
[4] C.-H. Chen and P.R. Menon, "An Approach to Functional Level Testability Analysis," Proc. ITC, pp. 373380,1989.
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381-390,1989.
[6] S.B. Akers, "Binary Decision Diagram," IEEE Trans. Comp., Vol. C-27, No. 6, pp. 509-516,1987.
[7] C. Wu, "Test Generation for High Level Synthesis Circuits," Master Thesis, Department of Computer
Science, University of Illinois at UrbanaChampaign,1991.
[8] M. McFarland, A. Parker and R. Camposano, "The High-Level Synthesis of Digital System," Proc. IEEE, Vol.
78, No. 2, pp. 301-318,1990.
[9] M. McFarland, "Using Botton-Up Design Techniques in the Synthesis of Digital Hardware from Abstract
Behavioral Description," Proc. DAC, pp. 474-480,1986.
ICCAD91, Pages 208-211
Path Sensitization in Critical Path Problem
Hsi-Chuan Chen, David H.C. Du
Department of Computer Science, University of Minnesota, Minneapolis, MN 55455
Abstract
Since the delay of a circuit is determined by the delay of its longest sensitizable paths (such paths
are called critical paths), the problem of estimating the delay of a circuit is called critical path
problem. One important aspect of the critical path problem is to decide whether a path is
sensitizable. Several path sensitization criteria have been proposed in previously proposed critical
path algorithms. However, they are often presented in different forms and it is hard to compare
with each other. In this paper we propose a path sensitization criterion according to a general
framework. Other path sensitization criteria can also be presented in the same framework.
Therefore, they can be compared with each other.
References
[1] J. Benkoski and et al, Timing Verification Using Statically Sensitizable paths, IEEE
Transactions on Computer-Aided Design, cad-9 (1990), pp. 1073-1084.
[2] D. Brand and V. Iyengar, Timing Analysis using Functional Analysis, tech. report, IBM
Thomas J. Watson Research Center, 1986.
[3] H. Chen and D. Du, Path Sensitization in Critical Path Problem, in ACM International
Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 1990.
[4] D. Du, H. Yen, and S. Ghanta, On the General False Path Problem in Timing Analysis,
in 26th Design Automation Conference, 1989, pp. 560-566.
[5] K. Keutzer, S. Malik, and A. Saldanha, Is Redundancy Necessary to Reduce Delay?, in
27th Design Automation Conference, 1990, pp. 228-234.
[6] P. Mcgeer and R. Brayton, Efficient Algorithms for Computing the Longest Viable
Path in a Combinational Network, in 26th Design Automation Conference, 1989, pp. 561-567.
[7] S. Perremans, L. Claesen, and H. Deman, Static Timing Analysis of Dynamically
Sensitizable Paths, in 26th Design Automation Conference, 1989, pp. 568-573.
ICCAD91, Pages 212-215
FPD - An Environment for Exact Timing Analysis
João P. Silva, Karem A. Sakallah, Luis M. Vidigal
Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109-2122
Abstract
Precise timing analysis is a key step in the design of high-performance digital circuits. In this paper
we introduce a new circuit model that accurately represents the temporal behavior of
combinational circuits. This circuit model is the basis for the derivation of a new sensitizing
criterion which provides the necessary conditions for accurate timing analysis. We describe the
FPD timing analysis environment supported by the sensitizing criterion and present examples of its
application.
References
[1] J. Benkoski, E.V. Meersch, L. Claesen, and H. De Man. "Efficient Algorithms for Solving the False Path
Problem in Timing Verifiers". In ICCAD Proceedings, pages 24-28, 1987.
[2] D. Brand and V.S. Iyengar. "Timing Analysis Using Functional Relationships". In ICCAD Proceedings,
pages 126-129,1986.
[3] D.H.C. Du, S.H.C. Yen, and S. Ghanta. "On the General False Path Problem in Timing Analysis". In DAC
Proceedings, pages 555-559,1989.
[4] P. Goel. "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits". IEEE
Transactions on Computers, pages 215-222, March 1981.
[5] V.M. Hrapcenko. "Depth and Delay in a Network". Soviet Math. Dokl., pages 1006-1009,1978.
[6] N. Ishiura, M. Takahashi, and S. Yajima. "TimeSymbolic Simulation for Accurate Timing Verification of
Asynchronous Behavior of Logic Circuits". In DAC Proceedings, pages 497-502,1989.
[7] N.P. Jouppi. "TV: A nMOS Timing Analyzer". In Proceedings Third Caltech VLSI Conference, pages
71-85,1983.
[8] T.I. Kirkpatrick and N.R. Clark. "PERT as an Aid to Logic Design". IBM Journal on Research and
Development, pages 135-141, March 1966.
[9] P.C. McGeer.
"On the Interaction of Functional and Timing Behavior of Combinational
Logic Circuits". PhD thesis, Department of Electrical Engineering and Computer Sciences. University of California at Berkeley, 1989.
[10] T.M. McWilliams. "Verification of Timing Constraints on Large Digital Systems". In DAC Proceedings,
pages 139-147,1980.
[11] S. Perremans, L. Claesen, and H.De Man. "Static Timing Analysis of Dynamically Sensitizable Paths". In DAC
Proceedings, pages 568-573, 1989.
[12] J.P. Roth. "Diagnosis of Automata Failures: A Calculus and a Method". IBM Journal on Research and
Development, pages 278-291, July 1966.
[13] K.A. Sakallah, T.N. Mudge, and O.A. Olukotun. "checkTc and minTc: Timing Verification and Optimal
Clocking of Synchronous Digital Circuits". In ICCAD Proceedings, pages 552-555,1990.
[14] F.F. Sellers Jr., M.Y. Hsiao, and L.W. Bearnson. "Analyzing Errors with the Boolean Difference". IEEE
Transactions on Computers, C-17:676-683, July 1968.
[15] J.P. Silva, K.A. Sakallah, and L.M.Vidigal. "Exact Timing Analysis of Combinational Circuits". Technical
Report CSE-TR-103-91, University of Michigan, 1991.
ICCAD91, Pages 216-219
A New Approach to Solving False Path Problem in Timing Analysis
Shiang-Tang Huang, Tai-Ming Parng
Dept. of Electrical Engineering
National Taiwan University
Taipei, Taiwan, R.O. C
Jyuo-Min Shyu
Computer & Communication Research Labs.
Industrial Technology Research Institute
Hsinchu, Taiwan, R.O. C
Abstract
A new approach to solving the false path problem is proposed. The approach is based on an
extended Boolean Algebra and is capable of modeling the logic and timing behavior of logic
networks in terms of modified Boolean functions. By applying algebraic manipulations, our
approach can extract correct timing information such as path delays as well as the input vectors
to activate the sensitizable paths. The approach has been implemented and tested on ISCAS
benchmarks.
References
[1] R. B. Hitchcock, Sr., G. L. Smith, and D. D. Cheng, "Timing Analysis of Computer Hardware," IBM. J. Res.
Develop., vol. 26, no. 1, pp. 100-106, Jan. 1982.
[2] H.C. Yen, S. Ghanta, H.C. Du, "A Path Selection Algorithm for Timing Analysis," Proc. of 25th Design
Automation Conf., 1988.
[3] Steve H.C. Yan, David H.C. Du, S. Ghanta, "Efficient Algorithms for Extracting the K Most Critical Paths in
Timing Analysis," Proc. of 26th Design Automation Conf., 1989.
[4] Robert B. Hitchcock, Sr., "Timing Verification and the Timing Analysis Program," Proc. of 19th Design
Automation Conf., pp. 594-604, 1982.
[5] J. Benkoski, E. Vanden Meersch, L. Claesen, and H. De Man "Efficient Algorithms for Solving the False Path
Problem in Timing Verification," IEEE Inter. Conf. on Computer-Aided Design (ICCAD87), 1987.
[6] David H.C. Du, Steve H.C. Yen, and S. Ghanta "On the General False Path Problem in Timing Analysis," Proc.
of 26th Design Automation Conf., 1989.
[7] Daniel Brand, Vijay S. Iyengar, "Timing Analysis Using Functionsl Analysis," IEEE Tran. on Computers, VOL
37, NO. 10, Oct. 1988.
[8] Patrick C. McGeer, Robert K. Brayton, "Efficient Algorithms for Computing the Longest Viable Path in a
Combinational Network," Proc. of 26th Design Automation Conf., 1989.
[9] Patrick C. McGeer, Robert K. Brayton, "Timing Analysis in Precharge/Unate Networks," Proc. of 27th Design
Automation Conf., 1990.
[10] ISCAS-85 Benchmarks, Special Session: Recent Algorithms for Gate Level ATPG with Fault Simulation and
Their Performance Assessment, IEEE International Symposium on Circuits and Systems, June 1985.
ICCAD91, Pages 222-225
State Assignment Based on the Reduced Dependency Theory
and Recent Experimental Results
C. Duff and G. Saucier
Institut National Polytechnique de Grenoble / CSI 46, av Felix Viallet - 38031 Grenoble Cedex - FRANCE
Abstract
The first step of this state assignment method recognizes predictive minimization situations
in the control flow graph. It is based on the partition pair theory and priviledges the cube
collapsing in the next state and output equations with regards to factorization. The second
step uses a powerful intersecting face embedding theory in the Boolean lattice [12].
References
[1] D.B. Armstrong: "A programmed algorithm for assigning internal codes to sequential machines", IRE
Transactions on Electronic Computers, pp 466-472, August 1962.
[2] C.N. Liu: "A State Variable Assignment Method for Asynchronous Sequential Switching Circuits", ACM,
April 63
[3] G. Saucier: "Encoding of Asynchronous Sequential Networks", IEEE Transactions on Electronic Computers
vol 16 pp 365-369
[4] G. Saucier: "State Assignment of Asynchronous Sequential Machines using Graph Techniques", IEEE
Transactions on Computers, vol. C-21, No. 3, pp. 282-288, March 1972.
[5] G. Saucier: "Next State Equations of Asynchronous Sequential Machines", IEEE Transactions on Computers,
November 1972.
[6] G. de Micheli, R.K. Brayton, A. SangiovanniVincentelli: "Optimal State Assignment of Finite State
Machines", IEEE Transactions on CAD, pp 269-284, July 1985
[7] S. Devadas, H. T. Ma, R. Newton, A. SangiovanniVincentelli: "MUSTANG: State Assignment of Finite State
Machines for Optimal Multi-Level Logic Implementations", ICCAD 87, pp 16-19, Santa Clara, November 1987
[8] B. Lin and A.R. Newton: "Synthesis of Multiple-Level Logic from Symbolic High Level Description
Languages", VLSI'89 Conference, Munich, pp 187-196, August 1989
[9] T. Villa, A. Sangiovanni-Vincentelli: "NOVA: State Assignment of Finite State Machines for Optimal TwoLevel Logic Implementations", 26th Design Automation Conference, Las Vegas, pp 327-332, June 1989
[10] G. Saucier, C. Duff, F. Poirot: "State Assignment Using a New Embedding Method Based on an Intersecting
Cube Theory", 26th Design Automation Conference, Las Vegas, pp 321-326, June 1989
[11] J. Hartmanis, R.E. Stearns: "Algebraic structure, Theory of Sequential Machines", Prentice Hall, 1666.
[12] C. Duff "Codage d'automates et théorie des cubes intersectants", INPG, PhD thesis in Microelectronics,
March 1991.
ICCAD91, Pages 226-229
A Flexible Scheme for State Assignment Based on Characteristics of the FSM
Biswadip Mitra, Preeti Ranjan Panda
Texas Instruments (India) Ltd.
71 Miller Road, Bangalore-560052, India.
P Pal Chaudhuri
Dept. of Computer Science,
Indian Inst. of Tech., Kharagpur-721302, India
Abstract
In this paper, a scheme has been described to perform state assignment based on FSM properties.
We use one of four state assignment techniques (that we have designed) which best suits the
given FSM. The selection of one of these techniques is done automatically by the system. An
option is provided to further optimize the generated solution using simulated annealing. Results
(on MCNC benchmarks) Indicate that the flexible methodology for state assignment, leads to
area and delay values that are better in most cases than existing state assignment schemes.
References
1. Biswadip Mitra and P Pal Chaudhuri, "State assignment of FSMs using a Cellular Automata based approach",
presented in CompEuro'91, May'91, Milan, Italy.
2. W. Pries, A. Thanailakis, and H.C. Card, "Group properties of cellular automata and VLSI applications," IEEE
Trans, Computers, vol. C-35, pp.1013-1024, Dec1986.
3. S. Devadas, H.-K. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli, "MUSTANG: State Assignment of
Finite State Machines Targeting Multi-Level Logic Implementations," IEEE Traps. CAD, vol. CAD-7, pp.12901300, Dec 1988.
4. R. K.Brayton, R.Rudell, A. Sangiovanni-Vincentelli, and A.Wang,"MIS: A multiple level logic optimization
system," IEEE Trans, Computer-Aided Design. vol. CAD-6, Nov. 1987.
5. Biswadip Mitra et al, "State assignment of sequential machines using a simulated annealing approach", in Int'I
conference on VLSI design Dec90.
6. Biswadip Mitra, Susanta Misra and P Pal Chaudhuri, "A system for synthesis of sequential machines with
built-in testability", Proc. of CICC'91, pp. 11.4.1-11.4.4.
ICCAD91, Pages 230-233
Encoding Multiple Outputs for Improved Column Compaction
David Binger and David W. Knapp
Department of Computer Science, University of Illinois
Abstract
In designing a digital circuit it is often necessary to convert a function with symbolic inputs
and outputs into a binary function. In such encoding problems, the input is a multiple-valued
logic function, whose symbolic values must be replaced by binary codes to produce the
corresponding binary function. The goal of an encoding problem is to find an encoding which
is optimal for some objective. In previously studied encoding problems (such as state
assignment), the objective is to find an encoding such that the binary logic function has a cover
with a minimal number of product terms, and hence a PLA implementation has a minimal
number of rows. In this paper, we introduce EP1, a new encoding problem where the objective
is to find an encoding so that the binary logic function has a minimal number of outputs after
column Compaction (as defined in [11]). Whereas state assignment is restricted to functions
which have only one multiple-valued output variable (the next state variable), EP1 is important
for functions which have many multiple-valued output variables: for example, control stores
and other components of finite state machines which often occupy large fractions of the total
chip area. This is particularly useful in high-level synthesis, where datapath components can
often be reallocated or resynthesized to accept arbitrary or near arbitrary control codes. A
heuristic solution to EP1 is given, and experimental results are provided.
References
[1] Frank Buijs and Thomas Lengauer. Synthesis of Multi-Level Logic with one Symbolic Input. In EDAC-91,
pages 60-64,1991.
[2] S. Devadas and A. R. Newton. Exact Algorithms for Output Encoding, State Assignment, and Four-Level
Boolean Minimization. IEEE Transactions on CAD, 10(1):13-27, January 1991.
[3] X. Du, G. Hachtel, B. Lin, and A. R. Newton. MUSE: A MUltilevel Symbolic Encoding Algorithm for State
Assignment. IEEE Transactions on CAD, 10(l):28-38, January 1991.
[4] J. R. Egan and C. L. Liu. Optimal Bipartite Folding of PLAs. In 19th Design Automation Conference, pages
141-146,1982.
[5] Michael R. Garey and David S. Johnson. Computers and Intractability: A Guide to the Theory o f NPCompleteness. W. H. Freeman and Company, 1979.
[6] Gary D. Hachtel, Arthur Richard Newton, and Alberto L Sangiovanni-Vincentelli. An Algorithm for Optimal
PLA Folding. IEEE Transactions on CAD, CAD-1(2):63-77, April 1982.
[7] Bill Lin and A. Richard Newton. Synthesis of Multiple Level Logic from Symbolic High-Level Description
Languages. In G. Musgrave and U. Lauther, editors, VLSI 89, pages 187-196. Elsevier Science Publishers B.V.
(North-Holland), 1990.
[8] Giovanni De Micheli, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. Optimal State Assignment for
Finite State Machines. IEEE Transactions on CAD, CAD-4(3):216-285, July 1985.
[9] Alexander Saldanha and Randy H. Katz. PLA Optimization Using Output Encoding. In ICCAD-88, pages 478481,1988.
[10] Tiziano Villa and A. Sangiovanni-Vincentelli. NOVA: State Assignment of Finite State Machines for Optimal
Two-Level Logic Implementation. IEEE Transactions on CAD, 9(9):905-924, September 1990.
[11] Ruey-Sing Wei and Chia-Jeng Tseng. Column Compaction and Its Application to The Control Path Synthesis.
In ICCAD-87, pages 320-323,1987.
[12] S. Yang and M. J. Ciesielski. Optimum and Suboptimum Algorithms for Input Encoding and Its Relationship to
Logic Minimization. IEEE Transactions on CAD, 10(l):4-12, January 1991.
ICCAD91, Pages 236-239
Synthesis of optimal 1-hot coded on-chip controllers for BIST hardware
D. Mukherjee, C. Njinda and M. A. Breuer
Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA 90089-0781
Abstract
We present a procedure for merging on-chip controllers for BIST circuitry to reduce
hardware overhead. Instead of starting with one minimal state assignment and then
performing state, input and output encoding, we pick the 1-hot code state assignment and
implicitly search the space of minimum prime compatible state covers to obtain an
optimal merged controller. This procedure uses knowledge of the greatest lower bounds
on states, arcs, next-state and the output logic of the merged controller to prune the
search space.
References
[1] M. S. Abadir and M. A. Breuer. A knowledge based system for designing testable VLSI chips. IEEE Design and
Test of Computers, pages 56-68, August 1985.
[2] R. K. Brayton, G. D. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for
VLSI Synthesis. Kluwer Academic, Boston, MA, 1984.
[3] R Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. MIS: A multiple-level logic optimization system.
IEEE Trans. Computer-Aided Design, pages 1062-1081, November 1987.
[4] A. D. Friedman and P. R. Menon. Theory and Design of Switching Circuits. Computer Science Press, 1975.
[5] S. Devadas, H. K. T. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli. Mustang: State assignment of finite state
machines targeting multi-level logic implementations. IEEE Trans. Computer-Aided Design, pages 1290-1300,
December 1988.
[6] D. Mukherjee, C. Njinda, and M. A. Breuer. Synthesis of optimal 1-hot coded on-chip controllers for BIST
hardware. Technical Report CENG 91-20, University of Southern California, 1991.
ICCAD91, Pages 240-243
BISTSYN - A Built-In Self-Test Synthesizer
Chien-In H e n r y Chen.
Department of Electrical Engineering, Wright State University, Dayton, OH 45435
Abstract
This paper presents a unifying procedure, called Three-Phase Cluster Partitioning, for automated
synthesis of pseudo-exhaustive test generator for Built-In Self Test (BIST) design. The
procedure minimizes the number of test patterns that are required for pseudo-exhaustive testing.
The design generator named BISTSYN, based on Three-Phase Cluster Partitioning algorithm,
was developed and implemented to facilitate the BIST design with this methodology. The input
to the design generator can be a circuit description at the gate level which is viewed as a netlist
or the circuit output functional dependency sets. BISTSYN provides the BIST mechanisms as the
output. The hierarchical design procedure is computationally efficient and produces test
generation circuitry with lower hardware overhead and fewer pseudo-exhaustive test patterns
than existing techniques.
References
[1]
Z. Barzilai, J. Savir, G. Markowsky, and M. G. Smith, "The Weighted Syndrome Sums Approach to VLSI
Testing", IEEE Trans. on Comp., vol. C-29, pp. 1012-1013, Nov. 1981.
[2]
E. J. McCluskey, "Verification Testing - A Pseudoexhaustive Test Technique", IEEE Trans. on Computers,
vol. C-33, No. 6, June 1984.
[3]
S. B. Akers, "On the Use of Linear Sums in Exhaustive Testing", Proc. 15th Fault Tolerant Comp. Symp.,
pp. 148-153, June 1985.
[4]
N. Vasanthavada and P. N. Marinos, "An Operationally Efficient Scheme for Exhaustive Test-Pattern
Generation Using Linear Codes", Proc. 1985 IEEE Test Conf., pp. 476-482, 1985.
[5]
L. T. Wang and E. J. McCluskey, "Condensed Linear Feedback Shifter Register (LFSR) Testing - A
Pseudoexhaustive Test Technique", IEEE Trans. on Computers, vol. C-35, No. 4, 1986.
[6]
L. T. Wang and E. J. McCluskey, "Circuits for Pseudoexhaustive Test Pattern Generation", Proc. 1986
IEEE Test Conf., pp. 25-37, 1986.
[7]
W. W. Peterson and E. J. Weldon, Jr., Error Correcting Codes, 2nd Edition, M.I.T. Press, 1972.
[8]
C.-I. H. Chen and G. Sobelman, "An Efficient Approach To Pseudo-Exhaustive Test Generation For BIST
Design," Proc. of IEEE International Conference on Computer Design, pp. 576579, 1989.
[9]
F. Brglez, P. Pownall and R. Hum, "Accelerated ATPG and fault grading via testability analysis", Proc.
1985 IEEE Int. Symp. Circuits and Systems, pp. 695-698, 1985.
ICCAD91, Pages 244-247
Comparison of Random Test Vector Generation Strategies
Warren H. Debany, Jr., Pramod K. Varshney, Kishan G. Mehrotra
Syracuse University, Syracuse NY 13244
Carlos R.P. Hartmann
Rome Laboratory (RL/ERDA), Griffiss AFB NY 13441
Abstract
Four random test generation strategies are compared to determine their relative effectiveness:
equiprobable 0s and 1s; two weighted random pattern generation algorithms; and the
maximum output information entropy principle. The test generation strategies are compared
at a variety of target fault coverages. Two statistically-based metrics are used to evaluate the
techniques: a large-sample test of the difference of means and an upper confidence limit. The
two weighted random test pattern generation strategies are found to be generally superior to
equiprobable 0s and 1s and maximum output entropy. For a given logic circuit, the same
technique is not necessarily optimal at every fault coverage.
References
[1] P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI. Pseudorandom Techniques, NY: John Wiley
& Sons, 1987, pp 216-225.
[2] E.B. Eichelberger, R.N. Langmaid, E. Lindbloom, F. Motika, J.L. Sinchak, and J.A. Waicukauski, "Weighted
random pattern testing apparatus and method," US Patent 4,687,988, 1987.
[3] V.D. Agrawal, "An information theoretic approach to digital fault testing," IEEE Transactions on Computers,
August 1981, pp 582-587.
[4] S.C. Seth and V.D. Agrawal, "Statistical design verification," Proceedings, Fault Tolerant Computing
Symposium, 1982, pp 393-399.
[5] The T TL Data Book for Design Engineers, 2nd Ed., Texas Instruments (TI), 1976.
[6] F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in
FORTRAN," Proceedings, International Symposium on Circuits and Systems (IS CA S), 1985.
[7] M.H. Schulz and E. Auth, "Advanced automatic test pattern generation and redundancy identification
techniques," Proceedings, Fault Tolerant Computing Symposium, 1988, pp 30-35.
[8] W. Mendenhall, Introduction to Probability and Statistics, North Scituate, MA: Duxbury Press, 5th ed., 1979.
[9] A.J. Duncan, Quality Control and Industrial Statistics, 5th ed., Homewood, IL: R.D. Irwin, 1986.
ICCAD91, Pages 248-251
Built-In Self-Test For Multi-Port RAMs
V. Castro Alves*, M. Nicolaidis*, P. Lestrat** and B. Courtois* *
*Reliable Integrated Systems Group, IMAG/TIM3 Laboratory, 46, av. Felix Viallet
38031 Grenoble Cedex -France
** Thomson Composants Militaires Et Spatiaux, BP 123 38521 St Egreve Cedex - France
Abstract
In this paper we present a new approach to the test of multi-port RAMs. A new fault model
that takes into account complex couplings resulting from simultaneous access of memory cells
is used in order to ensure a very high fault coverage. A new algorithm for the test of dual-port
memories is here detailed. This algorithm achieves 0(n) complexity thanks to the use of some
topological restrictions. We also present a new BIST scheme, based on programmable
schematic generators, that allows great flexibility for ASIC design.
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ICCAD91, Pages 254-257
The Hercules CAD Task Management System
Jay B. Brockman and Stephen W. Director
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
Abstract
We introduce a new information model for CAD task management, called the Task Schema, that
unifies many of the requisite features for data, process and methodology management into a
single, concise representation. The task schema based approach has been implemented in the
Hercules Task Management System.
References
[1] W.Allen, D.Rosenthal, and K.Fiduk. "Distributed Methodology Management for Design-in-the-Large." In
Proceedings of the IEEE International Conference on Computer-Aided Design, IEEE, 1990, pages 346--349.
[2] F.Bretschneider, C.Kopf, H.Lagger, A.Hsu, and E.Wei. "Knowledge Based Design Flow Management." In
Proceedings of the IEEE International Conference on Computer-Aided Design, IEEE, 1990, pages 350--353.
[3] M.Bushnell and S.W. Director. "Automated Design Tool Execution in the Ulysses Design Environment,"
IEEE Transactions on Computer-Aided Design, 8(3):279--287, March 1989.
[4] P.Chen. "The Entity-Relationship Model--Toward a Unified View of Data," ACM Transactions on Database
Systems, 1(1):9--36, March 1976.
[5] T.Chiueh and R.Katz. "A History Model for Managing The VLSI Design Process." In Proceedings of the IEEE
International Conference on Computer-Aided Design, IEEE, 1990, pages 358--361.
[6] J.Daniell and S.W. Director. "An Object Oriented Approach to CAD Tool Control within a Design Framework." In Proceedings of the 26th ACM/IEEE Design Automation Conference, ACM Press, 1989, pages 197--202.
[7] D.Harel. "On Visual Formalisms," Communications of the ACM, 31(5):514--530, May 1988.
[8] D.Harrison, A.Newton, R.Spickelmier, and T.Barnes. "Electronic CAD Frameworks," Proceedings of the
IEEE, 78(2):393--417, February 1990.
[9] K.K. Low and S.W. Director. "An Efficient Macromodeling Approach for Statistical IC Process Design." In
Proceedings of IEEE International Conference on Computer-Aided Design, IEEE, 1988, pages 16--19.
[10] T.Miyazaki, T.Hoshino, and M.Endo. "A CAD Process Scheduling Technique." In Proceedings of the IEEE
International Conference on Computer-Aided Design, IEEE, 1990, pages 354--357.
[11] P.van den Hamer and M.A. Treffers. "A Data Flow Based Architecture for CAD Frameworks." In
Proceedings of the International Conference on Computer-Aided Design, IEEE, 1990, pages 482--485.
ICCAD91, Pages 258-261
The Configuration Management for Version Control
in an Object-Oriented VHDL Design Environment
Moon Jung Chung and Sangchul Kim
Department of Computer Science, Michigan State University, E. Lansing, MI 48824
Abstract
This paper presents a constraint-driven, object-oriented approach to configuration management
within a VHDL design environment called SDE. A configuration is generated from a generic
design in a way that technology-specific cells are bound to the generic components of the design.
In our approach, user-defined constraints are exploited to efficiently organize versions and to
generate workable configurations. They are also used for providing the formal definitions of
various relationships between cells, enabling us to easily explore versions of a configuration by
substituting other cells with a certain relationship, e.g. replaceability, for its already bound cells.
To retrieve cells that satisfy constraints for a configuration to be generated, we suggest an objectoriented query model based on a graph model.
References
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VHDL Design Environment," Technical Report, Department of Computer Science, MSU.
[8] S. Kim and M. J. Chung, "A Constraint-Driven Approach to Configuration Binding in an Object-Oriented
VHDL Design Environment," submitted to CHDL91,1991.
[9] J.A. Darringer, D.Band, J.V.Gerbi, W.H.Joyner Jr. and L Trevillyan, "LSS: A System for Production Logic
Synthesis," IBM J. Research & Development," Vol. 28, No. 5.
[10] Katz, R.H. Bhateja, R., Chang, E.E., Gedye, D., Trijanto, V., "Design Version Management", IEEE Design and
Test, pp12-22,1987.
[11] Joseph S. Lis and Daniel D. Gajski, "Synthesis From VHDL," ICCAD-88, p378-p381,1988.
[12] Liu, L.-C, Wu, P.-C. and W. C.-H., "Design Data Management in a CAD Framework Environment,"
Proceedings of 27th DAC, p156-p161,1990
[13] Siepmann, E., and Zimmermann, G., "An Object-Oriented Data Model for the VLSI Design System
PLAYOUT," Proceedings of 26th Design Automation Conf., 1989, p814p817.
[14] Wayne H. Wolf, "How to Build a Hardware Description and Measurement System on an Object-Oriented
Programming Language," IEEE CAD, Vol. 8, No. 3, p288-p301,1989.
[15] P. van der Wolf and T.G.R. van Leuken, "Object-Type Oriented Data Modeling for VLSI Data Management,"
Proceedings of 25th DAC, p351-p356.
ICCAD91, Pages 262-265
SADE: A Graphical Tool for VHDL-based System Analysis
Jukka Lahti, Matti Sipola, Jorma Kivelä
University of Oulu, Department of Electrical Engineering, Electronics Laboratory, SF-90570 Oulu, Finland
Abstract
A graphical tool for system analysis is described. The tool can generate behavioral VHDL
models from graphical, Structured Analysis (SA) diagrams. The models can be simulated on a
standard VHDL simulator. The simulation results can be viewed animated in the graphical
diagrams. The tool provides the designer with features found in sophisticated CASE tools, which
make the construction of a system model, and the analysis of simulation results easy
References
[1] IEEE Standard VHDL Language Reference Manual
[2] Ward, PT. and Mellor, S.J.: "Structured Development for Real-Time Systems", vol. 1-3, Yourdon Press, N.Y,
19851986
[3] Oman, PW.: "CASE Analysis and Design Tools", IEEE Software, Vol 7, No 3, May 1990, pp. 37 - 43.
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Timing", IEEE Trans. on Software Engineering, Vol 12, No 2,1986, pp. 198210.
[5] Peterson, J.L.: "Petri Net Theory and the Modeling of Systems", Prentice Hall, 1981
[6] Razouk, R.R.: "The Use of Petri Nets for Modeling Pipelined Processors", Proc. of the 25th Design Automation
Conference, ACM/IEEE,1988.
[7] Kivelä, J et al.: "VHDL Supported by Graphical CASEtools.", Proc. EUROVHDL `90, Vol. 1, Marseile, France,
1990.
[8] Sipola, M. et al.:"Systems Real-time Analysis with VHDL Generated from Graphical SA-VHDL", Proc.
EUROVHDL `91, Stockholm, Sweden, 1991.
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[10] Lahti, J.: "Logic Compilation From Graphical Dependency Notation", Proc. of ICCAD-90, pp. 474-477, IEEE,
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ICCAD91, Pages 266-269
System Specification and Synthesis with the SpecCharts Language
Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
Department of Information and Computer Science, University of California, Irvine, CA, 92717
Abstract
There is a need for capturing behavioral specifications of entire systems and obtaining
multi-chip designs from those specifications. We discuss system level specification and
synthesis issues, along with the unique requirements they place on a specification
language. Since no current language meets those requirements, the SpecCharts language
was created on top of VHDL. Its model and constructs permit capturing system
specifications simply and precisely, while aiding synthesis.
References
[1] IEEE Standard VHDL Language Reference Manual, 1988.
[2] E. Sternheim, R. Singh and Y. Trivedi, "Hardware Modeling with Verilog HDL." Automata Publishing Co.,
1990.
[3] D. Harel et al, "STATEMATE : A Working Environment for the Development of Complex Reactive
Systems," in Proc. of the Intl. Conf. on Software Engineering, 1988.
[4] E. Lee, et al, "Gabriel: A Design Environment for Programmable DSP's," in Proc. of the 26th DAC,1989.
[5] W. Birmingham, A. Gupta and D. Siewiorek, "The MICON System for Computer Design," in Proc. of the
26th DAC, 1989.
[6] F. Vahid, S. Narayan, D. Gajski, "SpecCharts : A Lanuage for System Level Synthesis," in Proc. of the 10th
Intl. Symp. on Computer Hardware Description Languages, 1991.
[7] D. Harel, " Statecharts : A Visual Formalism for Complex Systems," Science of Computer Programming 8,
1987.
[8] G. Micheli and D. Ku "HERCULES - A System for High-Level Synthesis," in Proc. of the 25th DAC, 1988.
[9] C. Hoare "Communicating Sequential Processes," Comm. of the ACM, August 1978.
[10] S. Narayan, F. Vahid, and D. Gajski, "Modeling With SpecCharts." UC Irvine, TR 90-20, July 1990.
[11] S. Narayan, F. Vahid and D. Gajski, "Translating System Specifications to VHDL," in Proc. of the
European Conference on Design Automation, 1991.
[12] Intel Peripheral Design Handbook, 1981.
[13] J. Lis and D. Gajski, "Synthesis from VHDL " in Proc. of the International Conference on Computer
Design, 1988.
ICCAD91, Pages 272-275
Compiling Multi-dimensional Data Streams into Distributed DSP ASIC Memory
J. Vanhoof and I. Bolsens
IMEC
B-3001 Heverlee, Belgium
H. De Man
Katholieke Universiteit Leuven
B-3000 Leuven, Belgium
Abstract
State-of-the-art DSP algorithms include operations on multi-dimensional data
structures. In this paper we will demonstrate that, next to allocation and scheduling of data path operations, eff icient storage schemes and memory access are
crucial in DSP ASIC design. For complex, medium throughput DSP applications,
we have identified a strategy and important optimization tasks for compiling
multi-dimensional data structures into distributed dual-port register files and
single-port SRAMs. These techniques have been implemented in the
CATHEDRAL-II silicon compiler. Their applicability are demonstrated with the
design o f a vocoder chip featuring industrial complexity.
References
[1] P.N.Hilfinger et.al."DSP Specification Using the Silage Language," Proc. of ICASSP, Albuquerque,
New Mexico, April 1990.
[2] L.Nachtergaele et.al., "A Specification and Simulation Front-end for Hardware Synthesis of Digital
Signal Processing Applications," accepted for publication in Int. Journal of Computer Simulation.
[3] A.Delaruelle et.al., "Synthesis of Delay Functions in DSP Compilers," Proc. of EDAC90, Edinburgh.
[4] I.Verbauwhede et.al., "Background memory management for the synthesis of algebraic algorithms on
multiprocessor DSP chips," Proc. of the VLSI'89 Conference, Munich, August 1989.
[5] J.Rabaey et.al., "CATHEDRAL II: Computer Aided Synthesis of Digital Signal Processing Systems,"
Proc. IEEE Custom Integrated Circuits Conf., Portland OR, pp.157-180, May 1987.
[6] D.M.Grant et.al., "Address Generation for Array Access Based on Modulus m Counters," Proc. of
EDAC, Amsterdam, Feb. 1991, pp. 118-122.
[7] P.Lippens et.al., "PHIDEO: A Silicon Compiler for High Speed Algorithms," Proc. of EDAC 91,
Amsterdam.
[8] T.C.Hu, "Combinatorial Algorithms," Addison-Wesley, 1982, pp. 209-222.
[9] A.V.Aho, J.D.Ulmann, "Principles of Compiler Design," Addison-Wesley, 1977.
ICCAD91, Pages 276-279
Post-Processor For Data Path Synthesis Using Multiport Memories
Imtiaz Ahmad and C. Y. Roger Chen
Department of Electrical and Computer Engineering, Syracuse University, Syracuse, NY 13244
Abstract
A novel design methodology for data path synthesis using multiport memories is presented which
can be applied to scheduled algorithms or to already synthesized data path as a post-processor to
reduce the design space. Based on simple and clear, but powerful principles, the proposed technique not only groups variables to a minimum number of multiport memories depending upon their
ports and taking into consideration the variables access requirements, but also minimizes their
interconnection hardware (such as buses, multiplexers and tri-state buffers) to functional units. The
system, MAP, supports the synthesis of architecture in both linear topology and random topology
for the application specific design. The minimization problems have been formulated as 0-1 integer
linear programming (ILP) problems. Experiments on benchmarks show very promising results and
the CPU time for all the benchmarks is less than 1.4 seconds.
References
[1] M. C. McFarland, A. C. Parker, and R. Camposano, "The High-Level Synthesis of Digital Systems," Proc. of
IEEE, vol. 78, no. 2, pp. 301-318, Feb. 1990.
[2] C-J. Tseng and D. P. Siewiorek, "Automated Synthesis of Data Path in Digital Systems," IEEE Trans. on
CAD, vol. CAD-5, no. 3, pp. 379-395, Jul. 1986.
[3] P. G. Paulin and J. P. Knight, "Scheduling and Binding Algorithms for High-Level Synthesis," 23rd
ACM/IEEE Design Automation Conference, pp. 1-6, Jun. 1989.
[4] B. S. Haroun and M. I. Elmasry, "Architectural Synthesis for DSP Silicon Compiler," IEEE Trans. on CAD,
vol. CAD-8, no. 4, pp. 431-447, Apr. 1989.
[5] F. S. Tsai and Y. C. Hsu, "Data Path Construction and Refinement," IEEE International Conference on
Computer-Aided Design, ICCAD-90, pp. 308-311.
[6] C. A. Papachristou and H. Konuk, "A Linear Program Driven Scheduling and Allocation Method Followed by
an Interconnect Optimization Algorithm," 27th ACM/IEEE Design Automation Conference, pp. 77-83, Jun.
1990.
[7] H. Shinohara et al., "A Flexible Multiport RAM Compiler for Data Path," IEEE J. of Solid-State
Circuits, vol. 26, no. 3, Mar. 1991.
[8] K. Endo, T. Matsumura and J. Yamada, "Pipelined, Time-Sharing Access Technique for an Integrated Multiport Memory," IEEE J. of Solid-State Circuits, vol. 26, no. 4, Apr. 1991
[9] P. Marwedel, "The MIMOLA Design System: Tools for the Design of Digital Processors," 21st ACM/IEEE
Design Automation Conference, pp. 587-593, Jun. 1984.
[10] M. Balakrishnan, A. K. Majmudar, D. K. Banerji, J. G. Linders and J. C. Majithia, "Allocation of Multiport
Memories in Data Path Synthesis," IEEE Trans. on CAD, vol. 7, no. CAD-4, pp. 536-540, Apr. 1988.
[11] "LINDO: Linear Interactive and Discrete Optimizer for linear, integer, and quadratic programming problems," LINDO Systems Inc. no. 2, Feb. 1989.
ICCAD91, Pages 280-283
Clustering Techniques for Register Optimization during Scheduling Preprocessing
F. Depuydt, G. Goossens, H. De Mart
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Abstract
In this paper, a preprocessing technique for scheduling o f large hierarchical and conditional
DSP applications on a multi register file architecture is described. Its goals are the optimization
of the register cost and the reduction of the time complexity of complex scheduling techniques.
These are both achieved by reducing the operation mobility through hierarchical clustering.
The metric used in the clustering process is a multidimensional distance vector, based on a
hierarchical and multi-dimensional extension o f the min-flow algorithm.
References
[1] Raul Camposano and Reinaldo A. Bergamashi. Synthesis using path-based scheduling: algorithms and exercises.
In Proc. of the HLSW, November 1989.
[2] F. Depuydt et. al. Scheduling of large signal flow graphs based on metric graph clustering. In Proc. of IFIP90,
Paris, Elsevier Publishers, 1990.
[3] Shimon Even. Graph Algorithms. Computer Science Press, 1979.
[4] G. Goossens et. al. An efficient microcode compiler for application specific dsp processors. IEEE Trans. on
Computer-Aided Design, 9(9):925-937, September 1990.
[5] Paul N. Hilfinger et.al. DSP specification using the Silage language. In Proc. ICASSP90, Albuquerque NM,
April 1990.
[6] Stephen C. Johnson. Hierarchical clustering schemes. Psychometrika, 32(3):241-254, September 1967.
[7] D. Lanneer et. al. Open-ended system for high-level synthesis of flexible signal processors. In Proc. EDAC90,
Glasgow, March 1990.
[8] Jiahn-Hung Lee et. al. A new integer linear programming formulation for the scheduling problem in data path
synthesis. In Proc. ICCAD89, pages 20-23, Dept. Computer Science, Tsing Hua University, November 1989.
[9] Michael C. McFarland and Thaddeus J. Kowalski. Incorporating bottom-up design into hardware synthesis.
IEEE Trans. on Computer-Aided Design, 9(9):938-950, September 1990.
[10] Pierre G. Paulin and John P. Knight. Algorithms for high-level synthesis. IEEE Design & Test of Computers,
1831, December 1989.
ICCAD91, Pages 284-287
Scheduling in Programmable Video Signal Processors
G. Essink, E. Aarts, R. van Dongen, P. van Gerwen, J. Korst, K. Vissers
Philips Research, P.O. Box 80.000, 5600 JA Eindhoven, The Netherlands
Abstract
We discuss the problem of mapping algorithms for real-time processing of digital video signals
onto a fixed configuration of identical programmable video signal processors. Due to the periodic nature of the algorithms and the small periods that are involved, successive executions of
the algorithm have to be interleaved in time. The resulting scheduling problem is mathematically
modeled and examined. We present a novel solution approach that is based on a divide and
conquer strategy using phase assignment as the central part. This approach has been
implemented and it gives good results for industrially significant video applications.
References
[1] A.H.M. van Roermund et al., A General-Purpose Programmable Video Processor, IEEE Trans. on Consumer
Electronics, August 1989, 249.
[2] C.M. Huizer et al., A Programmable 1400 Mops Video Signal Processor, Proc. CICC, San Diego, CA, 1989,
24.3.1.
[3] H. Dijkstra et al., A General-Purpose Video Signal Processor: Architecture and Programming, Proc. ICCD,
Cambridge, MA, 1989, 74.
[4] K. Vissers et al., Programming and Tools for a general-purpose video signal processor, Fifth Int. Workshop on
HighLevel Synthesis, Buhlerhöhe, Germany, 1991, 169.
[5] J.H.M. Korst et al., Periodic Multiprocessor Scheduling, Proc. PARLE' 91, Springer LNCS, 505 (1991)166.
[6] M. Lam, Software Pipelining: An Effective Scheduling Technique for VLIW Machines, SIGPLAN-88 Conf. on
Programming Language Design and Implementation, Atlanta, GA, 1988, 356.
[7] E.A. Lee and D.G. Messerschmitt, Static scheduling of Synchronous Data Flow Graph for Digital Signal
Processing, IEEE Trans. on Computers, C-36(1987)24.
[8] D.A. Schwartz and T.P. Barnwell III, Cyclo-static Multiprocessor Scheduling for the Optimal Realization of
Shift-Invariant Flow Graphs, Proc. ICASSP, Tampa, FL, 1985, 1384.
[9] E.G. Coffman, Jr., M.R. Garey and D.S. Johnson, Approximation Algorithms for Bin-Packing - An Updated
Survey, in: Algorithm Design and Computer System Design, CISM Courses and Lectures 284, Springer, Vienna,
1984, 49.
[10] J. French, Sequencing and Scheduling: an Introduction to the Mathematics of the Job-Shop, J. Wiley & Sons,
NY, 1982, 177.
[11] E.L. Lawler, Combinatorial Optimization: Networks and Matroids, Holt, Rinehart and Winston, NY, 1976, 74.
[12] A. Gibbons, Algorithmic Graph Theory, Cambridge University Press, Cambridge, 1989, 195.
ICCAD91, Pages 290-293
Circuit Comparison by Hierarchical Pattern Matching
Georg Pelz, Uli Roettcher
Fraunhofer-Institute of Microelectronic Circuits and Systems, Finkenstr. 61, W-4100 Duisburg 1, Germany
Abstract
We present a new approach to circuit comparison and building-block recognition. In contrast
to conventional systems, netlist pattern matching is employed as the basic principle, allowing
to identify arbitrary subcircuits in larger circuits. Typically, a hierarchical netlist derived
from a schematic and a flat netlist extracted from a layout have to be compared. In our
approach, this is accomplished by the successive (bottom up) matching of the schematic cells
in the layoutnetlist, thus restoring the schematic hierarchy. The pattern matching algorithm is
embedded in a sophisticated hierarchy handling scheme, allowing to process even illstructured hierarchies. The method is independent from circuit technology and design style.
Typical drawbacks of traditional systems as the handling of parallel pathes or the
permutability of (groups of) terminals are overcome in a quite natural way. Additionally our
approach offers a universal and flexible solution to the problem of functional but not topological isomorphic subcircuits. Real-life examples prove its suitabiliy in function and
performance.
References
[1] Luellau, F., Hoepken, T. and Barke, E., "A technology independent block extraction algorithm", 21st Design
Automation Conference, 610 - 615, 1984.
[2] Nebel, W. and Hartenstein, R. W., "Functional design verification by register transfer net extraction from
integrated circuit layout data", COMPEURO, 254 - 257, Hamburg 1987.
[3] Takashima, M., Ikeuchi, A., Kojima, S., Tanaka, T., Saitou, T. and Sakata, J., "A circuit comparison system with
rule-based functional isomorphism checking", 25th Design Automation Conference, 512 - 516, 1988.
[4] Shiran, Y., "YNCC: a new algorithm for device-level comparison between two functionally isomorphic VLSI
circuits", Proc. of ICCAD, 298 - 301, 1986.
[5] Spickelmier, R.L. and Newton, A.R., "Connectivity verification using a rule-based approach", Proc. of ICCAD,
190 - 192, 1985.
[6] Ebeling, C., "GeminiII: a second generation layout validation program", Proc. of ICCAD, 322 - 325, 1988.
[7] U. Roettcher, J. Fritz, F. Krohm, G. Hess, "HIPARE: circuit and parameter extraction from mask layout data",
E S S CI R C D ig . o f T e c h n . P a pers, 217-219,1987.
[8] Jouppi, N.P., "Derivation of signal flow direction in MOS VLSI", IEEE Transactions on CAD, Vol. CAD-6,
No. 3, 480 - 490, May 1987.
ICCAD91, Pages 294-297
HIVE: An Efficient Interconnect Capacitance Extractor to Support
Submicron Multilevel Interconnect Designs
Keh-Jeng Chang, Soo-Young Oh, and Ken Lee
Hewlett-Packard Company Palo Alto, CA 94304, USA
Abstract
A new paradigm for efficiently providing 2-D and 3-D submicron multilevel (SMML) interconnect
capacitances to support VLSI/ULSI designs regarding RC-delay, electromigration, and crosstalk has
been developed. According to our SMML interconnect process measurements and simulations, when
the interconnect width/space changes, the corresponding changes of the ground and coupling
capacitances are linear in some cases and nonlinear in other cases. A set of representative SMML
layout structures are selected so that rigorous 2-D and 3-D simulations are done for the nonlinear
changes in advance, and fast interpolations/extrapolations are done for the linear changes when
circuit designers specify the width/space of interconnects. It is believed that EDA tools, such as logic
synthesizers, channel/area routers, and circuit extractors, can also take advantage of this algorithm.
The average time spent on X-window-based design curve generations is 1.4 seconds. The
computation time for each capacitance calculation is less than 100 microseconds. The maximal
difference between the interpolation/extrapolation results and the 2-D/3-D simulation results is
within 3%.
References
[Anna86] Marco Annaratone, Kluwer Academic Publishers, Norwell, MA, pp. 137-143,1986. [Cham88] Kit Cham,
Soo-Young Oh, et al., 2nd edition, Kluwer Academic Publishers, Norwell, MA, pp. 348-351,1988.
[Cott85] Peter E. Cottrell, et al., IBM J. Res. Develop., pp. 277-288, May 1985.
[LeCo9l] Yannick L. Le Coz, et al., Proceedings o f IEEE VMIC, pp. 364-366,1991.
[Lee89] Ken Lee, "Three Dimensional Modeling of Interconnect Capacitance and Inductance," Workshop on
Interconnect Modeling & Technology, IEEE Solid-State Circuits & Technology Committee, San Diego, May 1989.
[Meij89] N. P. van der Meijs, et al., Proceedings of 26th ACM/IEEE DAC, pp. 678-681, June 1989.
[Oh9l] Soo-Young Oh, Keh-Jeng Chang, and John L. Moll, Proceedings of IEEE VMIC, pp. 346-349, 1991.
[Saku83] T. Sakurai, et al., IEEE Trans. Electron Devices, pp. 183-185, Feb. 1983.
[Ushi88] Y. Ushiku, et al., Proceedings of IEEE IEDM, pp. 340-343,1988.
ICCAD91, Pages 298-301
Hierarchical analyzer for VLSI power supply networks
based on a new reduction method
Takeshi Yoshitome
NTT LSI Laboratories 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa, 243-01, Japan
Abstract
This paper presents an algorithm for hierarchical analysis of VLSI power supply
networks. The algorithm utilizes the design hierarchy and is independent of network
topology. Networks in each block are recursively reduced to equivalent and small
circuits in a bottom-up manner, and node voltages in the network are calculated in a
top-down manner. This allows to decrease the size of the matrix to be solved and to
reduce the execution time. Experimental results show that the factor of reduction in
matrix size is from 1/10 to 1/40 and execution is six times faster than with flat analysis.
References
[1] J. E. Hall, D. E. Hocevar, P. Yang, and M. J. McGraw. "SPIDER- A CAD System for Modeling VLSI
Metallization Patterns" in IEEE Trans. Computer-Aided Design, vol.CAD-6, no.6, pp.1023-1031, Nov, 1987
[2] An-Chang Deng,Yan-Chyuan Shiau, and Kou-Hung Loh. "Time domain current waveform simulation of CMOS
circuits" in IEEE Trans Computer-Aided Design, Tech. Papers, pp.208-211, Nov, 1988
[3] A Tyagi, "Hercules: A power analyzer for MOS VLSI circuits" Conf.Computer Aided Design Dig. Tech.
Papers, pp.530-533,Nov.1987
[4] F.Najm, R.Burch,"CREST - A current estimator for cmos circuits" Proc. Conf. Computer-Aided Design,
1988, pp.204-207
[5] D. Stark, M. Horowitz. "Analyzing CMOS Power Supply Networks using Ariel" Proc. Conf. Design
Automation, pp.460 -464, 1988
[6] D. Stark, M. Horowitz. "Techniques for Calculating Currents and Voltages in VLSI Power Supply Network"
IEEE Trans. Computer-Aided Design, vol.9, no.2, pp.126-132, Feb, 1990
ICCAD91, Pages 304-307
Automatic Detection of MOS Synchronizers for Timing Verification
Joel Grodstein, Nick Rethman, Rahul Razdan, and Gabriel Bischoff
SEG/CAD/CSV Group, Digital Equipment Corporation, Hudson, MA
Abstract
Static timing verifiers need to know at which points data is synchronized with clocks in a circuit.
Typically, this happens at latches and in clock qualification gates. However, in a general, fullcustom VLSI methodology, the "latch-equivalents" are far more varied and difficult to reliably
detect. We define these synchronization points, and present provably-robust algorithms to locate
them in a very general class of MOS networks, including arbitrary pass gates. The algorithms
have been applied to a variety of full-custom CPUs of up to 500K devices, and have been found
to work extremely reliably and quite fast.
References
l. Jouppi, N., "Timing Analysis & Performance Improvement of MOS VLSI Designs," IEEE Trans on CAD, Vol
CAD-6, No. 4,1987, pp. 655-6.
2. Szymanski, T., "Leadout: A Static Timing Analyzer for MOS Circuits," Proceedings ICCAD, 1986, pp. 130-133.
3. Weiner, N., and A. Sangiovanni-Vincentelli, "Timing Analysis in a Logic Synthesis Environment," Proc.
ACM/IEEE DAC,1988, pp. 655-61.
4. Sakallah, K., T. Mudge, and 0. Olukotun, "A Timing Model of Synchronous Digital Circuits,", Proc. 27th
ACM/IEEE DAC,1990, pp. 111- 117.
5. Bryant, R., "COSMOS, a Compiled Simulator for MOS Circuits," Proceedings 24th ACM/IEEE DAC,1987.
6. Bryant, R., "Algorithmic Aspects of Symbolic Switch Network Analysis," IEEE Trans. on CAD," Vol. CAD-6,
No. 4, July 1987, p. 618.
7. Breuer and Friedman, "Diagnosis & Reliable Design of Digital Systems," Computer Science Press, CA, 1976.
8. Bolsens, I., "Electrical Correctness Verif. of MOS Digital Circuits Using Expert System and Symbolic Anal.
Techniques," Ph.D. Diss., Katholieke Universiteit Leuven, Belgium, May 1989.
9. Brace, Karl, R. Rudell, and R. Bryant, "Efficient Implementation of a BDD Package", Proceedings 27th
ACM/IEEE DAC,1990, pp.40-45
10. Formal proofs omitted for lack of space, and are available upon request from the authors.
ICCAD91, Pages 308-311
Static Timing Analysis Using Interval Constraints
Ronald Stewart, Jacques Benkoski
SGS-THOMSON Microelectronics, 38019 Grenoble, France
Abstract
This work reduces the uncertainty inherent in timing analysis due to lack of proper signal
interaction modeling and delay evaluation inaccuracy. It refines the false path elimination
algorithms which place upper or lower bounds on the maximum settling time of a network by
generalizing the application of logical constraints to time intervals. This new method allows
simultaneous changes on inputs for path excitation, identifies glitches which cannot propagate,
and improves the handling of reconvergent paths. The algorithm presented is based on an
evolution of the LSP algorithm and derives multiple test vectors to excite the path as part of
the search and elimination process. The timing analyzer is tightly linked to an electrical
simulator which is used for verification of candidate paths.
References
[1] S. Even Graph Algorithms, Computer Science Press, 1979
[2] J. Benkoski, E. Vanden Meersch, L. Claesen, and H. De Man, Timing Verification Using Statically Sensitizable Paths, IEEE Transactions on CAD, Vol. 9, No. 10, Oct. 90
[3] R. Stewart and J. Benkoski, TAT00: An Industrial Timing Analyzer with False Path Generation and Test
Pattern Generation, Proceedings of the European Conference on Design Automation, Feb. 91
[4] P.C.McGeer, R.K. Brayton, Efficient Algorithms for Computing the Longest Viable Path in a Combinational
Network, Proceedings of the 26th Design Automation Conference, 1989
[5] J.Benkoski, M.Chew, A.J.Strojwas, A Framework for Timing Verification/Simulation with Varying Delays,
Proceedings of the IMEC-IFIP International Workshop on Applied Formal Methods for Correct VLSI Design,
Nov. 1989
[6] S. Perremans, L. Claesen, H. De Man, Static Timing Analysis of Dynamically Sensitizable Paths, Proceedings
of the 26th Design Automation Conference, 1989
ICCAD91, Pages 312-315
The Calculation of Signal Stable Ranges in Combinational Circuits
Li-Ren Liu, Hsi-Chuan Chen, David H.C. Du
Department of Computer Science, University of Minnesota, Minneapolis, MN 55455
Abstract
The estimation of signal stable ranges in combinational circuits is an important issue for
setting clock time in a synchronous system. In this paper, we first propose a sensitization
criterion for the shortest path, then use a path-oriented approach to reduce search space.
Considering the possible case where the signal stable range at the output of a gate could be
the union of the inputs', we can get more accurate results than the intersection-approach.
References
[1] D. Brand and V. S. Iyengar. Timing Analysis using Functional Analysis. Technical report, IBM Thomas J. Watson
Research Center, 1986.
[2] H. C. Chen and H. C. Du. Path Sensitization in Critical Path Problem. In ACM International Workshop on
Timing Issues in the Specification and Synthesis of Digital Systems, pages 1-26, 1990.
[3] M. R. Dagenais and N. C. Rumin. On the Calculation of Optimal Clocking Parameters in Synchronous Circuits
with Level-Sensitive Latches. IEEE TCAD, 8(3):268-278, 1989.
[4] J. P. Fishburn. Clock Skew Optimization. IEEE TC, 39(7):945-951, 1990.
[5] L. R. Liu, H. C. Chen, and H.C. Du. The Calculation of Signal Stable Ranges in Combinational Circuits. In
Techical Report 91-14, 1991.
[6] L. R. Liu, H. C. Du, and H. C. Chen. An Efficient Parallel Critical Path Algorithm. In Proceedings of 28th
ACM/IEEE Design Automation Conference, pages 535-540, 1991.
[7] P. C. McGeer and R. K. Brayton. Efficient Algorithms for Computing the Longest Viable Path in a Combinational
Network. In 26th DAC, pages 561-567, 1989.
[8] K. A. Sakallah, T. N. Mudge, and 0. A. Olukotun. Optimal Clocking of Synchronous Sustems. In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pages 1-21, 1990.
[9] S. H. Unger and C. J. Tan. Clock Schemes for HighSpeed Digital Systems. IEEE TC, 35(10):880-895, 1986.
ICCAD91, Pages 318-321
Automatic Synthesis of Locally-Clocked Asynchronous State Machines
Steven M. Nowick, David L. Dill
Computer Systems Laboratory, Margaret Jacks Hall, Room 222, Stanford University, Stanford, CA 94305
Abstract
This paper describes a new automated design methodology for asynchronous state-machine
controllers. Using a local-clocking scheme, the method allows multiple input changes and
produces hazard-free designs with a minimal or near-minimal number of states. We present an
automated program for asynchronous state machine synthesis, and describe a new heuristic for
state minimization and new optimizations to improve implementations. The program is used to
synthesize competitive implementations of published designs; results are compared
References
[1] E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In ICCAD-1989.
[2] J.A. Brzozowski and J.C. Ebergen. Recent developments in the design of asynchronous circuits. Technical
Report CS-89-18, U. Waterloo, CS Dept., 1989.
[3] S. M. Burns. Automated compilation of concurrent programs into self-timed circuits. Technical Report CaltechCS-TR-88-2,1987.
[4] T. A. Chu. Synthesis of self-timed vlsi circuits from graph-theoretic specifications. Technical Report MIT-LCSTR-393,1987.
[5] H.Y.H. Chuang and S. Das. Synthesis of multiple-input change asynchronous machines using controlled
excitation and flip-flops. IEEE TOC, C-22(12):1103-1109, 1973.
[6] A. Davis, W. Coates, and K. Stevens, 1990. Private communication.
[7] Alan B. Hayes. Stored state asynchronous sequential circuits. IEEE TOC, C-30(8):596-600,1981.
[8] L. A. Hollaar. Direct implementation of asynchronous control units. IEEE TOC, C-31(12 1133-1141,1982.
[9] M. Ladd and W. P. Birmingham. Synthesis of multiple-input change asynchronous finite state machines. In
DAC-91.
[10] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli. Algorithms for synthesis of hazard-free asynchronous
circuits. In DAC-91.
[1l] A. J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Henry Fuchs, editor, 1985
Chapel Hill Conference on Very Large Scale Integration, pages 245-60. CSP, Inc., 1985.
[12] Edward J. McCluskey. Logic Design Principles. Prentice-Hall, 1986.
[13] T. H. Meng. Synchronization Design for Digital Systems. Kluwer Academic, 1990.
[14] C. E. Molnar, T. P. Fang, and F. U. Rosenberger. Synthesis of delay-insensitive modules. In Henry Fuchs,
editor, 1985 Chapel Hill Conference on Very Large Scale Integration, pages 67-86. CSP, Inc., 1985.
[15] C.W. Moon, P.R. Stephen, and R.K. Brayton. Specification, synthesis, and verification of hazard-free
asynchronous circuits. In 1991 Int. Wkshp. Logic Synth. (MCNC).
[16] S. M. Nowick and D. L. Dill. Asynchronous state machine synthesis using a local clock. In 1991 Int. Wkshp.
Logic Synth. (MCNC).
[17] S. M. Nowick and D. L. Dill. Synthesis of asynchronous state machines using a local clock. In ICCD-1991.
[18] I.E. Sutherland Micropipelines. CACM, 32(6):720-738,1989.
[19] J.H. Tracey. Internal state assignments for asynchronous sequential machines. IEEE TEC, EC-15:551-560,
August 1966.
[20] S.H. Unger. Asynchronous Sequential Switching Circuits. New York: WileyInterscience,1969.
[21] P. Vanbekbergen, F. Catthoor, G. Goossens, and H. De Man. Optimized synthesis of asynchronous control
circuits from graph-theoretic specifications. In ICCAD-1990.
ICCAD91, Pages 322-325
Synthesis of Hazard-free Asynchronous Circuits from Graphical Specifications
Cho W. Moon, Paul R. Stephan, Robert K. Brayton
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley
Abstract
We propose some syntactic and semantic extensions to a graphical specification called the signal
transition graph (STG). Our extensions allow for a more natural and compact specification of
asynchronous behavior. We show that syntactic constraints on STGs are not sufficient to guarantee
a hazardfree implementation, and present techniques to synthesize hazard free circuits under both
single input change and multiple input change conditions.
References
[1] C. Berthet and E. Cerny. "Synthesis of Speed-independent Circuits Using SetMemory Elements". In G. Saucier,
editor, Proc. Int'l. Workshop Logic and Arch. Synthesis for Silicon Compilers. Grenoble, France, May 1988.
[2] G. Borriello. "A New Interface Specification Methodology and Its Application to Transducer Synthesis". PhD
thesis, U.C. Berkeley, 1988.
[3] Tam-Anh Chu. "Synthesis of Self timed VLSI Circuits from Graph-theoretic Specifications". PhD thesis, MIT,
June 1987.
[4] E. B. Eichelberger. "Hazard Detection in Combinational and Sequential Switching Circuits". IBM Journal of
Research and Development, pages 90 - 99, March 1965.
[5] Z. Har'El and R. P Kurshan. "Software for Analysis of Coordination". In Proc. International Conf. Syst. Sci.,
pages 382 - 385, 1988.
[6] T. Meng, R. W. Brodersen, and D. G. Messerschmitt. "Automatic Synthesis of Asynchronous Circuits from
High-Level Specifications". IEEE Tran. Computer-Aided Design, 8(11):1185 -1205, November 1989.
[7] Cho W. Moon, Paul R. Stephan, and Robert K. Brayton. "Specification, Synthesis and Verification of Hazardfree Asynchronous Circuits". Technical Report UCB/ERL M91/67, University of California, Berkeley, 1991.
[8] Stephen H. Unger. "Asynchronous Sequential Switching Circuits". Wiley-Interscience,1969.
[9] P. Vanbekbergen, F. Catthoor, G. Goossens, and H. De Man. "Optimized Synthesis of Asynchronous Control
Circuits from Graph-theoretic Specifications". In Proc. Int'l. Conf. Computer-Aided Design, pages 184 -187,1990.
ICCAD91, Pages 326-329
Synthesis for Testability Techniques for Asynchronous Circuits
Kurt Keutzer
Synopsys Inc.
Mountain View, CA
Luciano Lavagno
University of California
Berkeley, CA
Alberto Sangiovanni-Vincentelli
University of California
Berkeley, CA
Abstract
Our goal is to synthesize asynchronous circuits that realize two very stringent constraints
simultaneously: hazard-free operation and hazard-free robust path-delay-fault testability. In this
paper we present techniques which guarantee both hazard-free operation and hazard-free robust path-delay-fault testability, at the expense of possibly adding test inputs. We also give a set
of heuristics which can improve hazard-free robust path-delay-fault testability without requiring
such inputs. Finally, we demonstrate the effectiveness of these techniques on a set of
asynchronous interface circuits gathered from industry and academia.
References
[1] T. A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, MIT,
June 1987.
[2] S. Devadas and K. Keutzer. Synthesis of Robust Delay-fault Testable Circuits: Practice. IEEE Transactions on
Computer-Aided Design of Integrate Circuits and Systems, October 1991. To appear.
[3] S. Devadas and K. Keutzer. Synthesis of Robust Delay-fault Testable Circuits: Theory. IEEE Transactions on
Computer-Aided Design of Integrate Circuits and Systems, September 1991. To appear.
[4] S. Kundu, S. Reddy, and N. Jha. Design of robustly testable combinational logic circuits. IEEE Transactions on
Computer-Aided Design, 10(8):1036-1047, August 1991.
[5] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli. Algorithms for synthesis of hazard-free asynchronous
circuits. In Proceedings of the Design Automation Conference, June 1991.
[6] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli. Synthesis of verifiably .hazard-free asynchronous control
circuits. In Advanced Research in VLSI Conference, March 1991.
[7] M. C. Paull and S. H. Unger. Minimizing the Number of States in Incompletely Specified Sequential Circuits. In
IRE Transactions on Electronic Computers, volume EC-8, pages 356-357, September 1959.
ICCAD91, Pages 332-335
Timing-Oriented Routers for PCB Layout Design of High-Performance Computers
Yutaka Sekiyama1 Yasuyuki Fujihara1 Terumine Hayashi1 Mitsuho Seki1
Jiro Kusuhara2 Kazuhiko Iijima2 Masahiro Takakura3 Koji Fukatani3
1
Hitachi Research Laboratory, Hitachi, Ltd., Japan
2
Kanagawa Works, Hitachi, Ltd., Japan
3
Hitachi Engineering Co., Ltd., Japan
Abstract
This paper presents two timing-oriented routers for PCB layout designs of high-performance
computers. The Recursive Pattern-Search Router is a precise specified-length router, which
does not use detour points, but instead, recursively repeats the search procedures using Ushaped and simple patterns such that the wire length is adjusted to the specified value. This
router guarantees that a route can be found which satisfies the length constraint if one exists.
It is also capable of pairwise routing. The Detour-Length-Driven Line Router is a diagonal
router based on line routing. The router finds a minimal-length route rapidly using diagonal
and orthogonal directions. These routers were incorporated into a routing system for PCB
layout designs of mainframe computers, and they were confirmed as practical.
References
[1] H. Terai, et al., "Basic Concepts of Timing-oriented Design Automation for High-Performance Mainframe
Computers", Proc. 28th DAC, pp.193-198,1991.
[2] N. Kuwahara, et al. , "A Routing System for High-Performance Computer Systems", Proc. ICCAD-86, pp. 250253, 1986.
[3] A. Hanafusa, et al., "Router System for High-Density Multi-Layer Printed Wiring Boards", Proc. Printed Circuit
World Convention 4, WCIV-3,1987.
[4] A. Hanafusa, et al., "Three-Dimensional Routing for Multi-layer Ceramic Printed Circuit Boards", Proc. ICCAD90,
pp. 386-389, 1990.
[5] Y. Fujihara, et al. , "DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions", Proc.
26th DAC, pp. 791-794,1989.
[6] K. Mikami and K. Tabuchi, "A Computer Program for Optimal Routing of Printed Circuit Conductors", IFIP Proc.
68, pp. 1475-1478, 1968.
[7] D.W. Hightower, "A Solution to Line-Routing Problems on the Continuous Plane", Proc. 6th Design Automation
Workshop, pp. 1-24, 1969.
ICCAD91, Pages 336-339
Exact Zero Skew
Ren-Song Tsay
IBM, T. J. Watson Research Center
Abstract
An exact zero skew clock routing algorithm using Elmore delay model is presented.
Recursively in a bottom-up fashion, two zero-skewed subtrees are merged into a new tree
with zero skew. The algorithm can be applied to single-staged clock trees, multi-staged
clock trees, and multi-chip system clock trees. It is ideal for hierarchical methods of
constructing large systems. All subsystems can be constructed in parallel and
independently, then interconnected with exact zero skew.
References
[1] T. H. Corman, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. McGraw Hill, New York, 1990.
[2] J. P. Fishburn. Clock skew optimization. IEEE Transactions on Computer, C-39(7):945-951, 1990.
[3] M. A. B. Jackson, A. Srinivasan, and E. S. Kuh. Clock routing for high-performance IC's. In Proceedings o f
Design Automation Conference, pages 573-579, 1990.
[4] Andrew Kahng, Jason Cong, and Gabriel Robins. High-performance clock routing based on recursive geometric
matching. In Proceedings of Design Automation Conference, pages 322-327, 1991. .
[5] J. Rubinstein, P. Penfield, and M.A. Horowitz. Signal delay in rc tree networks. IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, 2(3):202-211, 1983.
[6] Ren-Song Tsay. Exact zero skew. Technical Report RC 16683, IBM Yorktown Research Center, 1991.
ICCAD91, Pages 340-343
PROTON.- A Parallel Detailed Router on an MIMD Parallel Machine
Tsukasa Yamauchi, Toshiyuki Nakata, Nobuhiko Koike
C&C Systems Research Laboratories, NEC Corporation, 4-1-1 Miyazaki Miyamae-Ku, Kawasaki, Kanagawa 216,
JAPAN
Akio Ishizuka, Nobuyuki Nishiguchi
VLSI CAD Engineering Division, NEC Corporation, 1753 Shimonumabe Nakahara-Ku, Kawasaki, Kanagawa 211,
JAPAN
Abstract
This paper describes a new parallel detailed router named PROTON (Parallel
ROuTer ON a parallel machine) with various new features including:
• Parallelized Line Search algorithm based on parallel breadth first search.
• Extraction of higher degree of parallelism by simultaneous routing of multiple
nets using the result o f the global router.
• Parallel router on a quasi-shared-memory based MIMD (Multiple Instruction
streams Multiple Data streams) parallel machine.
• Detailed router supporting multi-layer channelless gate arrays with complex
industrial design rules.
PROTON is implemented on an MIMD parallel machine named Cenju which
consists of 64 microprocessors. In order to improve routing speed, PROTON
incorporates two level parallelism, namely intranet parallelism and net level
parallelism. We have achieved a speedup of 43 times using 64 processors for a
medium scale channelless gate array (1,537 x 1, 790 grids, 12, 591 pin pairs).
References
[1] T.Nakata, N.Tanabe, N.Kajihara, S.Matsushita, H.Onozuka, Y.Asano and N.Koike, 'Cenju: A Multiprocessor
System for Modular Circuit Simulation', Computing Systems in Engineering Vol. 1, No.1, pp 101-109(1990).
[2] K.Suzuki, T.Ohtsuki and M.Sato, 'A Gridless Router:Software and Hardware Implementations', VLSI '87, pp
121-131(1987) .
[3] W.Lipski, 'Finding a Manhattan Path and Related Problems', NETWORKS, Vol.13, pp399409 (1983).
ICCAD91, Pages 344-347
A Parallel Steiner Heuristic For Wirelength Estimation Of Large Net Populations
Rajeev Jayaraman and Rob A. Rutenbar
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
Abstract
This paper discusses techniques to produce Steiner trees for a large population of nets, e.g., 1000
to 5000 nets, in parallel. This problem arises in iterative-improvement layout strategies that
perturb not just a single placed object, but a few thousand objects simultaneously. Such strategies
are the focus of work on mapping large placement problems onto massively parallel computers.
We present a new heuristic that computes Steiner-trees for an arbitrary number of nets, each with
an arbitrary number of terminals, in essentially constant time given sufficient data-parallel
machine resources and a constant distribution of net sizes. Experiments on a Connection
Machine demonstrate that it is possible to create good Steiner trees for a few thousand nets in a
few hundred milliseconds.
References
[1] M. Hanan, "On Steiner's problem with rectilinear distance," SIAM Journal on App. Math.,
vol. 14, pp. 255-265, March 1966.
[2] J. H. Lee, N. K. Bose, and F. K. Hwang, "Use of Steiner's problem in sub-optimal routing in
rectilinear metric," IEEE Trans. on Circuits and Systems, vol. CAS-23, pp. 470-476, July 1976.
[3] J. Ho, G. Vijayan, and C. K. Wong, "A new approach to the rectilinear Steiner tree problem,"
in Proc. ACM/IEEE Design Auto. Conf., 1989, pp. 161-166.
[4] W. Hillis, The Connection Machine. MIT Press, Cambridge, MA, 1985.
[5] T. Blank, "The Maspar MP-1 architecture," in Proc. COMPCON Spring 90, 1990, pp. 20-24.
[6] J. Savage and M. Wloka, "Heuristics for parallel graph-partitioning," Tech. Report CS-89-41,
Brown University, Providence, RI December 1989.
[7] R Guerrieri and A. Sangiovanni-Vincentelli, "Three-dimensional capacitance evaluation on a Connection
Machine," IEEE Trans. on CAD, vol. 7, pp. 1125-1133, November 1988.
[8] E. Carlson and R Rutenbar, "Design and performance evaluation of new massively parallel mask checking
algorithms in JIGSAW," in Proc. ACM/IEEE Design Auto. Conf., 1990.
[9] C. Sechen, VLSI Placement and Global Routing using Simulated Annealing. Kluwer Academic Publishers,
Boston, MA, 1988.
[10] A. Casotto and A. Sangiovanni-Vincentelli, "Placement of standard cells using simulated annealing on the
connection machine," in Digest of Technical Papers - ICCAD-87, 1987, pp. 350-353.
[11] R. Jayaraman and F Darema, "Error tolerance in parallel simulated annealing techniques," in Proc. ICCD 88,
1988.
[12] M. D. Durand, "Accuracy vs. speed in placement," IEEE Design and Test of Computers, vol. 6, pp. 8-27, June
1989.
[13] G. E. Blelloch, "Scans as primitive parallel operations," IEEE Trans. on Computers, vol. 38, pp. 1526-1538,
November 1989.
[14] M. Hanan, "Net wiring for Large Scale Integrated circuits," Tech. Report RC 1375, IBM, 1965.
[15] A. Dunlop and B. W. Kernighan, "A procedure for placement of standard-cell VLSI circuits," IEEE Trans. on
CAD, vol. CAD-4, pp. 92-98, January 1985.
[16] D. Richards, "Fast heuristics algorithms for rectilinear Steiner trees," Algorithmica, vol. 4, pp. 191-207, 1989.
[17] W. D. Hillis and G. L. Steele Jr., "Data parallel algorithms," Communications of the ACM, vol. 29, pp. 11701183, 1986.
[18] J. Rubenstein, P Penfield Jr., and M. Horowitz, "Signal delay in RC tree networks," IEEE Trans. CAD, pp.
202-211, July 1983.
ICCAD91, Pages 350-353
Extraction of Gate Level Models from Transistor Circuits
by Four-Valued Symbolic Analysis
Randal E. Bryant
Fujitsu Laboratories, Ltd. Kawasaki, JAPAN
Abstract
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit.
The resulting model contains only four-valued unit and zero delay logic primitives, suitable for
evaluation by conventional gate-level simulators and hardware simulation accelerators.
TRANALYZE has the same generality and accuracy as switch-level simulation, generating
models for a wide range of technologies and design styles, while expressing the detailed effects
of bidirectional transistors, stored charge, and multiple signal strengths. It produces models with
size comparable to ones generated by hand.
References
[1] D. T. Blaauw, P. Banerjee, and J. A. Abraham, "Automatic classification of node types in switch-level
descriptions," ICCAD,1990.
[2] D. T. Blaauw, D. G. Saab, J. Long, and J. A. Abraham, "Derivation of signal flow for switch-Level
simulation," EDAC,1990, 301-305
[3] D. T. Blaauw, D. G. Saab, P. Banerjee, and J. A. Abraham, "Functional abstraction of logic gates for switchlevel simulation," EDAC,1991.
[4] M. Boehner, "LOGEX--An automatic logic extractor from transistor to gate level for CMOS technology,"
25th DAC, 1988, 517-522.
[5] R. E. Bryant, et al, "COSMOS: a compiled simulator for MOS circuits," 24th DAC, 1987, 9-16.
[6] R. E. Bryant, "Algorithmic aspects of symbolic switch network analysis," IEEE Trans. CAD/IC, 1987, 618633.
[7] R. E. Bryant, "Boolean analysis of MOS circuits," IEEE Trans. CAD/IC, 1987, 634-649.
[8] F. Hirose, K. Takayama, and J. Niitsuma, "An event-driven logic simulation machine of computer systems,"
Proc.1990 European Simulation Multiconference, Nuremburg, Germany, June, 1990.
[9] A. Jain, and R. E. Bryant, "Mapping switch-level simulation onto gate-level hardware accelerators," 28th
DAC, 1991.
[10] K. Keutzer, "DAGON: Technology binding and local optimization by DAG matching," 24th DAC, 1987,
341-347.
ICCAD91, Pages 354-357
Bipolar Timing Modeling Including Interconnects Based on Parametric Correction
Andrew T. Yang, Yu-Hsu Chang
NSF Center for the Design of Analog-Digital Integrated Circuits, Dept. of Electrical Engineering, University of
Washington Seattle, Washington 98195
Abstract
We present an approach for the analytical timing model development of bipolar VLSI circuits.
The approach is based on the development of the delay functions of three basic bipolar subcircuits. We show that accurate timing information for two high-speed digital circuit
constructs, ECL and BiCMOS, can be obtained by repeated processing of these sub-circuit
delay functions. The timing models have been shown to be accurate typically within 10 % of
SPICE's estimates with up to three orders of speedup for large-scale BJT circuits.
References
[1] P. O'Brien, J. Wyatt, Jr., T. Savarino, J. Pierce, "Fast OnChip Delay Estimation for Cell-Based emittercoupled Logic", Proc. 1988 ISCAS, pp.1357-1360,1988.
[2] G. P. Rosseel and R. W. Dutton, "Influence of device parameters on the switching speed of BiCMOS
buffers," IEEE J. Solid-State Circuits, pp. 90-99, February 1989.
[3] D. G. Saab, A. T. Yang, I.N. Hajj, "Delay Modeling and Timing of Bipolar Digital Circuits", Proc. of DAC,
pp. 288-293, June,1988.
[4] D. S. Gao, A. T. Yang and S. M. Kang, "Modeling and simulation of interconnection delays and crosstalks
in highspeed integrated circuits," IEEE Trans. Circuits and Systems, pp. l-9, January 1990.
[5] T. Sakurai and K. Tamaru, "Simple formulas for two- and three- dimensional capacitances," IEEE Trans.
Electron Devices, pp. 183-185, Feb., 1983.
[6] I. N. Hajj and D. G. Saab, "Switch-level logic simulation of digital bipolar circuit," IEEE Trans. CAD, pp.
251-258, March 1987.
ICCAD91, Pages 358-361
A Stimulus/Response System Based on Hierarchical Timing Diagrams
K. Khordoc, M. Dufresne, E. Cerny
Dép. d'informatique et de recherche opérationnelle, Université de Montreal, C.P 6128, succursale A, Montréal,
Quebec, H3C 3J7 Canada
Abstract
We present a tool that captures timing specifications from hierarchical timing diagrams and
models them using hierarchical constraint graphs. Our main contribution is a new algorithm
that traverses the graph during simulation to generate stimuli and to validate circuit
responses. We discuss a VHDL-based implementation, and illustrate its usefulness and
limitations.
References
[1] F. Jahanian and A.K.L Mok, "A graph-theoretic approach for timing analysis and its implementation", IEEE
Transactions on Computers, C-36(8), August 1987.
[2] S.K Sherman, "Algorithms for timing requirement analysis and generation", in ACM/IEEE Proc. 25th DAC,
pages 724-727,1988.
[3] A.R Martello, S.P Levitan, and D.M Chiarulli, "Timing verification using HDTV", in ACM/IEEE Proc. 27th
DAC, pages 118-123,1990.
[4] A. Kara, R. Rastogi, and K. Kawamura, "TDS: An expert system to automate timing design for interfacing VLSI
chips in microcomputer systems", in IEEE Proc. ICCAD86, pages 362-365, 1986.
[5] G. Boriello, A New Interface Specification Methodology and its Application to Transducer Synthesis,
PhD thesis, University of California, Berkeley, 1988.
[6] IEEE, IEEE Standard 1076-1987, VHDL Language Reference Manual, IEEE, 1987.
[7] R.E Tarjan, Data Structures and Network Algorithms, SIAM, Philadelphia, 1983.
[8] K. Khordoc, M. Dufresne, and E. Cerny,
"A stimulus/response system based on hierarchical timing diagrams" Publication 770, Dept. I.R.O., University de Montreal,1991.
[9] Intel Corporation, MCS-85 User's Manual, Intel, Santa Clara, CA, 1978.
ICCAD91, Pages 362-365
Obtaining Functionally Equivalent Simulations Using VHDL and a
Time-shift Transformation
Frank Vahid and Daniel D. Gajski
Department of Information and Computer Science, University of California, Irvine, CA, 92717
Abstract
The advent of VHDL has brought about a number of VHDL simulators. Many translation
schemes from domain specific languages to supposedly functionally equivalent VHDL
have been developed as an approach to simulation. However, due to a subtle theoretical
limitation to this approach, functionally equivalent VHDL can not be created for the
general case, making such translations an unsound technique. We introduce this
fundamental limitation. We then propose an alternative approach which strives instead for
functionally equivalent simulation, while still taking advantage of VHDL simulators. Our
method uses a novel time-shift transformation in conjunction with any translation scheme,
making correct simulations easily obtainable. This bridges the gap to a sound and
advantageous use of VHDL as a tool for simulating domain specific languages.
References
[1] IEEE Standard VHDL Language Reference Manual, 1988.
[2] D. Harel, "Statecharts : A visual formalism for complex systems," Science of Computer Programming 8,
1987.
[3] A. Jerraya, P. Paulin, and D. Agnew, "Facilities for controllers modeling and synthesis in VHDL." VHDL User's
Group Conference, 1991.
[4] N. Dutt, T. Hadley, and D. Gajski, "An intermediate representation for behavioral synthesis," in Proc. of the 27th
DAC, 1990.
[5] F. Vahid, S. Narayan, and D. Gajski, "SpecCharts: A language for system level synthesis," in Proc. of the International Symposium on Computer Hardware Description Languages and their Applications, 1991.
[6] A. Arsenault, J. Wong, and M. Cohen, "VHDL transition from system to detailed design." VHDL User's Group
Meeting, 1990.
[7] N. Dutt, J. Cho, and T. Hadley, "A user interface for VHDL behavioral modeling," in Proc. of the International
Symposium on Computer Hardware Description Languages and their Applications, 1991.
[8] R. MacDonald and R. Waxman, "Operational specification of the SINCGARS radio in VHDL," in Proc. of the
AFCEA-IEEE Tactical Communications Conference, 1990.
[9] S. Narayan, F. Vahid, and D. Gajski, "Translating system specifications to VHDL," in Proc. of the European
Conference on Design Automation, 1991.
[10] T. Tikanen, T. Leppanen, and J. Kivela, "Structured analysis and VHDL in embedded asic design and
verification," in Proc. of the European Conference on Design Automation, 1990.
[11] M. Shahdad, et al., "VHSIC hardware description language," Computer, February 1985.
[12] S. Narayan and F. Vahid, "Translating SpecCharts to VHDL." UC Irvine, TR 90-21,1990.
[13] F. Vahid, "Obtaining functionally equivalent simulations using VHDL and a time-shift
transformation." UC Irvine, TR 91-33,1991.
ICCAD91, Pages 368-371
Converting Combinational Circuits into Pipelined Data Paths
Andreas Münzner, Gunter Hemme
Laboratorium für Informationstechnologie, Universität Hannover, Schneiderberg 32 3000 Hannover 1, FRG
Abstract
This paper presents an algorithm which converts combinational circuits into pipelined data paths
under consideration of a given clock period. The approach minimizes the number of registers
which is achieved by a recursive procedure selecting, for each pipeline level those circuit parts
where a register location satisfies the timing constraints. The selection is based on an as-soon-aspossible and as--late-as-possible register location using a modified retiming algorithm. Within
these circuit parts a maximal flow algorithm guarantees to find the minimal number of flip-flops
for a register. Because the algorithm runs in polynomial time and requires only a sparse graph
representation of the circuit it is applicable to VLSI circuits. It is integrated into a synthesis tool
for arithmetic building blocks and results are presented of its application to circuits of size up to
10,000 gates.
References
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R.B. Hitchcock, "Timing Verification and the Timing Analysis Program". IEEE Proc. o f the 19th
Design Automation Conference, June 1982, pp. 594--604.
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P.A. Jensen and J W. Barnes. Network Flow Programming. John Wiley & Sons Inc., 1980.
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H. Jeschke, T. Wehherg and H. Volkers, "A MIMD based multiprocessor architecture for real-time
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Circuits and Systems, Jan. 1991, pp. 74--84.
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ICCAD91, Pages 372-375
An ATPG-Based Approach to Sequential Logic Optimization
Kwang-Ting Cheng
AT&T Bell Laboratories Murray Hill, NJ 07974
Abstract
The authors propose a method of redundancy identification for synchronous sequential circuits that
don't have a global reset state. All existing structure-level test generators use the 3-valued logic,
which is not completely accurate, to process circuits that have an unknown initial state. A fault that
is reported undetectable by such test generators is not necessarily redundant. This paper contains
derivations of conditions in which undetectable faults are redundant. For a pure pipeline circuit or
in a resettable circuit, the authors show that a fault is undetectable (by 3-valued-logic based test
generators) if and only if it is redundant. For general sequential circuits, the authors classify
undetectable faults into three categories: (1) un-activatable faults (2) un-propagatable faults and
(3) faults that are both activatable and propagatable, but cannot be simultaneously activated and
propagated by any vector sequence. The authors show that class (1) and (2) faults are redundant
faults while class (3) faults may not be. Algorithms for identifying un-activatable and unpropagatable faults are also described. These algorithms are implemented and incorporated in a
redundancy removal system MIRACLE. Experimental results on large MCNC sequential
benchmark circuits are presented.
REFERENCES
1. K.-T. Cheng, "On Removing Redundancy in Sequential Circuits," Proc. 28th Design Automation Conf., pp.
164-169 (June 1991).
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on Computers C-28, pp. 864-865 (November 1979).
3. K.-T. Cheng, "An ATPG-Based Approach to Sequential Logic Optimization," Proc. Int'l Workshop on Logic
Synthesis, Research Triangle Park, NC (May 1991).
4. S. Devadas, H.-K. T. Ma, and A. R. Newton, "Redundancies and Don't Cares in Sequential Logic Synthesis,"
J. Electronic Testing: Theory and Application (JETTA) 1-1, pp. 15-30 (Feb. 1990).
5. T. Gheewala, "Crosscheck: A Cell Based VLSI Testability Solution," Proc. 26th Design Automation Conf.,
pp. 706-709 (June 1989).
6. R. A. Marlett, "EBT: A Comprehensive Test Generation Technique for Highly Sequential Circuits," Proc.
Des. Auto. Conf., Las Vegas, Nevada, pp. 335-339 (June 1978).
7. W. T. Cheng, "The BACK Algorithm for Sequential Test Generation," Proc. Int. Conf. Computer Design
(ICCD-88), Rye Brook, NY, pp. 66-69 (October 1988).
8. S. Yang, "Logic Synthesis and Optimization Benchmarks User Guide," MCNC Technical Report (Jan. 1991).
9. W.-T. Cheng and S. Davidson, "Sequential Circuit Test Generator (STG) Benchmark Results," Proc. Int'l
Symp. on Circuits and Systems, pp. 1939-1941 (May 1989).
ICCAD91, Pages 376-379
Calculating Resetability and Reset Sequences
Carl Pixley and Gary Beihl
Microelectronics and Computer Technology Corporation (MCC), Computer Aided Design Program, 3500 West
Balcones Center Drive, Austin, TX 78759-6509
Abstract
A synchronous sequential design is resetable if there is a finite sequence of primary input
vectors (called a reset (or synchronizing) sequence) and a single state (called a reset state)
such that application of the reset sequence to any initial state of the design, drives the
design into the reset state. Because the initial state of any design is uncertain when the
design is powered up, resetability is a fundamental property necessary for predictable
behavior [1] [2]. There are several problems related to resetability: (1) the problem of
deciding whether a design is resetable, (2) the problem of actually finding a reset sequence
and reset state, and (3) the problem of discovering whether a purported reset sequence
actually resets the design. New algorithms to solve each of these problems and
experimental results are presented.
References
[1] C. Pixley, A Computational Theory and Implementation of Sequential Hardware Equivalence, DIMACS
Technical Report 90-31, volume 2, Workshop on Computer-Aided Verification June 18-21, 1990, Robert
Kurshan and E.M. Clarke, eds.
[2] C. Pixley and G. Beihl, Quotient and Isomorphism Theorems of a Theory of Sequential Hardware Design,
Proceedings of the 1991 International Workshop on Formal Methods in VLSI Design, January 9-11, 1991, Miami,
Florida.
[3] O. Coudert, C. Berthet, Jean Christolphe Madre, Verification of Sequential Machines Using Boolean Functional
Vectors, Proceedings of the IMEC IFIP International Workshop on Applied Formal Methods For Correct
VLSI Design, November 13-16, 1989.
[4] R.E. Bryant, Graph-Based Algorithms for Boolean Function Manipulation, IEEE Transactions on Computers,
Vol. C35 No. 8, August 1986.
[5] K. Brace, R. Bryant, and R. Rudell, Efficient Implementation of a BDD Package, Proceedings of the 27th
ACM/IEEE Design Automation Conference, June 1990, pp. 40-45.
[6] K-T Cheng and V. Agrawal, State Assignment for Initializable Synthesis, Prodeedings of the IEEE International
Conference on Computer Aided Design, pp. 212-215, Santa Clara, CA, November 1989.
[7] H. Cho, G. Hachtel, S-W Jeong, B. Plessier, E. Schwarz, and F. Somenzi, ATPG Aspects of FSM Verification,
Prodeedings of the IEEE International Conference on Computer Aided Design, pp. 134-137, Santa Clara, CA,
November 1990.
[8] H. Cho, G. Hachtel, and F. Somenzi, Redundancy Identification and Removal Based on BDD's and Implicit State
Enumeration, preprint 1991.
[9] B. Lin, H. Touati, and A.R. Newton, Don't Care Minimization of Multi-level Sequential Logic Networks,
Prodeedings of the IEEE International Conference on Computer Aided Design, pp. 414-417, Santa Clara, CA,
November 1990.
ICCAD91, Pages 380-383
Verification of Relations between Synchronous Machines
Filip Van Aelten, Jonathan Allen, Srinivas Devadas
Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge,
MA 02139
Abstract
This paper addresses the problem of implementation verification at the behavioral level. A
formalism is needed for specifying synchronous circuits and expressing correctness
requirements that leave room for modifying the input/output behavior of the implementation. Furthermore, a procedure is needed to verify, these requirements. We model
both specifications and implementations as synchronous logic circuits, and cast the
correctness requirements as relations between string functions associated with a specification and an implementation. We define six primitive relations between string
functions, namely delay, don't care times, parallelism, encoding, input don't care and output
don't care relations. These relations have attributes, for instance a delay time for the delay
relation. We show that these relations can be verified by transforming the specification and
the implementation and performing an input/output equivalence check. We also allow for
composite relations, and show that, given an arbitrary composite relation, a closely related
composition can be constructed which can be verified through one equivalence check.
Experimental results are presented.
References
[1] A. Bronstein and C. Talcott. Formal Verification of Pipelines based on String-Functional Semantics. In Formal
VLSI Correctness Verification, VLSI Design Methods-II, pages 349-366. North-Holland, 1990.
[2] O. Coudert, C. Berthet, and J. C. Madre. Verification of Sequential Machines Using Boolean Functional Vectors.
In IMEC-IFIP Int'l Workshop on Applied Formal Methods for Correct VLSI Design, pages 111-128, November
1989.
[3] S. Devadas and K. Keutzer. An Automata-Theoretic Approach to Behavioral Equivalence. In Proceedings of
the Int'l Conference on Computer-Aided Design, pages 30-33, November 1990.
[4] M. Leeser and W. Wolf. Behavior FSMs for HighLevel Verification and Synthesis. In Proceedings o f 1991
International Workshop on Formal Methods in VLSI Design, January 1991.
[5] H. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit State Enumeration of Finite
State Machines Using BDD's. In Proc. of Int'l Conference on Computer-Aided Design, pages 130-133, November
1990.
ICCAD91, Pages 386-389
A Behavioral Representation for Nyquist Rate A/D Converters
Edward Liu, Alberto L. Sangiovanni-Vincentelli, Georges Gielen, and Paul R. Gray
Department of Electrical Engineering & Computer Sciences, University of California Berkeley, California
94720
Abstract
This paper presents a behavioral representation for the class of Nyquist rate A/D converters. The
representation captures the nominal A/D behavior, as well as all the statistical variations. The
variations are classified into noise and process variations according to how these non-idealities
affect the A/D behavior. To describe noise effects we use a joint probability density function. To
describe behavioral effects due to process variations we use a variance-covariance matrix, Et,
which is a generalization of the integral nonlinearity vector. Σt's rank characterizes the testability
of an A/D; its decomposition yields efficient strategies for A/D testing. Finally, parameter
extraction results obtained from prototypes are presented.
References
[1] G. Jusuf, P. R. Gray, A. L. Sangiovanni-Vincentelli "CADICS-Cyclic Analog-To-Digital Converter
Synthesis", ICCAD 1990.
[2] Ruan, Genhong "A Behavioral Model of A/D Converters Using a Mixed-Mode Simulator", IEEE Journal of
Solid-State Circuits, Vol. 26, No. 3, March 1991
[3] T. M. Souders, G. N. Stenbakken, "Cutting the high cost of testing", IEEE Spectrum, March 1991.
ICCAD91, Pages 390-393
Automating Analog Circuit Design using Constrained Optimization Techniques
Prabir C. Maulik and L. Richard Carley
Department o f Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
Abstract
A CAD tool that accurately sizes analog circuits in short-channel CMOS processes using
SPICE-quality device models and constrained optimization techniques is presented. All
knowledge about device behavior is embedded within an encapsulated device evaluator
which simplifies the description of the analog circuit that must be provided by an expert
designer, and makes that description independent of the specific device type and technology. The use of constrained optimization allows the KCL and KVL constraints that
determine the DC operating point of a circuit to be formulated and solved simultaneously
with the performance constraints. In addition, the constrained optimization formulation of
the analog design problem makes it easy for the user to study tradeoffs in the circuit design
space by varying the performance constraints. Simulation results demonstrate the tool's
ability to accurately synthesize high performance two-stage CMOS op amps in 2µm and
1.2 µm CMOS processes.
References
[1] Robert K. Brayton et. al. A survey of optimization techniques for integrated-circuit design. Proceedings
of the IEEE, 69(10):1334-1362, Oct. 1981.
[2] William Nye et. al. DELIGHT.SPICE: An optimization-based system for the design of integrated
circuits. IEEE Transactions On Computer-Aided Design, 7(4):501-519, Apr. 1988.
[3] R.Harjani, R.A.Rutenbar and L.R.Carley. OASYS: A framework for analog circuit synthesis. IEEE
Transactions on Computer-Aided Design, 8(12):1247-1266, Dec. 1989.
[4] H.Y.Koh, C.H.Sequin and P.R.Gray. OPASYN: A compiler for CMOS operational amplifiers. IEEE
Transactions on Computer-AidedDesign, 9(2):113-125, Feb. 1990.
[5] Marc G.R. Degrauwe et. al. IDAC: An interactive design tool for analog CMOS circuits. IEEE Journal
of Solid-State Circuits, sc22(6):1106-1116, Dec. 1987.
[6] E.Berkcan, M.d'Abreu, and W.Laughton. Analog compilation based on successive decompositions. In
Proceedings of 25th Design Automation Conference, pages 369-375. ACM/IEEE, 1988.
[7] G.G.E.Gielen et.al. ISAAC: A symbolic simulator for analog integrated circuits. IEEE Journal of SolidState Circuits, 24(6):1587-1597, Dec. 1989.
[8] Koen Swings, Georges Gielen, and W.Sansen. An intelligent analog is design system based on
manipulation of design equations. In Proceedings of Custom Integrated Circuits Conference. IEEE, 1990.
[9] FOp't Eynde and W.Sansen. Design and optimization of CMOS wideband amplifiers. In Proceedings of
Custom Integrated Circuits Conference. IEEE, 1989.
[10] Bing J. Sheu et.al. BSIM: Berkeley short-channel IGFET model for MOS transistors. IEEE Journal of
Solid-State Circuits, sc22(4):558-566, Aug. 1987.
[11] Philip Gill, Walter Murray, Michael Saunders, and Margaret Wright. User's guide for NPSOL (version
4.0). Technical Report SOL 86-2, Stanford University, Jan. 1986.
[12] Roger Fletcher. Practical Methods of Optimization. John Wiley and Sons.
[13] Paul J. Donahue. Synthesis of high performance regenerative comparators using constrained
optimization. Master's thesis, Camegie Mellon University, Oct. 1991.
ICCAD91, Pages 394-397
Techniques for Simultaneous Placement and
Routing of Custom Analog Cells in KOAN/ANAGRAM II
John. M. Cohn, David. J. Garrod, Rob. A. Rutenbar, and L. Richard Carley
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213
Abstract
We describe new techniques for simultaneous device-placement and detailed-routing of analog
cells. Both nets and devices are treated as placeable, malleable objects in a common simulatedannealing framework. A detailed routing abstraction called a k-bend net limits the complexity of
each net's topology, and allows simple incremental net reshaping during annealing. Analog layouts
in which the critical interacting nets are simultaneously embedded during device-placement prove
to be superior, in terms of performance-limiting crosstalk violations, to sequentially placed and
routed layouts.
References
[1] J. Rijmenants. et al., "Ilac: An automated layout tool for analog cmos circuits," IEEE JSSC, vol. 24, April 1989.
[2] U. Choudhury, E. Malvasi and A. Sangiovanni-Vincentelli, "A routing methodology for analog integrated
circuits," in Proc. IEEE Int'l Conf. on CAD, November 1990.
[3] S. Mehranfar, "A technology-independent approach to custom analog cell generation," IEEE JSSC, March 1991.
[4] J. Cohn, D. Garrod, R. A. Rutenbar, and L. R. Carley, "KOAN/ANAGRAM II: new tools for device-level analog
placement and routing," IEEE JSSC, March 1991.
[5] K. Nakamura and L. R. Carley, "A current positive-feedback technique for efficient cascode bootstrapping," in
Proc. IEEE VLSI Circuits Symposium, June 1991.
[6] A. Frey, R. Mosteller and R. Suaya, "2-d compaction: A monte carlo method," in Proc. Conf. Advanced
Research in VLSI, MIT Press, 1987.
[7] D. Jepsen and C. Gelatt. Jr., "Macro placement by monte carlo annealing," in Proc. IEEE ICCD, Nov. 1984, pp.
495-498.
[8] C. Sechen, "Chip-planning, placement and global routing of macro/custom cell integrated circuits using
simulated annealing," in Proc. 25th ACM/IEEE Design Auto. Conf., June 1988, pp. 73-80.
[9] S. Gerez and 0. Herrmann, "Switchbox routing by stepwise reshaping," IEEE Trans. CAD, December 1989.
ICCAD91, Pages 400-403
A Fault Oriented Partial Scan Design Approach
Vivek Chickermane and Janak H. Patel
Center for Reliable and High Performance Computing, University of Illinois at Urbana-Champaign, Urbana, IL,
61801
Abstract
The recent availability of efficient sequential automatic test generators (ATGs) calls for a new
look at the scan selection problem. Highly efficient ATGs abort relatively few faults. It is
therefore possible to perform partial scan selection as a sequel to test generation. In this paper
a fault oriented partial scan approach is proposed, where the structural analysis of the circuit is
enhanced by focusing on dropped and sequentially untestable faults. The advantages of this
method are that the highest possible fault coverage can be achieved while limiting the cost of
scan to a user-specified limit. Experiments on ISCAS89 circuits show that with only 10-20%
scan, extremely high fault coverage can be obtained.
References
[1] E. Trischler, "Incomplete scan path with an automatic test generation methodology," Proc. Int' l. Test Conf.,
pp.153-162,1980.
[2] V. D. Agrawal, K. T. Cheng, D. D. Johnson, and T. Lin, "A complete solution to the partial scan problem,"
Proc. Int'l. Test Conf., pp. 44-51, 1987.
[3] H-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovanni-Vincentelli, "An incomplete scan design
approach to test generation for sequential machines," Proc. Int'l. Test Conf., pp. 730-734,1988.
[4] K. T. Cheng and V. D. Agrawal, "An economical scan design for sequential logic test generation," Proc. 19th
Int' l. Symp. on FaultTolerant Computing, pp. 28-35,1989.
[5] R. Gupta, R. Gupta, and M. A. Breuer, "BALLAST: A methodology for partial scan design," Proc. 19th Int'l.
Symp. on Fault-Tolerant Computing, pp. 118-125,1989.
[6] D. H. Lee and S. M. Reddy, "On determining scan flip-flops in partial scan designs," Proc. Int' l. Conference
on Computer-Aided Design, pp. 322-325, November 1990.
[7] V. Chickermane and J. H. Patel, "An optimization based approach to the partial scan design problem," Proc.
Int' l. Test Conf., pp. 377-386, September 1990.
[8] F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," Proc.
1989 Int'l. Symp. Circuits and Systems, pp. 1929-1934,1989.
[9] T. M. Niermann and J. H. Patel, "HITEC: a test generation package for sequential circuits," Proc. European
Conference on Design Automation, pp. 214-218, February 1991.
[10] M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable design. New
York: Computer Science Press, 1990.
[11] L. H. Goldstein, "Controllability/Observability analysis of digital circuits," IEEE Trans. Circuits and
Systems, vol. 26, pp. 685-693,1979.
[12] R. Tarjan, "Depth first search and linear graph algorithms," SIAM J. Comput., pp. 146-160, June 1972.
ICCAD91, Pages 404-407
Timing-Driven Partial Scan
Jing-Yang Jou, Kwang-Ting Cheng
AT&T Bell Laboratories, Murray Hill, NJ 07974
ABSTRACT
In this paper, a partial scan approach is presented, which aims at reducing both area overhead and
performance degradation caused by test logic. Given a target speed and an initial design that meets
the target, the algorithm selects a minimum set of scan flip-flops, if they exist, that (1) will break
all sequential cycles and (2) will not violate the performance requirement after the scan logic is
added. If such a set does not exist, the algorithm will find a set of scan flip-flops in which (1) all
sequential cycles are broken and (2) the total area increase caused by the scan logic and the
subsequent performance optimization is minimized. For circuits synthesized by automatic
synthesis tools, the authors suggest a new design flow, which selects/inserts the partial scan logic
after area optimization, but before performance optimization. For meeting both performance and
testability requirements, the new design flow produces designs with less area increase than the
traditional design flow, which considers testability and add test logic after performance
optimization. Experimental results on the ISCAS'89 sequential circuits are presented as well as
comparisons between the new method and the existing methods.
REFERENCES
1. E. Trishler, "Incomplete Scan Path with an Automatic Test Generation Methodology," Proc. Int'l Test Conference, pp. 153-162 (Nov. 1980).
2. V. D. Agrawal, K. T. Cheng, D. D. Johnson, and T. Lin, "Designing Circuits with Partial Scan," IEEE Design &
Test of Computers 5, pp. 8-15 (April 1988).
3. R. Gupta, R. Gupta, and M. A. Breuer, "The Ballast Methodology for Structured Partial Scan Design," IEEE
Trans. Computers 39-4, pp. 538-544 (April 1990).
4. K. -T. Cheng and V. D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Trans.
Computers 39-4, pp. 544-548 (April 1990).
5. D. H. Lee and S. M. Reddy, "On Determining Scan Flip-Flops in Partial-Scan Designs," Int'l Conf. on
Computer-Aided Design (ICCAD-90) (Nov. 1990).
6. F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. Int'l
Symp. on Circuits and Systems, pp. 1929-1934 (May 1989).
7. J. P. Fishburn, "A Depth-Decreasing Heuristic for Combinational Logic," Proc. 27th Design Automation Conf.,
pp. 361-364 (June 1990).
ICCAD91, Pages 408-411
Ordering Storage Elements in a Single Scan Chain
Rajesh Gupta
IBM East Fishkill
Zip 3A1 /306, Route 52
Hopewell Junction, NY 12533
Melvin A. Breuer
Electrical Engineering-Systems
University of Southern California
Los Angeles, CA 90089
Abstract
In serial scan designs, particularly those tested in a partitioned manner, the circuit test time is
influenced by the ordering of the storage elements in the scan chain. This paper describes a
procedure for constructing a single serial scan chain with the objective of minimizing the overall
test time. It uses a polynomial-time algorithm which results in an ordering of the storage
elements along with an indication of the degree of optimality of the solution.
References
[1] E. B. Eichelberger and T. W. Williams. A logic design structure for LSI testability. In Proceedings, 14th Design
Automation Conference, pages 462-467, June 1977.
[2] M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. W. H.
Freeman & Co., New York, 1990.
[3] Rajesh Gupta. Advanced Serial Scan Design, for Testability. PhD thesis, University of Southern California,
Department of Electrical EngineeringSystems, 1991.
[4] Rajesh Gupta, Rajiv Gupta, and M. A. Breuer. The BALLAST methodology for structured partial scan design.
IEEE Transactions on Computers, 39(4): 538-543, April 1990.
[5] S. Bhawmik. An Integrated CAD System for the Design of Testable VLSI Circuits. PhD thesis, Indian
Institute of Technology, Kharagpur, India, February 1988.
[6] R. E. Tarjan. Data Structures and Network Algorithms. SIAM, Philadelphia, 1983.
ICCAD91, Pages 414-417
Finite State Machine Decomposition By Transition Pairing
James Kukula, Srinivas Devadas
Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts
Institute of Technology
Abstract
Techniques for state assignment and finite state machine (FSM) decomposition have
been a subject of extensive investigation. However, efficient and versatile algorithms are
still not available.
We develop a method based on the premise that optimal state assignment corresponds to
finding an optimal general decomposition of a FSM. We motivate the use of this approach
for encoding State Transition Graphs extracted from logic-level descriptions. We use the
notion of t r a ns i t i on pa i r i ng to decompose a given FSM into several submachines such
that the state assignment problem for the submachines is simpler than the original problem,
attempting to not compromise the optimality of the solution. We give a new decomposition
algorithm that can decompose a FSM into an arbitrary number of submachines, and a new
constraint satisfaction algorithm to encode the different submachines.
We provide experimental results that validate the use of decomposition-based
techniques to solve the encoding problem.
References
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Transactions on Electronic Computers, volume EC-11, pages 466-472, August 1962.
[2] P. Ashar, S. Devadas, and A. R. Newton. Optimum and Heuristic Algorithms for a Problem of Finite State
Machine Decomposition. In IEEE Transactions on Computer-Aided Design, pages 296-310, March 1991.
[3] P. Ashar, A. Ghosh, S. Devadas, and A. R. Newton. Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. In Proceedings of the Int’l Conference on Computer-Aided Design, November
1990.
[4] S. Devadas, H-K. T. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli. MUSTANG: State Assignment of
Finite State Machines Targeting Multi-Level Logic Implementations. In IEEE Transactions on Computer-Aided
Design, pages 1290-1300, December 1988.
[5] S. Devadas and A. R. Newton. Decomposition and Factorization of Sequential Finite State Machines. In
IEEE Transactions on Computer-Aided Design, pages 1206-1217, November 1989.
[6] S. Devadas and A. R. Newton. Exact Algorithms for Output Encoding, State Assignment and FourLevel
Boolean Minimization. In IEEE Transactions on Computer-Aided Design, pages 13-27, January 1991.
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Sequential Circuits Using Combinational Techniques. In IEEE Transactions on Computer-Aided Design, pages
74-84, January 1991.
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ICCAD91, Pages 418-421
Don't Care Sequences and the Optimization of Interacting Finite State Machines
June-Kyung Rho, Gary Hachtel, Fabio Somenzi
Department of Electrical and Computer Engineering, University of Colorado at Boulder
Abstract
We explore the nature of incomplete specification in sequential circuits. We compare it to the
case of combinational circuits and propose new definitions and algorithms. We extend the
existing algorithms for input don't care sequences and provide a new theory for output don't care
sequences, based on the concept of information lossyness. The implementation of the proposed
techniques in a program called SEQUOIA (SEQUential Optimization of Interacting Automata)
shows that our approach is viable and effective.
References
[1] R. K. Brayton and F. Somenzi, "An exact minimizer for boolean relations," in Proceedings of the IEEE
International Conference on Computer Aided Design, (Santa Clara, CA), pp. 316-319, Nov. 1989.
[2] B. Lin and F. Somenzi, "Minimization of symbolic relations," in Proceedings of the IEEE International
Conference on Computer Aided Design, (Santa Clara, CA), pp. 88-91, Nov. 1990.
[3] M. Damiani and G. D. Micheli, "Synchronous logic synthesis: Circuit specifications and optimization
algorithms," in Proceedings of the IEEE International Symposium on Circuits and Systems, (New Orleans, LA),
pp. 2566-2570, May 1990.
[4] S. H. Unger, Asynchronous Sequential Switching Circuits. New York: John Wiley, 1969.
[5] S. Devadas, "Approaches to multi-level sequential logic synthesis," in Proceedings of the 26th Design
Automation Conference, (Las Vegas, NV), pp. 270-276, June 1989.
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Transactions on Computers, vol. C-21, pp. 1440-1443, Dec. 1972.
[7] F. C. Hennie, Finite-State Models for Logical Machines. New York: John Wiley, 1968.
ICCAD91, Pages 422-425
An Automatic Finite State Machine Synthesis Using Temporal Logic Decomposition
Keisuke Bekki*, Tohru Nagai*, Nobuhiro Hamada*, Tsuguo Shimizu**,
Noriharu Hiratsuka**, Kazumasa Shima***
*Hitachi Research Laboratory, Hitachi Ltd. 4026, Kuji, Hitachi, Ibaraki, 319-12, Japan
**Central Research Laboratory, Tokyo, Japan
***Systems Development Laboratory, Kawasaki, Japan
Abstract
Since conventional methods to synthesize a finite state machine assign binary codes to all the
non-redundant states, they do not exploit delay latches which are sometimes effective in
simplifying machine structure. We propose a new method to synthesize a finite state-machine
by applying a time shift operation on both inputs and outputs of the finite state machine. The
time shift operation is easily implemented by a delay latch. Therefore, the finite state machine
is decomposed into a smaller scale finite state machine and two combinational logic circuits
including the delay latches. One of the combinational logic circuits is attached to the input part
of the finite state machine and the other is attached to its output part. The algorithm is
evaluated for several benchmark examples of finite state machines, from which we conclude
that the finite state machine can be synthesized with 5% less hardware by applying the
proposed algorithm.
References
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No. 12, 1983.
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Trans. Industrial Electronics, Vol.37, No.1, pp. 1 - 6, Feb., 1990.
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Implementations, IEEE Trans. on CAD, Vol. 7, No. 12, pp. 1290 - 1299, Dec., 1987.
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Theory: ACM/IEEE, 26th Design Automation Conference, pp. 321-326, June 1989.
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ICCAD91, Pages 428-431
Algorithms for Three-Layer Over-the-Cell Channel Routing
Nancy D. Holmes
Dept. of CS
Western Michigan University
Kalamazoo, MI 49008
Naveed A. Sherwani
Dept. of CS
Western Michigan University
Kalamazoo, MI 49008
Majid Sarrafzadeh
Dept. of EE & CS
Northwestern University
Evanston, IL 60208
Abstract
In this paper, we present a new algorithm for three-layer, over-the-cell channel routing of
standard cell designs. The novelty of our approach lies in use of "vacant" terminals for
over-the-cell routing. Furthermore, we consider both the maximum cliques in the horizontal
constraint graph and longest paths in the vertical constraint graph as a basis for chosing the
nets to route over the cells. We prove that our net selection algorithm is guaranteed to
produce a solution within 68% of the optimum. The proposed algorithm has been
implemented and tested on several benchmark examples. For the entire PRIMARY 1
benchmark, we reduce the total routing height by 76% as compared to a 2-layer channel
router which leads to a 7% reduction in chip height.
References
[1] C. Chiang, M. Sarrafzadeh, and C. K. Wong, "A Global Router Based on Steiner Min-Max Trees," ICCAD-89,
pp. 2-5.
[2] J. Cong and C. L. Liu, "Over-the-Cell Channel Routing," Proc. International Conference on ComputerAided Design, ICCAD-88, pp. 80-83.
[3] J. Cong, B. Preas, and C. L. Liu, "General Models and Algorithms for Over-the-Cell Routing in Standard Cell
Design," Proc. 27th ACM/IEEE Design Automation Conference, IEEE-90, pp. 709-715.
[4] J. Cong, D. F. Wong, and C. L. Liu, "A New Approach to the Three Layer Channel Routing Problem," Proc.
Intl. Con f. on Computer-Aided Design, 1987, pp. 378-381.
[5] N. Holmes, N. Sherwani, and M. Sarrafzadeh, "New Algorithm for Over-the-Cell Channel Routing Using
Vacant Terminals," Proc. 28th ACM/IEEE Design Automation Conference, June 1991, pp. 126-131.
[6] N. Holmes, N. Sherwani, and M. Sarrafzadeh, "A New Three-Layer, Over-the-Cell Channel Router," Technical
Report #TR91-11, Dept. of Computer Science, Western Michigan University, Apr. 1991.
[7] T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout, Wiley, 1990.
[8] K.-W. Lee and C. Sechen, "A New Global Router for Row-Based Layout," Proceeding of IEEE International Conference on Computer-Aided Design, November 7-10, 1988, pp. 180-183.
[9] M.-S. Lin, H. W. Perng, C. Y. Hwang, and Y.L. Lin, "Channel Density Reduction by Routing Over the Cells,"
Proc. 28th ACM/IEEE Design Automation Conference, IEEE-91, pp. 120-125.
[10] T. G. Szymanski, "Dogleg Channel Routing is NP-Complete," IEEE Trans. on Computer Aided Design,
1985, Vol. CAD-4, pp. 31-41.
ICCAD91, Pages 432-435
A New Model for Over-the-Cell Channel Routing with Three Layers
Masayuki Terai, Kazuhiro Takahashi, Kazuo Nakajima, and Koji Sato
ASIC Design Engineering Center, Mitsubishi Electric Copration, Itami, Hyogo 664, Japan
Abstract
We propose an approach to an over-the-cell channel routing problem using a new model. The
model consists of two channels and the routing area over a cell row between them. Three and
two layers are available for routing in the channels and the over-the-cell routing area,
respectively. We decompose the problem into two phases: over-the-cell routing and channel
routing. We formulate the problem in the first phase as that of channel routing with additional
constraints. Based on this formulation, we present an efficient over-the-cell routing algorithm.
The effectiveness of our approach is demonstrated by our experimental results on sea-of-gates
array chips.
References
[1] J. Cong and C. L. Liu, "Over-the-cell channel routing," IEEE Trans. Computer-Aided Design of ICAS, vol.
CAD-9, pp. 408-418, April 1990.
[2] J. Cong, B. Preas, and C. L. Liu, "General models and algorithms for over-the-cell routing in standard cell
design," in Proc. 27th Design Automation Conf., June 1990, pp. 709-715.
[3] D. N. Deutsch and P. Glick, "An over-the-cell router," in Proc. 17th Design Automation Conf., June 1980, pp.
32-39.
[4] N. D. Holmes, N. A. Sherwani, and M. Sarrafzadeh, "New algorithm for over-the-cell channel routing using
vacant terminals," in Proc. 28th Design Automation Conf., June 1991, pp.126-131.
[5] H. E. Krohn, "An over-cell gate array channel router," in Proc. 20th Design Automation Conf., June 1983, pp.
665-670.
[6] M. S. Lin, H. W. Perng, C. Y. Hwang, and Y. L. Lin, "Channel density reduction by routing over the cells," in
Proc. 28th Design Automation Conf., June 1991, pp. 120-125.
[7] Y. Shiraishi and Y. Sakemi, "A permeation router," IEEE Trans. Computer-Aided Design of ICAS, vol. CAD-6,
pp. 462-471, May 1987.
[8] T. Yoshimura and E. S. Kuh, "Efficient algorithms for channel routing," IEEE Trans. Computer-Aided Design of
ICAS, vol. CAD-1, pp. 25-35, Jan. 1982.
[9] T. Yoshimura, "An efficient channel router," in Proc. 21st Design Automation Conf., June 1984, pp. 38-44.
ICCAD91, Pages 436-439
A Channel Router for Single Layer Customization Technology
Yachyang Sun*, Sai-keung Dong*, Shinji Sato** and C. L. Liu*
*Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA
**Fujitsu Laboratories Ltd., Atsugi, Kanagawa 243-01, Japan
Abstract
We propose an algorithm that produces optimal routings for channels in QCL technology [1,
5].
References
[1] K. Nakamura, Y. Enomoto, Y. Suehiro and K. Yamashita, "Advanced CMOS ASIC design methodologies,"
Regional Conference on Microelectronics and Systems, 1989.
[2] R. Raghavan and S. Sahni, "Single row routing," IEEE Trans. on Computers, vol. C-32, no. 3, pp. 209220, March 1983.
[3] R. Raghavan and S. Sahni, "The complexity of single row routing," IEEE Trans. on Circuits and Systems,
vol. CAS-31, no. 5, pp. 462-472, May 1984.
[4] J. D. Ullman, Computational Aspects of VLSI, Computer Science Press, Rockville, Md.,1984.
[5] K. Yamashita, Y. Enomoto, T. Sasaki, S. Kawahara, A. Kumagai, T. Sendo and A. Okada, "A quick
turnaround time ASIC `QCL series',", Institute of Electronics, Information and Communication Engineers
Technical Report, vol. 89, no. 93, pp. 65-69, June 1989. (In Japanese)
ICCAD91, Pages 440-443
A Hierarchical Methodology to Improve Channel Routing by Pin Permutation
Cliff Yungchin Hou and C. Y. Roger Chen
Department of Electrical and Computer Engineering, Syracuse University, Syracuse NY 13244-1240
Abstract
In standard cell design, many cell terminals and gates are permutable. Therefore, it is important
for a channel router to take advantage of this so as to obtain better results. A hierarchical
algorithm is presented to determine the proper positions of permutable gates and cell terminals
such that the results of the subsequent channel routing can be significantly improved.
Experimental results show that our proposed algorithm indeed considerably reduces the number
of tracks and vias.
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ICCAD91, Pages 446-449
A New Test Generation Method for Sequential Circuits
Dong Ho Lee
Department of Computer Science, University of Iowa, Iowa City, IA 52242
Sudhakar M. Reddy
Department of Electrical and Computer Engineering, University of Iowa, Iowa City, IA 52242
Abstract
In this paper, a new test generation method for synchronous sequential circuits is proposed.
Among the new ideas employed are: 1) efficiently maintaining path information using an
extended value system in forward time processing, and 2) efficiently enumerating cubes for
state justification in backward time processing. The experimental results show that the proposed method is effective in generating high coverage tests for sequential circuits.
Reference
[1] F. Brglez, D. Bryan, and K.Kozminski, "Combinational Profiles of Sequential Benchmark Circuits", ISCAS 89,
pp 1929-1934
[2] K.T Cheng and J.Y. Jou, "Functional Test Generation for Finite State Machines", ITC 1990, pp 162-168
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[6] R. Marlett, "An Effective Test Generation System for Sequential Circuits," 23rd DAC, pp 250-256
[7] H.T Ma, S. Devadas, A.R. Newton, and A. Sangiovanni-Vincentelli, "Test Generation for Sequential Circuits",
IEEE Trans. on CAD, Vol. 7, No. 10, October 1988, pp 1081-1093
[8] T. Niermann and J.H. Patel, "HITEC: A Test Generation Package for Sequential Circuits," European Design
Automation Conference 1991, pp 214-218
[9] P. Muth, "A Nine-Valued Circuit Model for Test Generation," IEEE Trans. on Computers, Vol C-25, No. 6, pp.
630-636, June, 1976
[10] J.P. Roth, "Diagnosis of Automata Failures: A Calculus and a Method," IBM Journal of Research and
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ICCAD91, Pages 450-453
Test Generation for Synchronous Sequential Circuits Based on Fault Extraction
Irith Pomeranz and Sudhakar M. Reddy
Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA 52242
Abstract
In this paper, we describe an efficient procedure for translating stuck-at faults in a gate level
implementation into state-table faults in a state-table description of the circuit. Based on this
fault procedure, a test generation approach is presented for stuck-at faults, which results in short
test sequences and achieves complete coverage of stuck-at faults. Experimental results are given
for both MCNC and ISCAS-89 benchmark circuits, to demonstrate the applicability of the
method.
References
[1] K-T. Cheng and J.Y. Jou, "Functional Test Generation for Finite State Machines", Intl. Test Conference,
1990, pp. 162-168.
[2] K. Sabnani and A.T. Dahbura, "A Protocol Test Generation Procedure", Computer Networks, 1988, pp. 285297.
[3] M.S. Abadir and H.K. Reghbati, "Functional Test Generation for Digital Circuits Described Using Binary
Decision Diagrams", IEEE Trans. Comput., April 1986, pp. 375-379.
[4] H-K.T. Ma, S. Devadas, A.R. Newton, and A. S-Vincentelli, "Test Generation for Sequential Circuits", IEEE
Trans. CAD of ICS, Oct. 1988, pp. 1081-1093.
[5] A. Ghosh, S. Devadas and A.R. Newton, "Test Generation for Highly Sequential Circuits ", ICCAD, Nov.
1989, pp. 362-365.
[6] I. Pomeranz and S.M. Reddy, "On Achieving Complete Fault Coverage for Sequential Machines Using the
Transition Fault Model", DAC, June 1991, pp. 341-346.
[7] I. Pomeranz and S.M. Reddy, "Test Generation for Synchronous Sequential Circuits Using Multiple
Observation Times", FTCS, June 1991, pp. 52-59.
ICCAD91, Pages 454-457
Increasing Fault Coverage for Synchronous Sequential
Circuits by the Multiple Observation Time Test Strategy
Irith Pomeranz, Sudhakar M. Reddy and Lakshmi N. Reddy
Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA 52242
Abstract
We consider the test generation problem for synchronous sequential circuits when fault-free
hardware reset is not available. The multiple observation time test strategy was previously
suggested to detect faults which are undetectable or difficult to detect by the conventional test
generation approach. However, the multiple observation time strategy was applied only to small
circuits, described by state tables. In the work presented here, application of the multiple
observation time test strategy is investigated for medium to large circuits. An existing test generation procedure, based on the conventional testing approach, is enhanced for the multiple
observation time strategy and experimental results are presented, demonstrating the effectiveness
and practicality of the multiple observation time strategy.
References
[1] M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Computer
Science Press, 1990.
[2] S. Mallela and S. Wu, "A Sequential Test Generation System", ITC, Sept. 1985, pp. 57-61.
[3] R. Marlett, "An Effective Test Generation System for Sequential Circuits", DAC, June 1986, pp. 250-256.
[4] T. Ogihara, S. Saruyama, and S. Murai, "Test Generation for Sequential Circuits using Individual Initial Value
Propagation", ICCAD, Nov. 1988, pp. 424-427.
[5] V. D. Agrawal, K. T. Cheng, and P. Agrawal, "CONTEST: A Concurrent Test Generator for Sequential Circuits"
DAC, June 1988, pp. 84-89.
[6] W-T. Cheng and T. J. Chakraborty, "Gentest: An Automatic Test Generation System for Sequential Circuits",
IEEE Computer, April 1989, pp. 43-49.
[7] T. P. Kelsey and K. K. Saluja, "Fast Test Generation for Sequential Circuits", ICCAD, Nov. 1989, pp. 354-357.
[8] H-K. T. Ma, S. Devadas, A. R. Newton, and A. S-Vincentelli, "Test Generation for Sequential Circuits", IEEE
T-CAD, Oct. 1988, pp. 1081-1093.
[9] W-T. Cheng, "The Back Algorithm for Sequential Test Generation", ICCD, Oct. 1988, pp. 66-69.
[10] K-T. Cheng and J. Y. Jou, "Functional Test Generation for Finite State Machines", ITC, 1990, pp. 162-168.
[11] A. T. Dahbura, M. U. Uyar, and C. W. Yau, "An Optimal Test Sequence for the JTAG/IEEE P1149.1 Test
Access Port Controller", ITC, 1989, pp. 55-62.
[12] T. Nierman and J. H. Patel, "HITEC: A Test Generation Package for Sequential Circuits", EDAC, Feb. 1991,
pp. 214-218.
[13] I. Pomeranz and S. M. Reddy, "Test Generation for Synchronous Sequential Circuits Using Multiple
Observation Times", FTCS, June 1991, pp. 52-59.
[14] I. Pomeranz and S. M. Reddy, "Classification of Faults in Synchronous Sequential Circuits", Technical Report
No. 3-27-1991, Electrical and Computer Eng. Dept., U. of Iowa, 1991.
ICCAD91, Pages 458-461
A Signal-driven Discrete Relaxation Technique for Architectural Level Test Generation
Jaushin Lee and Janak H. Patel
Center for Reliable and High-Performance Computing, University of Illinois at Urbana-Champaign, Urbana, IL
61801, U.S.A.
Abstract
In this paper, a new architectural level test generation methodology is proposed to solve both
data flow path conflicts and data flow value conflicts. For each pattern to be justified at a high
level, an instruction sequence and the under-determined system of non-linear equations are
derived based on pre-processing information. The solution of the system of equations are
calculated by a signal-driven discrete relaxation algorithm without making any high level
decisions. The test generation is performed by recursively assembling the instruction sequence
and solving the system of equations. This new test generation approach has been implemented,
and the tests of several microprocessors have been generated successfully. The results show that
this approach is effective and promising.
References
[1] T. Sarfert, R. Markgraf, E. Trischler, and M. Schulz, "Hierarchical test pattern generation based on high-level primitives," International Test Conference, pp. 470-479, Sept. 1989.
[2] R. Kunda, J. Abraham, and B. Rathi, "Speedup of test generation using high-level primitive," 27th ACM/IEEE
Design Automation Conference, pp. 580-586, June 1990.
[3] A. Ghosh, S. Devadas, and A. Newton, "Sequential test generation at the register-transfer and logic levels," 27th
ACM/IEEE Design Automation Conference, pp. 580-586, June 1990.
[4] B. Murray and J. Hayes, "Hierarchical test generation using precomputed tests for modules," International Test
Conference, pp. 221-229, Sept. 1988.
[5] P. Anirudhan and P. Menon, "Symbolic test generation for hierarchically modeled digital systems," International
Test Conference, pp. 461-469, Sept. 1989.
[6] J. Lee and J. Patel, "An architectural level test generator for a hierarchical design environment," 21th Symposium
on Fault-Tolerant Computing, pp. 44-51, June 1991.
[7] R. S. Varga, Matrix Iterative Analysis. New Jersey: Prentice-Hall, 1962.
[8] T. Niermann and J. Patel, "Hitec: A test generation package for sequential circuits," European Design
Automation Conference, pp. 214-218, Feb. 1991.
[9] T. Niermann, W. Cheng, and J. Patel, "Proofs: A fast memory efficient fault simulator for sequential circuits," 27th
Design Automation Conference, June 1990.
ICCAD91, Pages 464-467
Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms
S.-W. Jeong, B. Plessier, G. Hachtel, F. Somenzi
Dept. of Electrical and Computer Engineering, University of Colorado at Boulder
Abstract
We present an extension to binary decision diagrams (BDD's) that exploits the information
contained in the structure of the circuit to produce a compact, semi-canonical, representation.
The extended BDD's (XBDD's) retain many of the advantages of BDD's, while at the same
time allowing one to deal with larger circuits.
References
[1] P. Ashar, A. Ghosh, S. Devadas, and A. R. Newton. Combinational and sequential logic verification using
general binary decision diagrams. In International Workshop on Logic Synthesis, MCNC, Research Triangle
Park, NC, May 1991.
[2] K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient implementation of a BDD package. In Proceedings of
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Aided Design, pages 6-9, 1988.
[13] A. Sangiovanni-Vincentelli, H.-K. Ma, S. Devadas, and R. Wei. Logic verification algorithms and their
parallel implementation. In Proceedings of the 24th Design Automation Conference, July 1987.
ICCAD91, Pages 468-471
Probabilistic Design Verification
Jawahar Jain, Jim Bitner, Donald S. Fussell, Jacob A. Abraham
Computer Engineering Research Center, The University of Texas at Austin, Austin TX, 78712
Abstract
We present a novel method for verifying the equivalence of two Boolean functions. Each
function is hashed to an integer code by assigning random integer values to the input variables
and evaluating its integer-valued representation. The equivalence of two functions can be
verified with a very low probability of error. The probability of error can be exponentially
decreased by making multiple runs. Results indicate significant time and space advantages for
this method over deterministic techniques. Some functions known to require space (and time)
exponential in the number of input variables for deterministic verification require only
polynomial resources using our technique.
References
[1] C. L. Berman. Circuit width, register allocation, and reduced function graphs. IBM Research Report, RC 14129,
October 1988.
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C-35:677-690, August 1986.
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[4] M. Fujita, H. Fujisawa, and N. Kawato. Evaluation and improvements of Boolean comparison method based on
binary decision diagrams. ICCAD, pages 2-5, 1988.
[5] J. Jain, J. Bitner, J. Abraham, and D. Fussell. A scheme for probabilistic design verification. Submitted for
publication, 1991.
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[7] S. Malik, A. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli. Logic verification using binary decision diagrams in a logic synthesis environment. ICCAD, pages 6-9, 1988.
ICCAD91, Pages 472-475
Minimization of Binary Decision Diagrams Based on Exchanges of Variables
Nagisa Ishiura
Hiroshi Sawada *
Department of Information Systems Engineering
Osaka University, Suita Osaka 565, JAPAN
Shuzo Yajima *
* Department of Information Science
Kyoto University, Kyoto 606-01, JAPAN
We propose in this paper a new exact algorithm and gradual improvement methods of
minimizing binary decision diagrams (BDD's). In the exact minimization algorithm the
optimum order is searched by the exchanges of variables of BDD's based on the
framework of Friedman's algorithm. The use of BDD representation of a given function
and intermediate functions makes it possible to introduce pruning into our method, which
drastically reduces the computation cost. We also propose a greedy method and a
simulated annealing method based on exchanges of arbitrary two variables and a greedy
method based on exchanges of adjacent m variables for m = 3 and 4.
References
[1] K. S. Brace, R. L. Rudell and R. E. Bryant: "Efficient Implementation of a BDD Package", Proc. 27th
DAC, pp. 40-45 (Jun. 1990).
[2] R. E. Bryant: "Graph-Based Algorithms for Boolean Function Manipulation", IEEE Trans. Comput.,
vol. C-35, no. 8, pp. 677-691 (Aug. 1986).
[3] K. M. Butler, et al.: "Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered
Binary Decision Diagrams" Proc. 28th DAC, pp. 417-420 (Jun. 1991).
[4] S. J. Friedman and K. J. Supowit: "Finding the Optimal Variable Ordering for Binary Decision Diagrams", IEEE Trans. Comput. vol. C-39 no. 5 pp. 710-713 (May 1990).
[5] M. Fujita, H. Fujisawa and N. Kawato: "Evaluation and Improvements of Boolean Comparison Method
Based on Binary Decision Diagrams", Proc. ICCAD, pp. 2-5 (Nov. 1988).
[6] M. Fujita, Y. Matsunaga and T. Kakuda: "On Variable Ordering of Binary Decision Diagrams for the
Application of Multilevel Logic Synthesis", Proc. EDAC, pp. 50-54 (Feb. 1991).
[7] N. Ishiura and S. Yajima: "A Class of Logic Functions Expressible b a Polynomial-Size Binary Decision Diagram", Proc. Synthesis and Simulation Meeting and Int. Interchange (SASIMI '90), pp 48-54
(Oct. 1990).
[8] S. Malik, et al.: "Logic Verification Using Binary Decision Diagrams in a Logic Synthesis Environment", Proc. ICCAD-88, pp. 6-9 (Nov. 1988).
[9] S. Minato, N. Ishiura and S. Yajima: "Shared Binary Decision Diagram with Attributed Edges for
Efficient Boolean Function Manipulation", Proc. 27th DAC, pp. 52-57 (Jun. 1990).
ICCAD91, Pages 476-479
Variable Ordering and Selection for FSM Traversal
S.-W. Jeong, B. Plessier, G. D. Hachtel, F. Somenzi
Department of Electrical and Computer Engineering, University of Colorado, Boulder, CO 80309
Abstract
We consider the problem of variable ordering in algorithms for verification of finite state
machines for which the traversal is based on BDD representation and image computation via
implicit enumeration. We treat two separate BDD ordering problems: (1) minimization of the
representation of the next state function and the representation of the set of reachable states, (2)
A selection heuristic to reduce the complexity of the image computation problem by dynamic
selection of the implicit enumeration splitting variables. In both problems we present theoretical
results based on algebraic structure of the next state functions, heuristic ordering methods, and
favorable experimental results for problems with significant algebraic structure
References
[1] K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient implementation of a BDD package. In Proceedings of
the 27th Design Automation Conference, pages 40-45, June 1990.
[2] R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on
Computers, C-35(8):677691, August 1986.
[3] H. Cho, G. D. Hachtel, S.-W. Jeong, B. Plessier, E. Schwarz, and F. Somenzi. ATPG aspects of FSM
verification. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 134137, November 1990.
[4] O. Coudert, C. Berthet, and J. C. Madre. Verification of sequential machines using boolean functional
vectors. In L. Claesen, editor, Proceedings IFIP International Workshop on Applied Formal Methods for
Correct VLSI Design, pages 111-128, Leuven, Belgium, November 1989.
[5] S. Devadas, H.-K. T. Ma, and A. R. Newton. On the verification of sequential machines at differing levels
of abstraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 7:713-722,
June 1988.
[6] A. L. Dulmadge and N. S. Mendelsohn. Two algorithms for bipartite graphs. J. Soc. Indust. Appl. Math.,
11:183-193, March 1963.
[7] M. Fujita, H. Fujisawa, and N. Kawato. Evaluation and improvements of boolean comparison method
based on binary decision diagrams. In Proceedings of the IEEE International Conference on Computer Aided
Design, pages 2-5, November 1988.
[8] P. Goel. An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE
Transactions on Computers, C-30(3):215-222, 1981.
[9] J. Hartmanis and R. E. Stearns. Algebraic Structure Theory of Sequential Machines. Prentice-Hall,
Englewood Cliffs, NJ, 1966.
[10] B. Lin, H. Touati, and A. R. Newton. Don't care minimization of multi-level sequential logic networks. In
Proceedings of the IEEE International Conference on Computer Aided Design, pages 414-417, Santa Clara,
CA, November 1990.
[11] S. Malik, A. Wang, R. Brayton, and A. Sangiovanni-Vincentelli. Logic verification using binary
decision diagrams in a logic synthesis environment. In Proceedings of the IEEE International Conference on
Computer Aided Design, pages 6-9, 1988.
[12] R. Tarjan. Depth first search and linear graph algorithms. SIAM Journal of Computing, 1:146-160,1972.
[13] H. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit enumeration of finite
state machines using BDD's. In Proceedings of the IEEE International Conference on Computer Aided
Design, pages 130-133, November 1990.
[14] S. Yang. Logic synthesis and optimization benchmarks user guide version 3.0. Technical report,
Microelectronics Center of North Carolina, Research Triangle Park, NC, January 1991.
ICCAD91, Pages 482-485
A Convex Optimization Approach to Transistor Sizing for CMOS Circuits
Sachin S. Sapatnekar*, Vasant B. Rao*, and Pravin M. Vaidya**
* Coordinated Science Laboratory
University of Illinois at Urbana-Champaign
1101 W. Springfield Avenue, Urbana, IL 61801.
** Department of Computer Science
University of Illinois at Urbana-Champaign
1304 W. Springfield Avenue, Urbana, IL 61801.
Abstract
The transistor sizing problem of minimizing the circuit area, subject to the circuit delay being
less than a given specification is formulated as a convex programming problem. An efficient
convex programming algorithm is then used to obtain the exact solution. Experimental results on
a variety of circuits show that, for a given delay specification, this approach is able to produce
circuits with significantly smaller area when compared with TILOS [1,2].
REFERENCES
[1] J. P. Fishburn and A. E. Dunlop, "TILOS : A Posynomial Programming Approach to Transistor Sizing," Proc.
ICCAD-85, Santa Clara, CA, pp. 326-328, Nov 1985.
[2] A. E. Dunlop, J. P. Fishburn, D. D. Hill, and D. D. Shugard, "Experiments using Automatic Physical Design
Techniques for Optimizing Circuit Performance," Proc. 32nd Midwest Symposium on Circuits and Systems,
Urbana, IL, Aug 1989.
[3] J. Shyu, J. P. Fishburn, A. E. Dunlop, A. L. Sangiovanni-Vincentelli, "Optimization-Based Transistor Sizing,"
IEEE J. Solid-State Circuits, Vol 23, pp. 400-409, Apr 1988.
[4] P. M. Vaidya, "A New Algorithm for Minimizing Convex Functions Over Convex Sets," Proc. IEEE
Foundations of Computer Science, Oct 1989, pp. 332-337; also to appear in Mathematical Programming.
[5] S. Even, Graph Algorithms, Computer Science Press, 1979.
[6] J. Rubenstein, P. Penfield, and M. A. Horowitz, "Signal Delay in RC Tree Networks," IEEE Trans. Computer
Aided Design, Vol. CAD-2, No. 3, pp. 202-211, Jul 1983.
[7] N. Hedenstierna, and K. O. Jeppson, "CMOS Circuit Speed and Buffer Optimization" IEEE Trans. ComputerAided Design, Vol CAD-6, pp. 270-281, Mar 1987.
[8] J. G. Ecker, "Geometric Programming: Methods, Computations and Applications," SIAM Review" Vol. 22, No.
3, pp. 338-362, July 1980.
[9] D. G. Luenberger, Linear and Non-linear Programming, Addison-Wesley, 1984.
[10] G. H. Golub, and F. H. Van Loan, Matrix Computations, The Johns Hopkins University Press, 1989.
ICCAD91, Pages 486-489
A New Linear Placement Algorithm for Cell Generation
E. Auer*, W. Schiele**, and G. Sigl*
*Institute of Electronic Design Automation,
Techn. University of Munich
Arcisstr. 21, D-8000 Munich 2, Germany.
**Siemens AG,
Semiconductor Group, HL CAD 55
Balanstr. 73, D-8000 Munich 80, Germany.
Abstract
Many design styles used for automatic cell generation need a linear placement of their
components. This paper presents a new two-phase algorithm for that task. In a first step the
net length is globally minimized by quadratic programming with an iterative weight update.
Its results are as good as a minimization of the net length by linear programming but are
obtained by significantly shorter CPU-times. Then in a second step track count, net length,
and possibility of abutment between components are optimized simultaneously by means of a
branch and bound algorithm applied to local subproblems. A comparison to previously
published algorithms shows that the results of our algorithm are superior.
References
[1] H. Cai, "A Data Path Layout Assembler for High Performance DSP Chips," DAC, pp. 306-311, 1990.
[2] S. Huang and O. Wing, "Improved Gate Matrix Layout," Trans. CAD-8, pp. 875-889, Aug. 1989.
[3] C. Rowen and J. Hennessy, "Logic Minimization, Placement and Routing in SWAMI," CICC, pp. 235-238,
1985.
[4] K. Just, E. Auer, W. Schiele, and A. Schwaferts, "Palace: A Layout Generator for SCVS Logic Blocks," DAC,
pp. 468473, 1990.
[5] S. Yamada, H. Okude, and T. Kasai, "A Hierarchical Algorithm for One-Dimensional Gate Assignment Based
on Contraction of Nets," Trans. CAD-8, pp. 622-629, June 1989.
[6] M. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness.
San Francisco: W.H. Freeman and Co., 1979.
[7] Y.-S. Hong, K.-H. Park, and M. Kim, "A Heuristic Approach for Ordering the Columns in One-Dimensional
Logic Arrays," Trans. CAD-8, pp. 547-562, May 1989.
[8] T. Fujii, H. Horikawa, et al., "A Heuristic Algorithm for Gate 'Assignment in One-Dimensional Array
Approach," Trans. CAD-6, pp. 159-164, Mar. 1987.
[9] S. Kang, "Linear Ordering and Application to Placement," DAC, pp. 457-464, 1983.
[10] C.-K. Cheng, "Linear Placement Algorithms and Application to VLSI Design," in NETWORKS, vol. 17, pp.
439-464, John Wiley & Sons, 1987.
[11] M. A. Jackson and E. S. Kuh, "Performance-Driven Placement of Cell Based IC's," DAC, pp. 370-375, 1989.
[12] J. Kleinhans, G. Sigl, F. Johannes, and K. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming
and Slicing Optimization," T. CAD-10, pp. 356-365, Mar. 1991.
[13] T. Asano, "An Optimum Gate Placement Algorithm for MOS One-Dimensional Arrays," Journ. Digital
Syst., vol. IV, pp. 1-27, 1982.
[14] J. Bhasker and S. Sahni, "Optimal Linear Arrangement of Circuit Components," Journ. VLSI and Computer
Systems, vol. 2, no. 1-2, pp. 87-109, 1987.
[15] I. Cederbaum, "Optimal Backboard Ordering through the Shortest Path Algorithm," Trans. CAS-27, pp. 626632, Sep. 1974.
[16] R. Bar-Yehuda, J. A. Feldman, et al., "Depth-First-Search and Dynamic Programming Algorithms for Efficient
CMOS Cell Generation," Trans. CAD-8, pp. 737-743, July 1989.
[17] T. Ohtsuki, H. Mori, E. Kuh, T. Kashiwabara, and T. Fujisawa, "One-dimensional logic gate assignment and
interval graphs," Trans. CAS-26, pp. 675-684, Sep. 1979.
[18] S. Devadas and R. Newton, "Topological Optimization of Multiple-Level Array Logic," Trans. CAD-6, pp.
915-941, Nov. 1987.
[19] G. Sigl, K. Doll, and F. Johannes, "Analytical Placement: A Linear or a Quadratic Objective Function," DAC,
pp. 427-432, 1991.
[20] P. Gill, W. Murray, and M. Wright, Practical Optimization. Academic Press, 1981.
[21] Y. Shirai and J. Tsujii, Artificial Intelligence, Concepts, Techniques, and Applications. John Wiley &
Sons, 1984.
ICCAD91, Pages 490-493
Two-Dimensional Layout Synthesis for Large-Scale CMOS Circuits
Katsunori Tani*, Kyoichi Izumi**, Masahiko Kashimura*,
Tsuneo Matsuda*, and Takashi Fujii*
*
NEC Corporation, Kawasaki, Kanagawa, 211 Japan
**
NEC IC Microcomputer Systems Ltd., Kumamoto 861-22 Japan
Abstract
This paper proposes an algorithm to automatically generate a mask pattern from the logical
description of a large-scale CMOS circuit, i.e. "macro", consisting of up to several thousands
of transistors. The layout model considered here is a two-dimensional or "multi-row" model
which is composed by a set of rows of paired PMOS and NMOS transistors. The large-scale
layout synthesis is attained by combining an effective one-dimensional layout synthesis and a
standard cell layout algorithm in divide-and-conquer style. The algorithm is the first practical
one to be successfully applied to a large-scale circuit. Experimental results for MCNC
benchmark circuits are superior to the best results exhibited at Design Automation Conference
1990, especially when the scale of circuit becomes large. For a practical circuit, the proposed
algorithm yields an 18% smaller layout than the, conventional standard cell approach.
References
[1] E.S.Kuh and T.Ohtsuki, "Recent Advances in VLSI Layout," Proc. IEEE, 78, 2, pp.237-263 (1990).
[2] Y.Shiraishi, et al., "A High Packing Density Module Generator for CMOS Logic Cells," Proc. 25th DAC,
pp.439-444 (1988).
[3] D.G.Baltus and J.Allen, "SOLO: A Generator of Efficient Layouts from Optimized MOS Circuit
Schematics," Proc. 25th DAC, pp.445-452 (1988).
[4] C.J.Poirier, "EXCELLERATOR: Automatic Leaf Cell Layout Agent," Proc. ICCAD'87, pp.176-179 (1987).
[5] Y.-L.Lin and D.D.Gajski, "LES: A Layout Expert System," IEEE Trans. CAD, 7, 8, pp.868-876 (1988).
[6] S.Wimer, et al., "Optimal Chaining of CMOS Transistors in a Functional Cell," IEEE Trans. CAD, 6, 5,
pp.795-801(1987).
[7] D.N.Deutsch and P.Glick, "An Over-The-Cell Router," Proc.17th DAC, pp.32-39 (1980).
[8] M.Edahiro and T.Yoshimura, "New Placement and Global Routing Algorithms for Standard Cell Layouts,"
Proc. 27th DAC, pp.642-645 (1990).
[9] T.Yoshimura, "An Efficient Channel Router," Proc. 21st DAC, pp.36-44 (1984).
[10] S.Even, Graph Algorithms, Computer Science Press Inc., Potomac (1979).
[11] T.Uehara and W.M.vanCleemput, "Optimal Layout of CMOS Functional Arrays," IEEE Trans. Computers,
30, 5, pp.305-312 (1981).
[12] R.L.Maziasz and J.P.Hayes, "Layout Optimization of Static CMOS Functional Cells," IEEE Trans. CAD,
pp.708-719 (1990).
[13] M.A.Breuer, "Min-Cut Placement," J. of DA & FTC, 1, 4, pp.343-362 (1977).
[14] C.M.Fiduccia and R.M.Mattheyses, "A Linear-Time Heuristic for Improving Network Partitions,"
Proc.19th DAC, pp.175-181 (1982).
[15] K.S.Booth and G.S.Lueker, "Testing for the Consecutive Ones Property, Interval Graphs, and Graph
Planarity using PQ-tree Algorithms," J. of Computer and System Science, 13, pp.335379 (1976).
[16] H.H.Chen and E.S.Kuh, "Glitter: A Gridless Variable-Width Channel Router," IEEE Trans. CAD, 5, 4,
pp.459-465 (1986).
[17] D.D.Hill and B.Preas, "Benchmarks for Cell Synthesis," Proc. 27th DAC, pp.317-320 (1990).
ICCAD91, Pages 496-499
A Systematic Approach for Designing Testable VLSI Circuits
Sen-Pin Lin, Charles A. Njinda and Melvin A. Breuer
Department of Electrical Engineering – Systems, University of Southern California, Los Angeles, CA 90089-0781
Abstract
A systematic approach has been developed to provide designers with a set of testable
versions for a given design, ranging from the minimal test time solution to the minimal
area overhead solution. The designer thus has the flexibility to make the necessary trade-off
between area overhead and test time depending on the constraints of the design under
consideration. By employing an expert selection system developed previously, the system
can be extended to operate as an intelligent BIST design advisor. Experiments have been
performed on several circuits generated by MABAL, a high-level synthesis tool, to
demonstrate the performance of this approach.
Index terms: Built-in-self-test, synthesis for testability, test scheduling.
References
[1] M.S. Abadir and M.A. Breuer. A Knowledge-Based System for Designing Testable VLSI Chips. IEEE Design
& Test. Aug. 1985, pp. 56-68.
[2] B. Konemann, J. Mucha, and G. Zwiehoff. Built-In Logic Block Observation Technique. Digest of Papers
1979 Test Conf. Oct. 1979, pp. 37-41.
[3] F.J. Hill and G.R. Peterson. Introduction to Switching Theory and Logical Design. Wiley, New York,
1981.
[4] K.Hwang and F.A.Briggs. Computer Architecture and Parallel Processing. McGraw-Hill, New York,
1984.
[5] P.R. Chalasani, S. Bhawmik, A. Acharya and P. Palchaudhuri. Design of Testable VLSI Circuits with Minimum
Area Overhead. IEEE Trans. on Computer. Vol.C-38, Oct. 1989, pp.1460-1462.
[6] G. Craig, C. Kime, and K. Saluja. Test Scheduling and Control for VLSI Built-In Self-Test. IEEE Trans. on
Computers. Vol. C-37, Sept. 1988, pp. 1099-1109.
[7] K. Kucukcakar and A.C. Parker. MABAL: A Software Package for Module and Bus ALlocation, Int'l J. of
Computer Aided VLSI Design. Vol.2, 1990, pp. 419-426.
[8] S.P. Lin, C.A. Njinda and M.A. Breuer. A Systematic Approach for Designing Testable VLSI Circuits.
Tech. Rpt. CRI-91-18, Computer Research Inst. (EE Dept.) Univ. of Southern Calif, Los Angeles, July 1991.
ICCAD91, Pages 500-503
Design for Easily Applying Test Vectors to Improve Delay Fault Coverage
Edwin Hsing-Mean Sha, Liang-Fang Chao
Dept. of Computer Science, Princeton University, Princeton, NJ 08544
Abstract
It has been noted that arbitrary test pairs (v1, v2) can not be applied to a combinational part of a
finite state machine (FSM) using standard scan path design. The scan path design is a special
case of test machines which are designed to control and observe the object machine for detecting
faults. By studying state transition graphs, we propose a general framework, which is composed
of two stages, to solve this problem. Given a set of test pairs and a set of test machines, the first
stage is to select a test machine which has the maximum delay fault coverage. If the fault
coverage is not satisfactory, two approaches are proposed at the second stage. We show that
these two optimization problems in the second stage are both NP-hard. Three algorithms are
designed to solve these problems.
References
[1] V.D. Agrawal and K.-T. Cheng, " Test function specification in synthesis," Proc. of 27th Design Automation
Conference, June 1990, pp 235-240.
[2] S. Devadas and K. Keutzer, " Synthesis and optimization procedures for robustly delay-fault testable combinational
circuits, " Proc. of 27th Design Automation Conference, June 1990, pp 221-227.
[3] M.R. Garey and D.S. Johnson , Computers and Intractability: A Guide to the Theory of NP-completeness,
W.H. Freeman and Company, New York, 1979.
[4] C.T. Glover and M.R. Mercer, "A method of delay fault test generation," Proc. of 25th Design Automation
Conference, June 1988, pp 90-95.
[5] Y.K. Malaiya and R. Narayanaswamy, " Modeling and testing for timing faults in synchronous sequential circuits, "
IEEE Design and Test, 1984, pp 62-74.
[6] W. Mao and M.D. Ciletti, "Arrangement of latches in scan-path design to improve delay fault coverage," Proc. of
Int'l Test conference, September 1990, pp 387-393.
[7] S.M. Reddy et al., "An automatic test pattern generator for the etection of path delay faults, " Proc. of the Int'l
Conf. on Computer-Aided Design, Novermber 1987, pp 284-287.
[8] E. H.-M. Sha and L.-F. Chao, "Improving delay fault coverage for finite state machines by applying sufficient test
pairs," Technical Report, Dept. of Computer Science, Princeton University, in preparation.
[9] J.A. Waicukuski, E. Lindbloom, B. Rosen and V. Iyengar, "Transition fault simulation by parallel pattern single
fault propagation, " Proc. of Int'l Test conference, September 1986, pp 542-549.
ICCAD91, Pages 504-507
The Impedance Fault Model and Design for Robust Impedance Fault Testability
Mark D. Sloan, William A. Rogers and Srihari Shoroff
The University of Texas at Austin, Department of Electrical and Computer Engineering, Computer Engineering
Research Center, Austin, Texas 78712-1084
Abstract
Advanced submicron CMOS processes result in failure mechanisms that tend to be
increasingly analog in nature. They are not adequately covered by stuck at, on, or open
models. Furthermore, delay faults, spot defect models, and IDDQ approaches only
cover restricted subsets of the dominant failure mechanisms. The impedance fault
model forms a superset of all the above fault models while explicitly addressing the
analog nature of the failures. An associated design methodology for robust impedance
fault testability (DRIFT) provides robustly testable general structures with less area
overhead than other transistor level DFT techniques and negligible speed penalties.
DRIFT is especially well suited for gate array, standard cell, and synthesized designs.
References
[1] R. L. Wadsack, "Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits," Bell System
Technical Journal (May-June 1978),1449-1473.
[2] W. Maly, "Realistic Fault Modeling for VLSI Testing," Design Automation Conference (1987), 173-180.
[3] F. J. Furgeson, Inductive Fault Analysis of VLSI Circuits, Department of Electrical and Computer Engr.,
Carnegie Mellon University, October 1987, Ph.D. dissertation.
[4] P. Nag, W. Maly & P. Nigh., "Testing Oriented Analysis of CMOS ICs with Opens," Proceedings of the IEEE
International Conference on Computer-Aided Design (November 1988), 318-323.
[5] S. M. Reddy, M. K. Reddy & J. G. Kuhl, "On Testable Design for CMOS Logic Circuits," Proceedings of the
International Test Conference (1983),435-445.
[6] Dick L. Liu & Edward J. McCluskey, "Designing Switch Level Circuits for CMOS Testability ," IEEE
Transactions on Design and Test (1987 ), 42-49 .
[7] M. K. Reddy & S. M. Reddy, "Testable Realizations for FET Stuck Open Faults in CMOS Combinational Logic
Circuits," IEEE Transactions on Computers C-35 (August 1986), 742-754.
[8] M. K. Reddy, S. M. Reddy & P. Agrawal, "Transistor Level Test Generation for MOS Circuits," 22nd Design
Automation Conference (1985), 825-828.
[9] K. W. Chiang & Z. W. Vranesic, "On Fault Detection in CMOS Logic Networks," Proceedings of the Design
Autmation Conference (1983), 50-56.
[10] Y. K. Malaiya & S. Y. H. Su, "A New Fault Model and Testing Technique for CMOS Devices," Proceedings
of the International Test Conference (1982),25-34.
[11] N. K. Jha & J. A. Abraham, "Design of Testable CMOS Logic Circuits Under Arbitrary Circuit Delays," IEEE
Transactions on CAD (July 1985), 264-269.
[12] S. Kundu & S. M. Reddy, "On the Design of Robust Testable CMOS Combinational Logic Circuits," IEEE
(1988).
ICCAD91, Pages 510-513
Application of Boolean Unification to Combinational Logic Synthesis
Masahiro Fujita, Yutaka Tamiya
Fujitsu Laboratories Ltd., Kawasaki 211, Japan
Yuji Kukimoto
University of Tokyo, Tokyo 113, Japan
Kuang-Chien Chen
Fujitsu America Inc., San Jose 95134-2022, CA
Abstract
Boolean unification is an algorithm to obtain the general solution of a given Boolean equation.
Since the general solution provides a way to represent complete don't care sets in a functional
form, Boolean unification can be a powerful method when applied to logic synthesis. In this paper we present various applications of Boolean unification to combinational logic synthesis.
Three topics of combinational logic synthesis: redesign, multi-level logic minimization and
minimization of Boolean relations are discussed. All these problems can be uniformly formalized
as Boolean unification problems. Experimental results are also reported.
References
[1] D. Bostick, G. D. Hachtel, R. Jacoby, M. R. Lightner, P. Moceyunas, C. R. Morrison, and D. Ravenscroft. Boulder
optimal logic design system. In Proc. ICCAD, pages 62-65, November 1987.
[2] R. K. Brayton, R. Rudell, A. L. Sangiovanii-Vincentelli, and A. R. Wang. MIS: A multiple-level interactive logic
optimization system. IEEE Trans. on Computer-Aided Design, 6(6):1062-1081, November 1987.
[3] Randal E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Trans. on Computer, C35(8):677-691, August 1986.
[4] W. Buttner and H. Simonis. Embedding boolean expressions into logic programming. Journal of Symbolic Computation, 4:191-205, 1987.
[5] M. Fujita, T. Kakuda, and Y. Matsunaga. Redesign and automatic error correction of combinational circuits. In Proc.
IFIP Working Conference on Logic and Architectural Synthesis, May 1990.
[6] A. Ghosh, S. Devadas, and A. R. Newton. Heuristic minimization of boolean relations using testing techniques. In
Proc. ICCD, pages 277-281, September 1990.
[7] S. Minato, N. Ishiura, and S. Yajima. Shared binary decision diagrams with attributed edges for efficient boolean
function manipulation. In Proc. DAC, pages 52-57, June 1990.
[8] U. Martin and T. Nipkow. Unification in boolean rings. Journal of Automated Reasoning, 4:381-396, 1988.
[9] U. Martin and T. Nipkow. Boolean unification - the story so far. Journal of Symbolic Computation, 7:275293,1989.
[10] S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney. The transduction method - design of logic network based
on permissible functions. IEEE Trans. on Computer, 38(10):1404-1424, October 1989.
[11] H. Simonis. Test generation using the constraint logic programming language CHIP. In Proc. 6th International
Conference on Logic Programming, June 1989.
[12] F. Somenzi and R. K. Brayton. An exact minimizer for boolean relations. In Proc. ICCAD, pages 316-319,
November 1989.
[13] Y. Watanabe and R. K. Brayton. Heuristic minimization of boolean relations. In Proc. MCNC International
Workshop on Logic Synthesis, May 1991.
ICCAD91, Pages 514-517
Extracting Local Don't Cares for Network Optimization
Hamid Savoj, Robert K. Brayton
Department of EELS
University of California at Berkeley
Berkeley, CA 94720
Herve J. Touati
DEC PRL
85, avenue Victor Hugo
92563 Rueil-Malmaison Cedex - France
Abstract
An algorithm for computing local don't cares (in terms of immediate fanin variables) at each
intermediate node of a Boolean network is presented. These don't cares can be directly used for the
simplification of each node by a two-level minimizer. The simplification is relatively fast and the
optimized circuits are 100% testable in most cases. This method is more powerful than previous
ones developed for node simplification because it computes almost the full local don't care set at
each node using image computation techniques [3]. External don't cares are used effectively and
there is no restriction on how these are represented because BDD's are used to translate them into
local don't cares. This algorithm has been implemented in Sequential Interactive Logic Synthesis
System (SIS) and we present experimental results that show the effectiveness of the new algorithm
on benchmark circuits with and without external don't cares.
References
[ 1 ] R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. MIS: Multiple-Level Logic Optimization
System. In IEEE Transactions on Computer Aided Design o f Integrated Circuits and Systems, pages 1062-1081,
November 1987.
[2] R. E. Bryant. Graph Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, C35(8):677-691, August 1986.
[3] O. Coudert, C. Berthet, and J. C. Madre. Verification of Sequential Machines Based on Symbolic Execution. In
Proceedings of the Workshop on Auiomatic Verification Methods for Finite State Systems, Grenoble, France, 1989.
[4] B. Lin, H. Touati, and R. Newton. Don't Care Minimization of MultiLevel Sequential Logic Networks. In IEEE
International Conference on Computer-Aided Design, November 1990.
[5] S. Malik, A. R. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli. Logic Verification Using Binary Decision
Diagrams in a Logic Synthesis Environments. In IEEE International Conference on Computer Aided Design, pages 69, November 1988.
[6] A. Saldanha, A. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli. Multi-Level Logic Simplification using
Don't Cares and Filters. In Design Automation Conference, 1989.
[7] H. Savoj and R. Brayton. The Use of Observability and External Don't Cares for the Simplification of Multi-Level
Networks. In 27th ACM/IEEE Design Automation Conference, Orlando, June 1990.
[8] H. Touati, H. Savoj, B. Lin, R. Brayton, and A. Sangiovanni-Vincentelli. Implicit State Enumeration of Finite State
Machines using BDD's. In IEEE International Conference on Computer Aided Design, November 1990.
ICCAD91, Pages 518-521
Observability Relations and Observability Don't Cares
Hamid Savoj, Robert K. Brayton
Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA
94720
Abstract
The observability relation O(x, z) (as defined by Cemy [4]) or Boolean relation (discussed in [3])
provides a description of all the flexibility one has in implementing a Boolean network N. We propose to represent and use this flexibility in a logic synthesis system by adding a single output node
to the Boolean network N. The node function for the new node is O(x, z). The newly constructed
network N' (called the observability network) has only one output and computes 1 for every input
x. We show that the observability don't cares (ODC's) for a node yi in N' provide the maximum
flexibility for implementing yi and subsume the flexibility obtained for yi in N even with don't cares
provided at each output. This gives rise to new methods for computing complete ODC's for N' and
hence for N.
References
[1] K. Bartlett, R. K. Brayton, G. D. Hachtel, R. M. Jacoby, C. R. Morrison and R. L. Rudell, A. SangiovanniVincentelli, and A. R. Wang. Multi-level Logic Minimization Using Implicit Don't Cares. In IEEE Transactions on
CAD, pages 723-740, June 1988.
[2] R. K. Brayton, G. D. Hachtel, C.T. McMullen, and A.L. SangiovanniVincentelli. Logic Minimization Algorithms
for VLSI Synthesis. Kluwer Academic Publishers, 1984.
[3] R. K. Brayton and F. Somenzi. Boolean Relations and the Incomplete Specification of Logic Networks. In VLSI' 89,
August 1989.
[4] E. Cerny. An approach to unified methodology of combinational switching circuits. IEEE Transactions on
Computers, 27(8), 1977.
[5] M. Damiani and G. De Micheli. Observability Don't Care Sets and Boolean Relations. In IEEE International
Conference on ComputerAided Design, pages 502-505, November 1990.
[6] M. Damiani and G. De Micheli. Derivation of Don't Care Conditions by Perturbation Analysis of Combinational
Multiple-Level Logic Circuits. In International Workshop on Logic Synthesis, May 1991.
[7] M. Fujita, Y. Tamiya, Y. Matsunaga, and K.C. Chen. Multi-Level Logic Synthesis for Boolean Relations.
Submitted to VLSI,1991.
[8] A. Ghosh, S. Devadas, and A. R. Newton. Heuristic Minimization of Boolean Relations Using Testing Techniques.
In IEEE international Conference on Computer Design, Cambridge, September 1990.
[9] S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney. The Transduction Method - Design of Logic Networks
Based on Permissible Functions. In IEEE Transactions on Computers, October 1989.
[10] H. Sato, Y. Yasue, F. Matsunaga, and M. Fujita. Boolean Resubstitution with Permissible Functions and Binary
Decision Diagrams. In 27th ACMIIEEE Design Automation Conference, pages 284-289, Orlando, June 1990.
[11] H. Savoj and R. Brayton. The Use of Observability and External Don't Cares for the Simplification of MultiLevel Networks. In 27th ACM/IEEE Design Automation Conference, Orlando, June 1990.
[12] H. Savoj and R. K. Brayton. Observability Relations and Observability Don't Cares. ERL Memo, UC Berkeley,
1991
[13] H. Savoj, H. Touati, and R. K. Brayton. Extracting Local Don't Cares for Network Optimization. In IEEE
International Conference on Computer Aided Design, November 1991.
ICCAD91, Pages 524-527
Minimizing Channel Density by Shifting Blocks and Terminals
Yang Cai and D.F. Wong
Department of Computer Sciences, University of Texas at Austin, Austin, Texas 78712
Abstract
We study in this paper the problem of minimizing channel density by shifting the blocks that
form the sides of the channel and the terminals on the boundary of each block. Several special
cases of this problem have been investigated, but no polynomial time algorithm was known for
the general case. We present a polynomial time optimal algorithm for solving this problem. For
long channels, we propose heuristic approaches to speed up our algorithm. Extensions as well as
applications of our algorithm to detailed routing in building-block layout design are also
discussed. Preliminary experimental results are very promising. Substantial reductions in routing
area were obtained in moderate computation time.
References
[1] M. Burstein and R. Pelavin, "Hierarchical channel router", INTEGRATION, the VLSI journal, vol. 1, 2138,1983.
[2] H. Cai and P. Dewilde, "Attacking the problem of minimizing channel density", ISCAS-86, 353-356.
[3] Y. Cai and D.F. Wong, "A new method for detailed routing in building-block layout design", Manuscript,
1991.
[4] Y Cai and D.F. Wong, "Minimizing channel density by shifting blocks and terminals", Manuscript, 1991.
[5] Y Cai and D.F. Wong, "Optimal channel pin assignment", to appear in IEEE Trans. on CAD, 1991.
[6] D.N. Deutsch, "A dogleg channel router", DAC-76, 425-433.
[7] C.M. Fiduccia and R.L. Rivest, "A greedy channel router", DAC-82, 418-424.
[8] M.R. Garey and D.S. Johnson, Computers and intractability: a guide to the theory of NP-completeness,
W.H. Freeman & Co., New York, 1979.
[9] I.S. Gopal, D. Coppersmith and C.K. Wong, "Optimal wiring of movable terminals", IEEE Trans. on
Comp., vol. C-32, 845-858,1983.
[10] P. Groeneveld, "On global wire ordering for macro-cell routing", DAC-89,155-160.
[11] A. Hashimoto and J. Stevens, "Wire routing by optimizing channel assignment within large apertures",
DAW-71, 155-163.
[12] A.S. LaPaugh and R.Y. Pinter, "On minimizing channel density by lateral shifting", ICCAD-83,121-122.
[13] J. Reed, A. Sangiovanni-Vincentelli, and M. Santomauro, "A new symbolic channel router: YACR2",
IEEE Trans. on CAD, vol. CAD-4.,208-219,1985.
[14] H. Shin and A. Sangiovanni-Vincentelli, "MIGHTY: a 'ripup and reroute' detailed router", ICCAD-86, 25.
[15] L. Stockmeyer, "Optimal orientation of cells in slicing floorplan designs", Information and Control, vol. 59,
91-101, 1983.
[16] T.G. Szymanski, "Dogleg channel routing is NP-complete", IEEE Trans. on CAD, vol. CAD-4,3141,1985.
[17] T.-C. Wang and D.F. Wong, "An optimal algorithm for floorplan area optimalization", DAC-90,180-186.
[18] S. Wimer, I. Koren and I. Cederbaum, "Optimal aspect ratio of building blocks in VLSI", IEEE Trans. on
CAD, CAD-8, 139-145,1989.
[19] T. Yoshimura and E.S. Kuh, "Efficient algorithms for channel routing", IEEE Trans. on CAD, vol. CAD-1,
25-35,1982.
ICCAD91, Pages 528-531
The Crossing Distribution Problem
Malgorzata Marek-Sadowska
ECE Department
University of California
Santa Barbara, CA 93106
Majid Sarrafzadeh
Department of EE & CS
Northwestern University
Evanston, IL 60208
Abstract
In this paper we study the problem of "properly” distributing the set of crossings (i.e.,
intersection of nets), of a given global routing, among the regions. Each region is assigned a
quota, being the maximum number of crossings allowed in that region, which depends on its
area and its complexity (e.g., the number of nets going through it and the number of
terminals it contains). The crossing distribution problem (CDP) is to find a net ordering at
each boundary as to minimize the total number of crossings and to satisfy the quotas. We
propose an 0(mn2 + mξ3/2) time algorithm for CDP, where m is the number of modules, n is
the number of nets, and ξ is the number of crossings.
References
[1] H. Cai and P. Dewilde, "Attacking the Problem of Minimizing Channel Density," Proceedings of
International Symposium on Circuits and & Systems, 1986, pp. 353-356.
[2] N. P. Chen, C. P. Hsu, E. S. Kuh, C. C. Chen, and M. Takahashi. "BBL: A Building Block Layout System for
Custom Chip Design," Proceedings of International Conference on Computer-Aided Design, 1983, pp.
40-41.
[3] W. M. Dai, T. Asano, and E. S. Kuh, "Routing Region Definition and Ordering Scheme for Building Block
Layout," IEEE Transactions on Computer-Aided Design, Vol. CAD-4, No. 3, July 1985, pp. 189-197.
[4] P. Groenveld, "On Global Wire Ordering for Macro-Cell Routing," Proceedings of Design Automation
Conference, 1989, pp. 155-160.
[5] H. C. Hsieh et al, "Third-Generation Architecture Boosts Speed and Density of FieldProgrammable Gate
Array", Proceedings of Custom Integrated Circuits Conference, 1990, pp. 31.2.1- 31.2.7.
[6] E. S. Kuh and M. Marek-Sadowska, "Global Routing," in Layout Design and Verification, T. Ohtsuki
(Editor), Elsevier Science Publishing, 1986.
[7] U. Lauther, "A Min-Cut Placement Algorithm for General Cell Assemblies based on a Graph Representation",
Proceedings of 16th Design Automation Conference, June 19879, pp. 1-10.
[8] T. Ohtsuki, Editor, Layout Design and Verification, Amsterdam: North Holland, 1986.
[9] R. Pinter, "Optimal Routing in Rectilinear Channel", A chapter in The Impact of Layer Assignment
Methods on Layout Algorithms for Integrated Circuits, Ph.D. thesis, M.I.T., August 1982.
[10] R. E. Tarjan, Network Optimization, SIAM, 1983.
ICCAD91, Pages 532-535
On Topological Via Minimization and Routing
Moazzem Hossain and Naveed A. Sherwani
Department of Computer Science, Western Michigan University, Kalamazoo, MI 49008
Abstract
We consider topological via minimization problem in a bounded region. The problem is
known to be NP-complete. An approximation algorithm is proposed for this problem, which
solves the two-layer topological via minimization problem in a bounded region with at most
1/4 m* more vias than the optimal number of vias, where m* is the size of the maximum
two-planar subset of nets for the given problem. A graph theoretic heuristic algorithm is also
proposed to obtain a geometric routing from a topological solution.
References
[1] A. Abdullah, and S. Sastry, "Topological Via Minimization and Routing," In Proc. of 1st Great Lakes Sym. on
VLSI, Kalamazoo, MI, March 1-2, 1991.
[2] J. Cong, and C. L. Liu, "On the k-Layer Planar Subset and Via Minimization Problems," 1990 European
Design Automation Conference.
[3] S. Haruyama, D. Wong, and D. Fussell, "Topological Channel routing," Proc. ICCAD,1988, pp. 406-409.
[4] M. Hossain, and N. A. Sherwani, "On Topological Via Minimization and Routing," Technical report, No.
TR/91-13, Department of Computer Science, WMU.
[5] Chi-Ping Hsu, "Minimum Via Topological Routing," IEEE Trans. on CAD, Vol CAD-2, No. 4, pp. 235-246,
October 1983.
[6] R. D. Lou, M. Sarrafzadeh and D. T. Lee, "An Optimal Algorithm for the Maximum Two-chain Problem," In
Proceedings of First SIAM-ACM Conf. on Discrete Algorithms, San Francisco, CA, January 1990.
[7] M. Marek-Sadowska, "An Unconstrained Topological Via Minimization," IEEE Trans. on CAD, Vol. 3, No. 3,
July 1984, 184-190.
[8] C. S. Rim, T. Kashiwabara and K. Nakajima, "Exact Algorithms for Multilayer Topological Via Minimization",
IEEE Trans. on CAD, Vol. 8, No. 11, pp.1165-1184, November 1989.
[9] M. Sarrafzadeh and D. T. Lee, "A New Approach to Topological Via Minimization," IEEE Trans. on CAD,
Vol. 8, No. 8, pp. 890-900, Aug. 1989.
[10] M. Stallmann, T. Hughes, and W. Liu, "Unconstrained Via Minimization for Topological Multilayer Routing,"
IEEE Trans. on CAD, Vol. 9, No. 9, pp. 970-980, September 1990.
[11] K. J. Supowit, "Finding a Maximum Planar Subset of a Set of Nets in a Channel," IEEE Transactions on
CAD, Vol. CAD-6, No. 1, Jan. 1987.
ICCAD91, Pages 536-539
Switchbox Steiner Tree Problem in Presence of Obstacles
S. Miriyala, J. Hashmi, and N. Sherwani
Department of Computer Science, Western Michigan University, Kalamazoo, MI 49008
Abstract
In this paper, we consider a problem related to global routing of multiterminal nets in VLSI
layout. We investigate the problem of finding minimum Steiner tree in presence o f obstacles
when the terminals lie on the boundary of a rectangle (RSTO) and present two results. Our
first contribution is an exact solution for finding the shortest rectilinear Steiner tree in
presence of an obstacle when the terminals lie on the boundary of a rectangle. Secondly, we
give an approximation algorithm for RSTO in presence of k obstacles. We show that our
algorithm has a tight performance bound. We also give a heuristic algorithm which produces
solutions very close to the optimal.
References
[1] P. K. Agarwal, and M. T. Shing, "Algorithms for Special Cases of Rectilinear Steiner Trees: 1. Points on the
Boundary of a Rectilinear Rectangle," Networks, Vol. 9, No. 20, 1990, pp. 453-485.
[2] A.V. Aho, M. R. Gary, and F. K. Hwang, "Rectilinear Steiner Trees: Efficient special case algorithms,"
Networks, Vol. 7, 1977, pp. 37-58.
[3] M. Bern, "Faster Exact Algorithms for Steiner Trees in Planner Networks," Networks Vol. 20, 1990, pp. 109120.
[4] J. P. Cohoon, D. S. Richards, and J. S. Salowe, "An Optimal Steiner Tree Algorithm for a Net Whose Terminals
Lie on the Perimeter of a Rectangle," IEEE Trans. on Comp.-Aided Design, Vol. 9, No. 4, April 1990, pp. 398407.
[5] M. R. Garey, and D. S. Johnson, "The Rectilinear Steiner Tree Problem is NP-Complete," SIAM Journal of
Applied Math., Vol. 32, No. 4, Jan. 1977, pp. 37-58.
[6] D. Tritsch, "Interconnecting Networks in the Plane: The Steiner Case," Networks Vol. 20, 1990, pp. 93-108.
[7] M. Hanan, "On Steiner's Problem with Rectilinear Distance," SIAM Journal of Applied Mathematics, Vol.
14, No. 2, Feburary 1966, pp. 255-265.
[8] J-M. Ho, G. Vijayan, and C. K. Wong, "Constructing the Optimal Rectilinear Steiner Tree Derivable from a
Minimum Spanning Tree," Proceedings of IEEE Inter. Confer. on Comp. Aided Design, Nov. 1989, pp. 5-8.
[9] P. J. de Rezende, D. T. Lee, and Y. F. Wu, " Rectilinear Shortest Paths in the Presence of Rectangular Barriers,"
in Proc. ACM. Sympo. Computation Geometry (Baltimore, MD.), 1987, pp. 204-213.
[10] F. K. Hwong, "On Steiner Minimal Trees with Rectilinear Distance," SIAM J. of Appl,. Math., Vol. 30, No. 1,
Jan. 1976, pp. 104-114.
[11] J. Jájá, and S. Wu, " On Routing Two-Terminal Nets in the Presence of Obstacles," IEEE Trans. on Comp.Aided Design, Vol. 8, No. 5, May 1989, pp. 563-570.
[12] S. Miriyala, J. Hashmi, and N. Sherwani, "Switch-box Routing," TR- 91, Department of Computer Science,
WMU.
ICCAD91, Pages 542-545
PARIS: A Parallel Pattern Fault Simulator for Synchronous Sequential Circuits
Nikolaus Gouders
University of Duisburg, Electrical Engineering, Dept. of Data Processing, Bismarckstr. 81,
W-4100 Duisburg 1, Germany
Reinhard Kaibel
Siemens Nixdorf Information Systems, Information Systems Plant, Techniques Division - WI T 24, Pontanusstr. 55,
W-4790 Paderborn, Germany
Abstract
In this paper, we describe PARIS, a parallel pattern fault simulator for synchronous sequential
circuits. PARIS is based on the well known approach of parallel pattern single fault propagation
for combinational circuits [121 and features several new techniques. Every single pattern packet
is simulated by an iterative, event-driven method. Heuristic look-ahead of signal values
minimizes the number of events that must be tracked. Clever circuit partitioning prevents
multiple evaluation of the feedback free parts of the circuit, thus further reducing the required
simulation effort. Our experiments show that PARIS runs at a substantially higher asymptotic
speed compared with a state-of-the-art fault simulator for synchronous sequential circuits.
References
[1] K.J. Antreich, M.H. Schulz, "Fast Fault Simulation in combinational circuits," Proc. Int'l Conf. on ComputerAided Design, pp. 330-333,1986.
[2] Z. Barzilai, J.L. Carter, B.K. Rosen, J.D Rutledge, "HSS - A High-Speed Simulator," IEEE Transact. on
Computer-Aided Design, pp. 601-617, July 1987
[3] B. Becker, R. Hahn, R. Krieger, U. Sparmann, "Structure Based Methods for Parallel Pattern Fault Simulation in
Combinational Circuits," Proc. Europ. Design Automation Conf., pp. 497-502,1991.
[4] F. Brglez, D. Bryan, K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. Int'l
Symp. Circ. and Systems, pp.1929-1934,1989.
[5] F. Brglez, H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in
Fortran," Proc. Int'l Symp. Circ. and Systems, Special Session on ATPG and Fault Simulation, 1985.
[6] W. Cheng, J.H. Patel, "PROOFS: A Super Fast Fault Simulator for Sequential Circuits," Proc. Europ. Design
Aut. Con,:, pp. 475-479,1990.
[7] P. Goel, "Test Generation Costs Analysis and Projections," Proc. IEEE Design Automation Conf, pp. 7784,1980.
[8] S.J. Hong, "Fault Simulation Strategy for Combinational Logic Networks," Proc. Fault Tolerant Computing
Symposium, pp. 96-99,1978.
[9] R. Kaibel, "Automatische Testgenerierung fur kombinatorische Schaltungen," Ph.D. Thesis, University of
Duisburg, 1991.
[10] J.P. Roth, W.G. Bouricious, P.R. Schneider, "Programmed Algorithms to Compute Tests to Detect and
Distinguish Between Failures in Logic Circuits," IEEE Trans. Electron.. Comput., Vol. EC-16, No. 5, pp. 567-580,
Oct. 1967.
[1l] B. Underwood, J. Ferguson, "The Parallel-Test-Detect Fault Simulation Algorithm," Proc. Int'l Test Conference,
pp. 712-717,1989.
[12] J.A. Waicukauski, E.B. Eichelberger, D.O. Forlenza, E. Lindbloom, T. McCarthy, "Fault Simulation for
Structured VLSI," VLSI Systems Design, pp. 20-32, Dec. 1985.
ICCAD91, Pages 546-549
Methods for Reducing Events in Sequential Circuit Fault Simulation
Elizabeth M. Rudnick
Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL 61801
Thomas M. Niermann
Sunrise Test Systems Inc, Sunnyvale, CA 94086
Janak H. Patel
Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL 61801
Abstract
Methods are investigated for reducing events in sequential circuit fault simulation by
reducing the number of faults simulated for each test vector. Inactive faults, which are
guaranteed to have no effect on the output or the next state, are identified using local
information from the fault-free circuit in one technique. In a second technique, the StarAlgorithm is extended to handle sequential circuits and provide global information about
inactive faults, based on the fault-free circuit state. Both techniques are integrated into the
PROOFS synchronous sequential circuit fault simulator. An average 28% reduction in
faulty circuit gate evaluations is obtained for the 19 ISCAS-89 benchmark circuits studied
using the first technique, and 33% reduction for the two techniques combined. Execution
times decrease by an average of 17% when the first technique is used. For the largest
circuits, further improvements in execution time are made when the Star-Algorithm is
included.
References
[1] E. G. Ulrich and T. Baker, "The Concurrent Simulation of Nearly Identical Digital Networks," Proc. 10th Design
Automation Workshop, Vol. 6, June 1973, pp. 145-150.
[2] P. Goel, H. Lichaa, T. E. Rosser, T. J. Stroh, and E. B. Eichelberger, "LSSD Fault Simulation Using Conjunctive
Combinational and Sequential Methods," Proc. Intn'l Test Conf., November 1980, pp. 371-376.
[3] D. B. Armstrong, "A Deductive Method for Simulating Faults in Logic Circuits," IEEE Trans. Comput., Vol. C21,
No. 5, May 1972, pp. 464-471.
[4] T. M. Niermann, W. -T. Cheng, and J. H. Patel, "PROOFS: A Fast, Memory Efficient Sequential Circuit Fault
Simulator," Proc. 27th Design Automation Conf., June 1990, pp. 535-540.
[5] W. -T. Cheng and M. -L. Yu, "Differential Fault Simulation - A Fast Method Using Minimal Memory," Proc. 26th
Design Automation Conf., June 1989, pp. 424-428.
[6] S. Seshu, "On An Improved Diagnosis Program," IEEE Trans. Electron. Comput., Vol. EC-14, February 1965,
pp. 76-79.
[7] S. B. Akers, B. Krishnamurthy, S. Park, and A. Swaminathan, "Why is Less Information From Logic Simulation
More Useful in Fault Simulation?" Proc. Intn'l Test Conf., September 1990, pp. 786-800.
[8] F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Intn'l Symposium of Circuits & Systems, May 1989, pp. 1929-1934.
[9] W. -T. Cheng and S. Davidson, "Sequential Circuit Test Generator (STG) Benchmark Results," Intn'l Symposium
of Circuits & Systems, May 1989, pp. 1938-1941.
ICCAD91, Pages 550-553
Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets
Noriyuki Takahashi, Nagisa Ishiura*, Shuzo Yajima
Department of Information Science, Kyoto University, Kyoto 606-01, JAPAN
*Department of Information Systems Engineering, Osaka University, Suita, Osaka 565, JAPAN
Abstract
We propose a new fault simulation technique for multiple faults. In order to handle a huge
number of multiple faults, sets of multiple faults are represented by Boolean functions, in which
shared binary decision diagrams are used as an internal representation of Boolean functions. We
also propose a fault dropping method, prime fault dropping, which is used efficiently to execute
multiple fault simulation. We succeeded in simulation of 39 million double faults of the circuit of
2300 gates with about 20MByte storage.
References
[1] M. A. Breuer and A. D. Friedman, Diagnosis & Reliable Design of Digital Systems, Computer Science Press,
1976.
[2] J. L. A. Hughes "Multiple Fault Detection Using Single Fault Test Sets," IEEE Trans. Computer-Aided
Design, Vol. CAD-7,1,1988.
[3] M. Abramovici and M. A. Breuer, "Fault Diagnosis in Synchronous Sequential Circuits Based on an EffectCause Analysis," IEEE Trans. Comput., Vol. C-31,12, pp. 1165-1172,1982.
[4] H. Cox and J. Rajski, "A Method of Fault Analysis for Test Generation and Fault Diagnosis," IEEE Trans.
Computer Aided Design, Vol. 7, 7, pp. 813-833,1988.
[5] S. Maker and E. McCluskey, "The Critical Path for Multiple Faults," Proc. Int. Conf. Computer-Aided Design,
pp.162-165,1989.
[6] F. Braglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN," Proc. Int. Symp. on Circuits and Systems, 1985.
[7] S. Minato, N. Ishiura and S. Yajima, "Shared Binary Decision Diagram with Attributed Edges for Efficient
Boolean Function Manipulation," Proc. 27th Design Automat. Conf., pp. 52-57,1990.
[8] R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Comput., Vol. C35, 8, pp. 677-691,1986.
[9] K. Cho and R. E. Bryant, "Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation," Proc. 26th Design Automat. Conf., pp. 418-423, 1989.
ICCAD91, Pages 554-557
A Switch-Level Matrix Approach to Transistor-Level Fault Simulation
Terry Lee and Ibrahim N. Hajj
Coordinated Science Laboratory and ECE Department, University of Illinois, 1101 West Springfield Avenue,
Urbana, Illinois 61801
Abstract
This paper describes a method for performing transistor-level logical fault simulation. The
method relies on switch-level modeling and uses a switch-level matrix-equation formulation
and solution [8] into which fault models are inserted in a straightforward manner. The fault
models include transistor stuck-at, node stuckat, and bridging faults. Both output voltage
monitoring and current testing are used for fault detection.
The approach has been implemented in a concurrent fault simulator and tested using both
combinational and sequential circuit benchmarks. The results of the simulator compares very
favorably with existing switch-level fault simulators while allowing more complete transistorlevel fault models to be included.
References
[1] P. Banerjee and J.A. Abraham, "MURPHY: A Logic Simulator for MOS VLSI Circuits," Proceedings of the
International Conference on Computer-Aided Design, 1983, pp. 94-95.
[2] F. Brglez and H. Fujiwara, "Neutral Netlist of Ten Combinational Circuits and a Target Translator in
FORTRAN," Special session on ATPG and fault simulation, Proceedings of the International Symposium on
Circuits and Systems, 1985, pp. 695-698.
[3] R.E. Bryant, "Performance Evaluation of FMOSSIM, a Concurrent Switch-Level Fault Simulator," Proceedings
of the 22nd Design Automation Conference, 1985, pp. 715-719.
[4] R.E. Bryant, D. Beatty, K. Brace, K. Cho, and T. Scheffler, "COSMOS: A Compiled Simulator for MOS
Circuits," Proceedings of the 24th Design Automation Conference, 1987, pp. 9-16.
[5] R.H. Byrd, G.D. Hachtel, M.R. Lightner, and M.H. Heydemann, "Switch-Level Simulation: Models, Theory,
and Algorithms," Computer-Aided Design of VLSI Circuits and Systems, Vol. I, JAI Press, Greenwich, Conn.,
1986.
[6] F.J. Ferguson and J.P. Shen, "Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault
Analysis," Proceedings of the International Test Conference, 1988, pp. 475-484.
[7] I.N. Hajj and D. Saab, "Fault Modeling and Logic Simulation of MOS VLSI Circuits Based on Logic
Extraction," Proceedings of the International Conference on Computer-Aided Design, 1983, pp. 99-100.
[8] I.N. Hajj, "An Algebra for Switch-Level Simulation," Proceedings of the International Conference on
ComputerAided Design, 1990, pp. 488-491.
[9] P. Nigh and W. Maly, "Test Generation for Current Testing," IEEE Design & Test of Computers, 1990, pp. 2638.
ICCAD91, Pages 560-563
Multi-level Logic Minimization based on Minimal Support and its Application to the
Minimization of Look-up Table Type FPGAs
Masahiro Fujita and Yusuke Matsunaga
Artificial Intelligence Lab., Fujitsu Laboratories Ltd., 1015 Kamikodanaka, Nakahara-ku, Kawasaki 211, JAPAN
Abstract
We present a method for multi-level logic minimization which is particularly suitable for the
minimization of lookup table type FPGAs. Given a set of nodes to be minimized, we first
calculate sets of supports which are necessary to construct the functions for the given nodes by
applying functional reduction [1,2]. The functional reduction process guarantees that we can get
the minimal support for each node. We then make a covering table for the set of nodes to be
minimized so that we can get the minimal supports to cover all the functions for the given set of
nodes to be minimized. We present a preliminary implementation and its results of ISCAS
combinational benchmark circuits combined with MIS2.1 standard script [3] and our Boolean
resubsitution minimizer [5], and show the effectiveness of the presented method.
References
[1] C. Halatsis and N. Gaitanis, "Irredundant Normal Forms and Minimal Dependence Sets of a Boolean Function,"
IEEE Trans. Computer, C-27(11):1064-1068, November 1978.
[2] F.M. Brown, "Boolean Reasoning," Kluwer Academic Publishers, 1990.
[3] R.K. Brayton, R. Rudell, A.L. Sangiovanni-Vincentelli, and A.R. Wang, "MIS: A Multiple-Level Logic
Optimization," IEEE Trans. CAD, pp.1062-1081, Nov. 1987.
[4] D. Bostick, G.D. Hachtel, R.M. Jacoby, M.R. Lightner, P. Moceyunas, C.R. Morrison, and D. Ravenscrofit,
"The boulder optimal logic design system," Proc. ICCAD '87, November 1987.
[5] H. Sato, Y. Yasue, Y. Matsunaga, and M. Fujita, "Boolean resubstitution with permissible functions and Binary
Decision Diagrams," Proc. 27th Design Automation Conference, 1990.
[6] R. Murgai, Y. Nishizaki, N. Shenoy, R.K. Brayton, and A. Sangiovanni-Vincentelli, "Logic Synthesis for
Programmable Gate Arrays," IEEE/ACM 27th Design Automation Conference, June 1990.
[7] R.J. Francis, J. Rose, and K. Chung, "Chorle:A Technology Mapping Program for Lookup TableBased Field
Programmable Gate Arrays," IEEE/ACM 27th Design Automation Conference, June 1990.
[8] A. Saldanha, A.R. Wang, R. Brayton, and A. Sangiovanni-Vincentelli, "Multi-Level Logic Simplification using
Don't Cares and Filters," Proc. 25th DAC, June 1989.
[9] M. Fujita, Y. Matsunaga, and T. Kakuda, "On Variable Ordering of Binary Decision Diagrams for the
Application of Multi-Level Logic Synthesis," Proc. 2nd EDAC,1990.
[10] R.L. Rudell, "Logic Synthesis for VLSI Design," Technical Report UCB/ERL M89/49, University of
California, Berkeley, 1989.
ICCAD91, Pages 564-567
Improved Logic Synthesis Algorithms for Table Look Up Architectures
Rajeev Murgai, Narendra Shenoy, Robert K. Brayton, Alberto Sangiovanni-Vincentelli
Department of EECS, University of California, Berkeley, CA-94720
Abstract
Programmable Gate Arrays (PGA's) are important architectures for rapid system prototyping.
We address the problem of synthesis for a popular class of PGA architectures - the table look up
(TLU) architectures. These use lookup table memories to implement logic functions. Several
techniques have been presented for synthesis onto such architectures ([1], [2], [3], [4], [5]). Here
we present new and improved techniques for minimizing the number of table look up blocks
used to implement a combinational circuit. On average, the results obtained on a set of
benchmarks are 15-29% better than results obtained by previous approaches.
References
[1] R. Murgai, Y Nishizaki, N. Shenoy, R. K. Brayton and A. Sangiovanni-Vincentelli, "Logic Synthesis for
Programmable Gate Arrays", Proc. 27th Design Automation Conference, June 1990, pp. 620-625.
[2] R. J. Francis, J. Rose, and K. Chung, "Chortle: A Technology Mapping Program for Lookup Table-Based Field
Programmable Gate Arrays", Proc. 27th Design Automation Conference, June 1990, pp. 613-619.
[3] R. J. Francis, J. Rose, and Z. Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based
FPGAs", to appear in Proc. 28th Design Automation Conference, June 1991.
[4] D. Filo, J. C. Yang, F. Mailhot, G. D. Micheli, "Technology Mapping for a TwoOutput RAM-based FieldProgrammable Gate Arrays", European Design Automation Conference, February 1991, pp. 534-538.
[5] K. Karplus, "Xmap: A Technology Mapper for Table-Lookup FieldProgrammable Gate Arrays", Proc. 28th
Design Automation Conference, June 1991.
[6] Xilinx Inc., 2069, Hamilton Ave. San Jose, CA-95125, The Programmable Gate Array Data Book.
[7] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: A Multiple-Level Logic
Optimization System", IEEE Transactions on CAD, November 1987.
[8] J.P. Roth and R.M. Karp, "Minimization over Boolean graphs", IBM Journal of Research and Development,
April 1962.
[9] R. Murgai, N. Shenoy, R. K. Brayton and A. Sangiovanni-Vincentelli, "Improved Logic Synthesis Algorithms
for Table Look Up Architectures", Internal Report, University of California, Berkeley, 1991.
[10] A. Saldanha, A. Wang, R. Brayton, and A. Sangiovanni-Vincentelli, "MultiLevel Logic Simplification using
Don't Cares and Filters", Proc. 26th Design Automation Conference, 1989.
ICCAD91, Pages 568-571
Technology Mapping of Lookup Table-Based FPGAs for Performance
Robert J. Francis, Jonathan Rose, Zvonko Vranesic
Department of Electrical Engineering, University of Toronto
Abstract
A new technology mapping algorithm that reduces the delay of combinational circuits
implemented with lookup table-based Field-Programmable Gate Arrays (FPGAs) is
presented. The algorithm reduces the contribution of logic block delays to the critical path
delay by reducing the number of lookup tables on the critical path.
The key feature of the algorithm is the use of bin packing to determine the gate-level
decomposition of every node in the network. In addition, reconvergent paths and the replication
of logic at fanout nodes are exploited to further reduce the depth of the lookup table circuit. For
fanout-free trees the algorithm will construct the optimal depth K-input lookup table circuit when
K is less than or equal to 6.
References
[1] R. J. Francis, J. Rose, K. Chung, "Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays," Proc. 27th DAC, June 1990, pp. 613-619.
[2] R. Murgai, Y, Nishizaki, N. Shenay, R. K. Brayton, A. Sangiovanni-Vincentelli, "Logic Synthesis for Programmable Gate Arrays," Proc. 27th DAC, June 1990, pp. 620-625.
[3] P. Abouzeid, L. Bouchet, K. Sakouti, G. Saucier, P. Sicard, "Lexicographical Expression of Boolean Function for
Multilevel Synthesis of high Speed Circuits," Proc. SASHIMI 90, Oct. 1990, pp. 31-39.
[4] D. Filo, J. C. Yang, F. Mailhot, G. De Micheli, "Technology Mapping for a Two-Output RAM-based field Programmable Gate Array," Proc. EDAC 91, Feb, 1991, pp. 534-538.
[5] R. J. Francis, J. Rose, Z. Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs," Proc.
28th DAC, June 1991 pp. 227-233.
[6] K. Karplus, "Xmap: a Technology Mapper for Tablelookup Field-Programmable Gate Arrays," Proc, 28th DAC,
June 1991, pp. 240-243.
[7] K. Keutzer, "DAGON: Technology Binding and Local Optimization by DAG Matching," Proc. 24th DAC, June
1987, pp. 341-347.
[8] R. J. Francis, "Technology Mapping for Lookup TableBased FPGAs," Ph.D. Thesis in preparation, University of
Toronto, Department of Electrical Engineering.
[9] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, A. Wang, "MIS: a Multiple-Level Logic Optimization System," IEEE Tr. CAD, Vol CAD-6, No. 6, Nov. 1987, pp. 1062-1081.
[10] K. J. Singh, A. R. Wang, R. K. Brayton, A. Sangiovanni-Vincentelli, "Timing Optimization of Combinational
Logic" Proc. ICCAD 88, Nov 1988, pp.282-285.
[11] XACT LCA Development System, Vol. II, Xilinx Inc., 1989.
ICCAD91, Pages 572-575
Performance Directed Synthesis for Table Look Up Programmable Gate Arrays
Rajeev Murgai, Narendra Shenoy, Robert K. Brayton, Alberto Sangiovanni-Vincentelli
Department of EECS, University of California, Berkeley, CA-94720
Abstract
Programmable gate arrays (PGA's) are playing an increasing role as a cheap and efficient means of
prototyping. Previous work on automation for PGA's ([1], [2]) has focussed on area optimization,
i.e., on minimizing the number of blocks to implement a circuit. We address the problem of delay
optimization for PGA's. The main considerations are the number of levels in the circuit and the
wiring delay. We propose a two-phase approach: the first phase involves delay optimizations
during logic synthesis before placement, and the second uses logic resynthesis during a timingdriven placement technique.
References
[1] R. Murgai, Y Nishizaki, N. Shenoy, R. K. Brayton and A. Sangiovanni-Vincentelli, "Logic Synthesis for
Programmable Gate Arrays", Proc. 27th Design Automation Conference, June 1990, pp. 620-625.
[2] R. J. Francis, J. Rose, and K. Chung, "Chortle: A Technology Mapping Program for Lookup Table-Based Field
Programmable Gate Arrays", Proc. 27th Design Automation Conference, June 1990, pp. 613-619.
[3] Xilinx Inc., 2069, Hamilton Ave. San Jose, CA-95125, The Programmable Gate Array Data Book.
[4] K. J. Singh, A. R. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli,"Timing Optimization of
Combinational Logic", Proc. ICCAD, Nov. 1988, pp. 282-285.
[5] H. Touati, C. Moon, R. K. Brayton, and A. Wang, "Performance-oriented Technology Mapping", Advanced
Research in VLSI: Proceedings of the sixth MIT Conference, MIT Press, Apr. 1990.
[6] P. Massoud, and N. Bhat, "Layout Driven Technology Mapping", Proc. 28th Design Automation Conference,
June 1991.
[7] R. J. Francis, J. Rose, and Z. Vranesic, "Technology Mapping for Delay Optimization of Lookup Table-Based
FPGAs", Proc. International Workshop on Logic Synthesis, May 1991.
[8] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: A Multiple-Level Logic
Optimization System", IEEE Transactions on CAD, November 1987.
[9] J. Rubinstein, P Penfield, and M. A. Horowitz, "Signal Delay in RC Tree Networks", IEEE Transactions on
CAD, July 1983, pp. 119-127.
[10] J.P. Roth and R.M. Karp, "Minimization over Boolean graphs", IBM Journal of Research and Development,
April 1962.
[11] R. Murgai, N. Shenoy, R. K. Brayton and A. Sangiovanni-Vincentelli, "Improved Logic Synthesis Algorithms
for Table Look Up Architectures", Proc. ICCAD, Nov. 1991.
[12] R. Murgai, N. Shenoy, R. K. Brayton and A. Sangiovanni-Vincentelli, "Performance Directed Synthesis for
Table Look Up Programmable Gate Arrays", Internal Report, University of California, Berkeley, 1991.