Digital Control in the Voltage Regulators for Computers
Praveen Jain, CHiL Semiconductor
Abstract – This paper review the latest advances in digital control techniques, which are suitable for multi-phase
synchronous buck converters for computer applications. Some digital control algorithms, which can improve
dynamic and static performance, are reviewed for the single-phase or multi-phase synchronous buck converters.
Finally, performance of CHiL’s new digital control is presented that eliminates the bulk capacitors and improves
the light load efficiency.
I. INTRODUCTION
To decrease power consumption and increase the speed, the next generation of computer microprocessors will
operate at significantly lower voltages and higher currents than today’s generation. Recently, the supply voltage is
reduced to around 1V, which was 5V or 3.3V five or ten years ago. It is expected that in future the supply voltage
is going to drop to a level of 0.8V or lower. Future processors will require more than 200A current at the voltage
of about 0.8V and needs up to around 120A/ns current transient speed. This makes it much more difficult to
maintain an accurate voltage regulation for voltage regulators [1] - [4].
Analog circuits have been dominating in the control of switching power supplies because of its simplicity and
low implementation cost. Unfortunately, it may not meet the increasingly stringent requirement of today’s and
future processors. Digital control methods are now offering good alternatives to analog approaches.
With the advancement in digital technology, the implementation of digital controller have become more
feasible, which vary from the use of DSP, microprocessors, and FPGA, to software-programmable mixed-signal
integrated circuits. Compared with analog circuit, digital controllers offer a number of salient advantages:
(1) Enabling advanced control algorithms: It is much easier to implement the advanced control techniques
into digital control system, some of which are considered impractical for analog realization. Advanced
control schemes may help in improving one or several system performances of power converters such as
dynamic performance, efficiency, stability, etc.
(2) Flexibility and programmability: The use of software or programmable memory to change the controller
functionality makes a system based on a digital controller very flexible. The design can be easily adapted
or modified to meet new requirements. It is also very easy to implement power management aspect in the
digital controllers that is increasingly becoming system requirement.
(3) Less susceptible to component and ambient variations: Analog controllers suffer from component
tolerance variation and drift due to ambient conditions and aging. A digital controller can precisely position
poles and zeros and requires fewer components. Thus, the digital control system is less susceptible to these
variations.
A typical digital controlled synchronous buck converter, which is widely used in the voltage regulators, is
shown in Fig.1. The digital controller typically consists of analog/digital converter, digital control law processor,
and digital PWM generator. A lot of research has been performed in these areas of digital control of switching
power supplies and significant progress has been achieved.
Lf
M1
V in
Vo
Cf
M2
D river
D PW M
R Load
Sensor Gain H
D igital C ontrol
Algorithm Processor
A /D
C onverter
Digital Controller
Fig. 1 Typical block diagram of a digitally controlled synchronous buck converter
II. ARCHITECTURE OF ANALOG TO DIGITAL CONVERTER
Normally, analog control provides very fine resolution to position output voltage. Output voltage can be
adjusted to any arbitrary value, which is only limited by loop gain and noise levels. However, a digital controller
has a finite set of discrete levels, since quantizing elements, the A/D converter and the DPWM, exist in the digital
control loop. Thus, the quantization of A/D converter and DPWM is critical to both static and dynamic
performance of power converters.
A. Resolution Requirement of the A/D Converter
Resolution of the A/D converter (ADC) should be such that the output voltage error of power converter tightly
falls within the allowed voltage range. That’s, the product (VLSB) of least significant bit (LSB) of the ADC has to
be less than the allowed maximum scaled output voltage variation (∆Vo×H), where H is the scaled factor of
voltage sensor, expressed as:
Vref
V
V LSB = Nsradc ≤ ∆Vo ⋅ H = ∆Vo ⋅
Vo
2

V
V
N adc ≥ int  log 2  sr ⋅ o
V

 ref ∆Vo



 
(1)
Where, Vsr is the voltage scale range of the ADC, Vref is the reference voltage, and function int[ ] takes the upper
rounded integer value of the product.
The formula (1) indicates the minimum number of bits of the ADC to meet output voltage regulation
requirement of power converters. For a voltage regulator with 1.5V output voltage, 5mV allowed voltage
variation, if the reference voltage is 1.5V, and the voltage scale range of ADC is 1.8V, a minimum 9-bit
resolution will be required for the ADC.
B. Analog-to-Digital Converters
As described above, dedicated voltage regulators for microprocessors supply large current with very fast
current slew rate requirements. Thus, high dynamic performance is necessary in designing these voltage
regulators. Extremely fast response is one of the most important dynamic criteria. When the A/D converter is
involved in the digital control loop, ADC architectures with low latency are desirable, since the latency causes a
phase shift into the loop that may degrade the system response.
A wide choice of ADC architectures exist that differs in resolution, bandwidth, accuracy, and power
requirements. The major ADC architectures are flash, successive approximation (SAR), and pipelined with
multiple flash stages. Both SAR and pipelined ADC will introduce larger latency since they need several cycles to
convert the analog signal. On the other side, the flash architecture has the advantage of being very fast because the
conversion occurs in a single cycle. Therefore the flash architecture is preferable for the design of digital
controller for these applications. The main disadvantage of the flash structure is that it requires a large number of
comparators (2n-1 comparators for an n-bit ADC). With the example above, the 9 bits full range ADC will require
511 comparators, which require large core area and power consumption.
Observing that under normal operation the output voltage of the regulators should not deviate substantially
from the reference voltage Vref. The output voltage Vo has to be quantized only over the regulation window around
the reference voltage Vref [5]-[8]. Thus, a windowed ADC that realizes high resolution with reduced quantization
range can be used.
Fig.2: Block diagram of a “window” flash
implementation of A/D converter
Fig.3: Block diagram of a “window” delay-line A/D converter
A block-diagram of a flash implementation of such a “window” ADC is shown in Fig. 2 [5]. Note that, since
Vo is compared against Vref, the resulting digital signal (De) is the difference between these two values, which is a
digital representation of the error signal Ve. Hence, it has the functionality of both an ADC and an error amplifier.
Regarding the example above again, if the possible output voltage variation is ±40mV, only a 3-bit ADC is
needed for 5mV resolution.
The window concept has been successfully used in delay-line ADC [6] as shown in Fig.3. The unique
advantage of this ADC is that it does not require any precision analog components, so that it can be implemented
by using standard logic gate. But this A/D converter has larger latency than the flash one. Generally, for a
voltage regulator, where extremely fast response is most important, the windowed flash architecture is preferable.
III. DIGITAL PWM GENERATION
A. Resolution Requirement of DPWM
Digital pulse width modulator (DPWM) produces a discrete and finite set of duty ratio values. From the point
of view of steady-state output, only a set of discrete output voltages is possible. It is necessary that the resolution
of the DPWM be high enough to avoid a phenomenon known as limit-cycle oscillation. In a limit cycle oscillation,
the output goes into an oscillation of fixed amplitude and frequency [9].
A necessary condition to avoid the limit cycle oscillation is that the change ∆Vod in the output voltage caused
by one LSB change in the duty cycle ratio has to be smaller than the analog equivalent of the LSB of the A/D
converter. For the synchronous buck converter widely used for voltage regulators,
Vod = Vin ⋅ ∆D =
Vin
2
N dpwm
≤
V sr Vo
⋅
2 N adc Vref
Thus, the minimum number of DPWM is given as:

 Vref 

N dpwm ≥ int  N adc + log 2 

 Vsr ⋅ D 
The minimum number of DPWM depends on topology, the output voltage and the ADC resolution.
B. Fast Counter-Comparator Scheme
The simplest method to generate DPWM signals is the fast counter-comparator scheme [10] [11]. In this
scheme a system counter (n bits) is used to generate the fixed sampling. The resolution of DPWM signals hereby
is 1/2n. By comparing counter value and the numerical duty cycle value, the switch of the converter is turned
on/off. This scheme is very simple and easy to implement. This scheme takes reasonable small die area but the
power consumption is relatively large, since a high frequency clock and other related fast logic circuits are needed
to achieve a high enough resolution based on a high switching frequency in this scheme. For 10 bits DPWM
based on 1MHz switching frequency, the clock frequency will be 1.024GHz. This is too high and unacceptable.
For voltage regulators with the structure of a multi-phase synchronous buck converter, the system counter can
be shared by all phases, with shifting turning-on signal of each phase for certain phase degree. But independent
comparator is needed for each phase. It doesn’t increase power consumption that much. Symmetric PWM phase
signals can be achieved based on the fast counter-comparator scheme.
Fig. 4: Structure of tapped delay line DPWM circuits
C. Tapped Delay-Line Scheme
A tapped delay line scheme (shown in Fig. 4) is proposed in [6]. Power is significantly reduced with respect to
the fast-counter-comparator scheme as the fast clock is replaced by a delay-line that runs at the switching
frequency of the converter. In this scheme, a pulse from a reference clock starts a cycle and sets the DPWM
output to go high. The reference pulse propagates through the delay line, and when it reaches the output selected
by the multiplexer, the DPWM output goes low. The total delay of the delay line is adjusted to match the
reference clock period.
The main drawback is that the size of the MUX grows exponentially with the number of resolution bits n. In a
multiphase controller, precise delay matching among the phases places a stringent symmetry requirement on the
delay line, so it is not well suited for multiphase application [12]. However, both these two drawback may be
relieved in the combination of delay-line and counter-comparator scheme, which is presented in [13]. The
symmetry among the phases may be provided when the number of counter is larger than phase number. For
example, a counter with at least 2 bits (counter number is 2n for n bits counter) is needed to achieve phase
symmetry for a four-phase synchronous buck converter.
C. Ring-Oscillator-MUX scheme
A ring-oscillator-MUX scheme is presented in [12], which has area and power considerations similar to those
of the delay line approach. In this scheme, the ring oscillator in the DPWM runs in current starved mode and by
adjusting the supply current frequency can be controlled to the entire ring. Thus, the switching frequency of the
converter can be locked to an external clock by controlling the DPWM ring current.
The advantage of ring-oscillator-MUX over the delay line structure is that it has a symmetric structure.
Therefore, it is well suitable for multi-phase applications.
Fig. 5 Structure of ring-oscillation-MUX DPWM circuit
D. Dithering Method
Dithering method is a soft method to increase the effective resolution of a DPWM module without increasing
the hardware resolution, which is proposed in [8]. The idea behind digital dither is to vary the duty cycle by an
over a few switching periods, as shown in Fig. 6, so that the average duty cycle has a value between two adjacent
quantized duty cycle levels. The averaging action is implemented by using an output filter. However, the
disadvantages of dithering method are low system bandwidth and low frequency output ripple.
Fig. 6 Illustration of 1 bit dither method
In general, all the techniques and their combinations reviewed above may be used in the application of
voltage regulators. Fast counter-comparator scheme is easy to use and simple to implement. Since it is fully
digital logic circuits, it is very suitable for implementation in microprocessors, DSPs or FPGAs. However, when
high-resolution and high-switching frequency is a must, extremely high clock frequency and power consumption
will disqualify it. If it is combined with dithering method, this problem could be relieved somewhat. Both tapped
delay-line and ring-oscillator-MUX are implemented by analog method, so it is only suitable for mixed mode
analog and digital implementation. The ring-oscillator-MUX scheme is well suitable for these applications with a
multi-phase structure because of its symmetric structure. Dithering method also can be utilized with them to save
digital core area of the chip.
IV. DIGITAL CONTROL ALGORITHMS
The most important advantage of digital control is enabling advanced control algorithms. A number of
research works have been performed on digital control algorithms. Basically, they are falling into two classes:
linear control method, and non-linear control method. Linear digital control methods are translated directly from
those techniques, which are widely used in analog control circuits, and provide comparable performance. On the
other side, non-linear digital control such as predictive control, adaptive control, and multi-mode control can
improve dynamic performance, as well as static performance. This section will briefly review these aspects.
A. Linear Control Method
All analog linear control concepts can be translated into their digital ones, including classic PID control [14].
The discrete time of feedback control PID law has the form:
Dc [ k + 1] = k p De [ k ] + k d ( De [ k ] − De [ k − 1]) + K i Di [ k ]
Di [ k + 1] = Di [ k ] + De [ k ]
Where Dc[k] is the duty-ratio command at discrete time k, De[k] is the digitized version of the error signal Ve,
and Di[k] is the state of a digital integrator, Kp is the proportional coefficient, Ki is the Integral coefficient, and Kd
is the derivative coefficient.
B. Adaptive Voltage Positioning
Digital control based on the concept of adaptive voltage positioning (AVP) [15]-[17] has been widely used in
recent voltage regulator designs. In AVP, a variable reference voltage is used as a function of the load current
according to the following equation.
Vvref = Vfref – Io x RESR
Where, Vvref is variable reference voltage, Vfref is a fixed reference voltage, Io is a load current and RESR is
a real equivalent source resistance. In AVP, the idea is always to position Vo at variable reference voltage, instead
of a fixed value Vfref [9]. This way the converter behaves as a voltage source with output impedance that is always
real and equal to RESR. If adaptive voltage positioning is used, ideally output filter capacitor can be made half the
size required for a stiff voltage regulator design, which can save on cost and circuit area and volume.
In [5], the adaptive-voltage-position technique is extended to non zero-delay digital controller. The scheme
for implementing AVP with a digital controller is shown in Fig. 7. A digital PID compensation is implemented.
Typical performance is shown in Fig. 8.
Fig. 7: Implementation of optimal voltage positioning
using a digital controller.
Fig. 8: Transient response of a prototype digitally controlled
multiphase buck converter (10A load step).
B. Peak Current Control
Another digital implementation, peak current control to achieve adaptive-voltage-position is introduced in [17].
The basic idea is coming from analog counterpart presented in [18]. In this approach a feedback loop is designed
to make the power converter to have constant output impedance. To implement digital peak current control, a fast
ADC, whose sampling frequency is at least 100 times the switching frequency of the power converter, is required.
This makes this method expensive to implement.
C. Droop Control
Another digital implementation, active droop control to achieve adaptive-voltage-position is also introduced in
the literature. The digital implementation of active droop control is that the sensed inductor current is added to the
sensed output voltage before the ADC. In this approach only one ADC is required and a double-edge modulation
method is used so that sampling frequency can be reduced somewhat.
D. Non-Linear Control
A new optimal control algorithm, which provides different control laws for different modes of operation, is
proposed in [19]–[20] to achieve the best possible dynamic performance for synchronous buck converters under
dynamic load changes. This patented control technique eliminates the need for the bulk capacitors in the power
delivery of the high-speed processors. Figure 9 shows the dynamic performance of the CHiL’s proposed solution,
for a multi-phase buck converter for 1V @ 120A application with a step-up of 30A-to-125A, without using any
bulk capacitors with respect to the current solutions available in the market.
1.8V
1.6V
Proposed Solution
1.4V
1.2V
1.0V
Current Solutions
0.8V
0s
50us
V(Vo)
100us
150us
200us
250us
300us
350us
Time
Fig. 9: Transient performance of the proposed CHiL’s solution.
400us
IV. LIGHT-LOAD EFFICIENCY
The light-load efficiency is becoming very critical due to new regulatory requirements such as Energy Star.
To address this, a multi-mode control strategy for a synchronous buck converter operating over a wide load range
is presented in [16]. For heavy loads, the converter runs in fixed-frequency continuous-conduction-mode (CCM).
At light loads, it enters discontinuous-conduction-mode (DCM) with synchronous rectification. At still lighter
loads, synchronous rectification is disabled in DCM. At very light loads, the converter operates in variablefrequency pulse skipping mode. The synchronous rectifier (SR) timing is scheduled as a function of the load
current, enabling appropriate transition among the modes. An on-line adaptive algorithm to optimize the SR
timing, based on power loss minimization, is introduced. Complex computations are required to be performed in
digital controller. This makes overall design of the digital controller expensive and prohibitive for many cost
sensitive applications such as Desktop Personal Computers.
CHiL has developed a unique control and drive technology [21] that enables the use of simple control algorithm
for cost effective design of digital controllers, making their use possible in the cost sensitive applications of
Desktop computers. Figure 10 shows significantly improved light-load efficiency with CHiL solution.
90
80
70
Eff
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90 100 110
Current
Fig.10: Percentage efficiency as a function of load current, using CHiL’s controller and drivers.
V. CONCLUSIONS
Future microprocessors will operate at lower voltage and higher current with faster transient slew rate. The
use of digital controllers in these applications is becoming essential not only to meet the core powering
requirements but also to significantly improve system diagnostics with system level power management. CHiL is
developing a slew of mixed-analog & digital controller that will enable this promising technology with cost
effectiveness.
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