Vol. 35, No. 4
Journal of Semiconductors
April 2014
A dynamic-biased dual-loop-feedback CMOS LDO regulator with fast
transient response
Wang Han(王菡)Ž and Sun Maomao(孙毛毛)
Analog IC Design Department, Chongqing Acoustoelectric and Optoelectronic Co., Ltd., Chongqing 400060, China
Abstract: This paper presents a low-dropout regulator (LDO) for portable applications with dual-loop feedback
and a dynamic bias circuit. The dual-loop feedback structure is adopted to reduce the output voltage spike and
the response time of the LDO. The dynamic bias circuit enhances the slew rate at the gate of the power transistor.
In addition, an adaptive miller compensation technique is employed, from which a single pole system is realized
and over a 59ı phase margin is achieved under the full range of the load current. The proposed LDO has been
implemented in a 0.6-m CMOS process. From the experimental results, the regulator can operate with a minimum
dropout voltage of 200 mV at a maximum 300 mA load and IQ of 113 A. The line regulation and load regulation
are improved to 0.1 mV/V and 3.4 V/mA due to the sufficient loop gain provided by the dual feedback loops.
Under a full range load current step, the voltage spikes and the recovery time of the proposed LDO is reduced to
97 mV and 0.142 s respectively.
Key words: dual-loop feedback; dynamic bias; adaptive miller compensation; low-dropout regulator (LDO); transient response
DOI: 10.1088/1674-4926/35/4/045005
EEACC: 1205
2. Overview of transient response and stability of
low quiescent current LDOS
1. Introduction
In recent years, low-dropout linear regulators (LDOs) have
been widely used in portable battery-powered electronic devices, as LDOs can convert decaying battery voltages to lownoise and accurate voltages for noise-sensitive systems.
There are several factors that have an effect on the response
of a low dropout regulator (LDO) to a load transient, such as
the external compensation of the LDO, output capacitance and
the parasitics of the output capacitor including equivalent series resistance (ESR) and equivalent series inductance (ESL).
The unity gain frequency (UGF), slew rate and stability of the
LDO circuit determine the overall transient response of the
LDO also. Several techniques have been shown to improve
transient response, like dynamic biasingŒ1 4 , SR enhancementŒ5 9 , output current boostingŒ10 , output current flexible controlŒ11; 12 and a modified compensation strategyŒ13 17 .
However, their performances can only be optimized for specific loading conditions because loading current variations are
always faster than the control loop. Recently dual-loop feedback techniques have been shown to improve the transient responseŒ18; 19 .
Figure 1 shows a block diagram of a typical LDO regulator, which consists of an error amplifier, a power transistor,
high resistance feedback network and an output capacitor. In
order to achieve high efficiency, the error amplifier current is
usually required to be less than 1%–2% of the nominal load
current. This small quiescent current results in a relatively narrow bandwidth for the LDO.
Figure 2 shows details of a typical LDO response to a load
current step. The response of an LDO to a load current change
is characterized in two sections: initial step responses t1 and
t3 at settling times t2 and t4 . The step response represented in Fig. 2 is a function of the amplifier bandwidth and
the large signal slew rate at the gate of the power transistor.
t1 is given byŒ10
In this paper, an LDO with dynamic bias and dualloop feedback structure is proposed. A global voltage mode
feedback achieves an accurate steady-state operation, and a
secondary current mode feedback is utilized to achieve a fast
transient response. In addition, a dynamic bias technique is employed to enhance the slew rate at the gate of the power transistor by detecting output voltage variations and dynamically altering the gate driving current. Thus, a fast and current-efficient
LDO can be achieved.
† Corresponding author. Email: eehanwang@gmail.com
Received 21 August 2013, revised manuscript received 27 November 2013
045005-1
Fig. 1. Block diagram of a typical LDO regulator.
© 2014 Chinese Institute of Electronics
J. Semicond. 2014, 35(4)
Wang Han et al.
Fig. 2. Typical LDO transient response to load current step.
Fig. 4. Block diagram of the proposed regulator.
Fig. 3. Frequency response of a typical linear regulator under different
load conditions.
t1 D
1
1
V
C tsr D
C CP
;
BWcl
BWcl
Isr
(1)
where BWcl is the closed-loop bandwidth of the system, tsr is
the slew rate time associated with CP , V is the voltage variation at CP and Isr is the slew rate limited current. Similar to t1 ,
the response time to a load current drop t3 is also inversely
proportional to the closed loop bandwidth and slew rate limited current of the LDO. In order to minimize t1 and t3 ,
the LDO requires a wide closed-loop bandwidth and a large
slew rate current. Using a small output capacitor, t2 and t4
could also be minimized. Output transient voltages Vtr1 and
Vtr2 strongly depend on the voltage drop across the equivalent series resistance (RESR /, which is defined by Vtr1 RESR Iload . To improve the accuracy of an LDO during load
variations, transient voltage errors could be minimized by using small RESR .
The worst-case output voltage variation is a function of
the bandwidth and the slew rate limit of the circuit. However, bandwidth and slew rate limit are highly dependent
on quiescent current flow. As bandwidth is demanded to increase, the parasitic poles are required to increase accordingly,
thereby necessitating more current flow to decrease associated
impedances. Consequently, the error amplifier’s quiescent current must necessarily increase to yield faster response times.
Moreover, increasing slew rate performance requires an increase in bias current on the circuit driving the slew rate limited
node. As a result, the overall minimum quiescent current flow
is limited by the maximum allowable output voltage variation
arising from full range load current steps.
For a low dropout voltage, a pMOS device is usually
adopted as the output transistor. The regulation function for a
stable output is a feedback system with a large loop gain. Figure
3 depicts the frequency response of a typical LDO under different output loads. The system has one dominant pole fp1 at
the output node and two high-frequency poles fp2 and fp3 . Although the equivalent series resistance (RESR / associated with
the output capacitor can generate a zero fz1 for enhancing the
phase margin, RESR is usually in a limited range and varies
with temperature. The biggest difficulty in this loop design is
the various transfer functions for different load currents. For
example, if the load current increases, the output impedance of
the power transistor will decrease and the loop gain will decrease accordingly. Pole fp1 at the output of the power transistor therefore moves to a higher frequency and the whole curve
shifts to the right. This transfer curve change gives rise to a
stability concern if the unity gain frequency is higher than the
high-frequency pole fp3 . Thus, the unity-gain frequency of a
typical LDO is limited by the parasitic pole fp3 , which is generated by the output impedance of the error amplifier and gate
capacitance of the power transistor. This pole can be pushed
to a higher frequency by using a low output impedance voltage buffer between the error amplifier and the power transistorŒ4; 8; 10 . An LDO with a voltage buffer to push the pole to
higher frequencies can still take 6–10 s settling time with fullload transientsŒ4 .
With forecasting that more SoC will be implemented by
ultra-small-scale technologies in the next decade, the nanoscale technology on the LDO design cannot be overlooked anymore. Both the parasitic capacitances and channel resistances
of the transistors are diminished in nano-scale technology.
As the non-dominant poles are shifted to higher frequencies,
the constraint on bandwidth is relaxed. However, the reduced
channel resistance also lowers the loop gain of the LDO, which
prevents the maximum attainable bandwidth being achieved.
Thus, several gain-enhanced techniques are shown to improve
both the accuracy and speed of the LDO in nano-scale technologiesŒ20; 21 .
3. Design of the proposed LDO
Figure 4 shows the proposed structure. It is composed of a
global reference tracking loop for steady state accuracy and a
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Wang Han et al.
Fig. 5. Schematic of the dual-loop feedback LDO.
secondary load regulation loop for load transient enhancement.
The reference tracking loop utilizes an OTA based voltagefeedback error amplifier with high gain and low quiescent
current. The load regulation loop utilizes a low ac impedance
feedback path to achieve fast response while maintaining low
quiescent power consumption. The low ac impedance feedback
path is constructed using a current-feedback based structure.
Moreover, with the aid of a dynamic bias technique that provides a larger driving current for power transistor gate control,
the load regulation loop exhibits a fast transient response when
the loading is with disturbance. Section 3 provides details of
the circuit implementation and principle of operation.
3.1. Circuit implementation
Figure 5 shows the schematic of the dual-loop feedback
LDO. A folded cascode OTA is used as the first error amplifier. The error voltage Ve at the output of the folded cascade
error amplifier is connected to the gate of input transistor M12;
feedback voltage VOUT is connected to the source of M12. This
connection ensures that there is no dc current drawn from the
primary folded cascode amplifier. M14, M15 and M17 form
a local current feedback loop ensuring iM14 D iM15 . This current feedback structure guarantees the wide bandwidth and fast
response with minimum slew-rate limiting.
To understand the behavior of the load regulation loop,
we can consider two critical load transients. In case of a load
current increase, feedback voltage VOUT drops. Unlike a voltage feedback amplifier, the input transistor M12 detects the
transient voltage reduction. This reduction instantaneously decreases the current through the transistor M14, responding with
a fast increase in node voltage Va . On the other hand, when
load current is reduced, the input transistor M12 detects the
transient voltage increment, responding with a fast decrease in
node voltage Va . This ensures a fast response in both transient
conditions.
In addition to controling the loop bandwidth, the transient
response is limited by the slew rate at the gate VP of power transistor MP. As shown in Fig. 5, M19 forms the buffer stage and
provides the driving current of the gate VP of the power transis-
Fig. 6. Dynamic bias technique in output stage.
tor. M19 is made of depletion mode FET to ensure the complete
turn-off of MP. The slew rate of VP can be expressed by slew
rate D Id /CP , where CP denotes all of the capacitance seen at
node VP and Id is the current error between current flowing in
M19 and M23. The constant current in M23 has a compromise
in the output stage. A larger current in M23 has the advantage
of discharging the gate VP of the power transistor and a smaller
current in M23 has the advantage of charging the gate VP of
the power transistor. This is the reason that a large bias current
does not always guarantee a small output peak variation. To
speed up the slew rate in both operating cases, a dynamic bias
is introduced in this design, which is shown in Fig. 6. M23 in
the output stage is divided into two parts: M23A and M23B.
M23A has a constant current bias and Id is adjusted by M23B
accordingly. In the dynamic design, a gm stage is realized with
a differential pair to convert the error voltage between VREF
and VFB as a current to M23B. When VREF is larger than VFB ,
the current flowing from M23B increases and the voltage at VP
can decrease more quickly to enhance the turn-on speed of MP.
When VREF is smaller than VFB , the current flowing at M23B
decreases and the voltage at VP can increase more quickly to
enhance the turn-off speed of MP. Note that the dynamic bias
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Wang Han et al.
Fig. 7. Simulation result of load transient responses for the proposed LDO and voltage follower based LDO with a 300 mA load current change
with a 3.3 F load capacitor.
Fig. 8. Equivalent circuit model of the load regulation loop.
should be chosen by a proper value to ensure that the feedback
control in the load regulation loop is not affected by this dynamic feedback bias.
ALRLopen .s/ D
Figure 7 shows the simulated load transient performance
of the proposed dynamic biased dual-loop based LDO compared with a voltage follower based LDO with an equivalent
quiescent current. As seen in Fig. 7, the proposed LDO settles
60% faster.
s
s
1C
ALRL 1 C
!z1
!z2
s
s
1C
1C
!p1
!p2
1C
s
!p3
1C
s
!p4
1
;
(2)
where ALRL is the dc open-loop gain, which is the product of
DC gains of the local current-feedback stage, power transistor
and feedback loop as follows:
3.2. AC and DC analysis of the proposed LDO
3.2.1. Stability analysis of load regulation loop
gm14 Rb gm6 Rc gmp ZOUT RL
;
ZOUT C RL
(3)
!p1 D .ZOUT C RL /=COUT ZOUT RL ;
(4)
!p2 D gm15 =gm16 Rc C2 ;
(5)
!p3 D gm16 =Cc ;
(6)
!p4 D gm19 =CP ;
(7)
!z1 D 1=RESR COUT ;
(8)
ALRL D
Figure 8 shows the small-signal model of the load regulation loop. In the output stage, gmp is the transconductance of
the power device, while COUT and RESR model the load capacitor and equivalent series resistance. CP is all of the capacitance seen at the gate of the power device. ZOUT is the output
impedance of the power stage. RL denotes the load impedance.
M12 acts as the input stage of the current-feedback buffer;
therefore, the feedback voltage VOUT follows the voltage Ve ,
regardless of the feedback current Ifb . The voltage mode loop
gain of the load regulation loop is represented by
!p1 , !p2 , !p3 , !p4 , !z1 , !z2 are given by
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J. Semicond. 2014, 35(4)
Wang Han et al.
!z2 D 1=R1 C2 ;
(9)
GBW D gm14 Rb gm16 Rc gmp =COUT :
(10)
The dominant pole !p1 is derived from the output
impedance of the power device and the load capacitor. The second dominant pole !p2 is derived from the internal pole of the
feedback loop and is located at node Vb . !p3 and !p4 are located at a much higher frequency than unity gain frequency.
!z1 is derived from the load capacitor and equivalent series resistance and !z2 is derived from capacitor C2 and series resistor R1 , both of which are located above unity gain frequency to
offset high frequency parasitic poles. To ensure the stability of
the dual feedback system, the open-loop bandwidth of the load
regulation loop is designed to be wider than the error amplifier. As discussed earlier, the current-mode feedback connection from node VOUT to Va enables a fast transient response and
a wide bandwidth helps to achieve a fast setting time.
In a load regulation loop, the dominant pole of the feedback loop locates at the output node and its position can be
shifted to cover a 5–6 decades range while the current that goes
through the pass device varies from 5 to 300 mA. With
p !p1 increasing with Iload and
the
loop
gain
decreasing
with
Iload , the
p
UGF moves up with Iload , which affects the stability. Several
active compensation approaches have been shown to address
the problemŒ22; 23 .
The proposed LDO utilizes the adaptive Miller compensation (AMC) technique to make the second pole of the loop
beyond the unity-gain frequency (UGF) under all loading conditions, which provides high stability. Beside, since there is no
need of a low frequency zero for phase saving, the equivalent
series resistance of the load capacitor is small, which reduces
the output voltage spike greatly. As shown in Fig. 5, M16, M17,
C2 , R2 and M18 form the AMC stage. The equivalent capacitance seen at node Vb is gm16 (R2 C 1=gm18 /C2 . Due to the
impact of the local current feedback loop, the impedance seen
at node Vb is 1/gm15 . Therefore, the second dominant pole is
!p2 D gm15 =gm16 .R2 C 1=gm18 /C2 :
(11)
When the load current increases, the voltage at node Vc
decreases, therefore the current flowing through
p the diode
connected transistor M18 increases. For gm D KIDS , the
transconductance
of M18 increases approximately proporp
tional to Iload , which makes the second dominant pole !p2
move to a higher frequency along the frequency axis.
Figure 9 indicates the simulated loop-gain transfer function of the load regulation loop. The figure shows that only the
main pole exists within the unity-gain frequency under both
no-load and full-load conditions. The phase margins under the
two conditions are 60ı and 59ı , respectively.
3.2.2. Stability analysis of reference tracking loop
Figure 10 shows the equivalent model of the reference
tracking loop, where gm1 represents the transconductance of
error amplifier and Roe models the output impedance. ˇ is the
voltage ratio of the output feedback network. The configuration
in the load regulation loop is also copied to the reference tracking loop. Because the reference tracking loop does not regulate
the output node directly, the pole in the reference tracking loop
Fig. 9. Simulated frequency response of load regulation loop.
no longer drifts with different loading conditions and stability
is independent of the load. The corresponding loop gain in the
reference tracking loop is
gm1 Roe ˇ
T .s/ s
1C
!pr1
(
1C
s
!pr2
1C
s
!pr3
h
s i
gm14 Rb gm16 Rc gmp ZOUT 1 C
!z1
1
C1
)
1
gm1 Roe ˇ
;
s
s
1C
1C
!pr1
!pr2
(12)
where !pr1 is derived from the output nodes of the error amplifier, and !pr2 and !pr3 are the poles in the load regulation loop.
The corresponding poles can be expressed as
!pr1 D 1=Roe C1 ;
(13)
!pr2 D 1=ZOUT COUT ;
(14)
!pr3 D gm15 =gm16 Rc C2 ;
(15)
0
!pr2
D gm14 Rb Rm16 Rc gmp =COUT :
(16)
Since the reference tracking loop does not need to drive
real output loads, the pole in the load regulation is at a very high
frequency. The signal path in the reference tracking loop can
simply be treated as a single pole system along with a wideband
buffer. The signal path can be expressed as a two-pole transfer
function.
Figure 11 shows the frequency response of the reference
tracking loop. The reference tracking loop was designed to
have an open-loop dc gain of 86 dB, a phase margin of 62ı
and a bandwidth of 120 kHz. With the feedback arrangement,
we can derive the closed-loop transfer function from VREF to
045005-5
J. Semicond. 2014, 35(4)
Wang Han et al.
Fig. 10. Equivalent circuit model of the reference tracking loop.
Fig. 12. Equivalent model for calculating closed-loop output resistance.
given byŒ24 ,
VOS_L VOUT
ROL
VOUT
D
C
:
ILOAD
1 C AOL ˇ
ILOAD IREF
Fig. 11. Simulated frequency response of reference tracking loop.
Ve as
ve .s/
vREF .s/
sCOUT
gm1 Roe 1 C
gm14 Rb Rm16 Rc gmp
: (17)
sCOUT
C gm1 Roe ˇ
.1 C sRoe C1 / 1 C
gm14 Rb Rm16 Rc gmp
The error voltage Ve will track the reference voltage with a
constant voltage difference. The closed-loop transfer function
from VOUT to VREF can be given by the following equation:
vout .s/
ve .s/
ALRLclosed .s/;
vREF .s/
vREF .s/
(18)
where
ALRLclosed .s/ D
ALRLopen .s/
vout .s/
D
:
ve .s/
1 C ALRLopen .s/
(19)
Since the closed-loop transfer function from Ve to VOUT in
the load regulation loop is a non-inverting unity gain buffer, the
unity gain frequency of this buffer should be wider than that of
the reference tracking loop.
3.2.3. Load regulation
The load regulation of an LDO is defined as the output
voltage variation when the load current is changed, which is
(20)
The first term denotes the closed-loop output resistance of
the regulated loop, where ROL is the open-loop output resistance, AOL is the dc open-loop gain and ˇ is the negative feedback gain factor. Obviously, increasing AOL improves loadregulation performance. Besides the impact of limited closedloop output resistance, systematic input-offset voltages, which
result from asymmetric currents and voltages in the feedback
error amplifier, further degrade load-regulation performance.
Even if the LDO were symmetric, its widely variable load
would cause considerable voltage swings at internal nodes,
subjecting some of the devices to asymmetric conditions. The
second term models the impact of systematic load-dependent
input-referred offset voltage (VOS /, where VOSL is the systematic variation of VOS with respect to a dc change in load current
ILOAD . Considering loop stability, the open-loop gain of the
feedback error amplifier is relatively low, which leads to a large
VOSL degrading the load regulation performance.
The proposed dual-loop based linear regulator has excellent load regulation performance owing to the open-loop gain
enhancement and input-offset attenuation.
Figure 12 shows the equivalent model for calculating
closed-loop output resistance of the proposed LDO, where A1
represents the DC gain of error amplifier, A2 the DC gain of
current feedback buffer and A3 the DC gain of the power stage.
Setting the input node to ground and adding a voltage source
VX at the output node, we can get VF D ˇVX , Ve1 D ˇVX ,
Ve2 D .1CˇA1 / VX and VM D A2 A3 (1 C ˇA1 / VX . Neglecting the feedback current Ifb , the closed-loop output resistance
is
ROL
VX
D
:
(21)
RCL D
IX
1 C A2 A3 .1 C ˇA1 /
045005-6
Compared with a conventional linear regulator, the closed-
J. Semicond. 2014, 35(4)
Wang Han et al.
Fig. 15. Chip photograph of the proposed linear regulator.
Fig. 13. Equivalent model for calculating load-dependent inputreferred offset voltage.
Fig. 16. Measured output waveform of load transient response with
the output current switch between 1 and 300 mA.
VOUT VP VOUT
;
A1 A2 VREF
(22)
which is greatly attenuated by the open gain of the two feedback loops.
Figure 14(a) shows the simulated load regulation performance of the proposed LDO compared with a voltage follower
based LDO. Obviously, the proposed LDO has better load regulation due to the dual-loop based structure.
Fig. 14. Simulated (a) load regulation and (b) line regulation of the
proposed LDO and voltage follower based LDO.
loop output resistance of the proposed LDO is attenuated significantly by the open gain of the two feedback loops.
The load-dependent input-referred offset voltage is greatly
reduced by the dual-loop based structure also. As seen in
Fig. 13, VP is the voltage swing at the gate of power transistor due to the varying load current, which introduces the inputreferred offset voltage of the current feedback buffer (Vos-b /.
The output voltage shift due to Vos-b can be detected by the
reference tracking loop, responding with an increase or decrease of the integrator capacitor voltage Ve , which effectively compensates the systematic offset of the error amplifier.
The output voltage shift due to the systematic variation of VOS
is
3.2.4. Line regulation
Line regulation (LNR) performance, like load regulation,
is also a dc parameter and it refers to the output voltage variations arising from dc changes in the input supply. Power supply
variations affect the regulator in two ways: directly through its
own supply, and systematic supply-induced input-referred offset voltage:
gmp ROL
VOSS VOUT
VOUT
D
C
;
VIN
1 C AOL ˇ
VIN VREF
(23)
where gmp is the transconductance of the power device and
VOSS is the systematic variation of VOS with respect to a dc
change in supply voltage VIN . Similar to the analysis of load
regulation performance, due to the boosted open-loop gain and
attenuated input-referred offset voltage, the line regulation performance of the proposed LDO is improved significantly. Cir-
045005-7
J. Semicond. 2014, 35(4)
Parameter
Technology (m)
VOUT (V)
IOUT (mA)
CL (F)
IQ (A)
VOUT (mV)
Setting time (s)
Current efficiency (%)
Wang Han et al.
Table 1. Performance comparison with recent published works.
Ref. [17], 2003 Ref. [4], 2007
Ref. [1], 2008
Ref. [5], 2010
0.6
0.35
0.35
0.35
1.3
1.8
0.9
1.8
100
200
50
100
10
1
1
1–10
38
20
164
4
130
54
6.6
55
1.6
0.27
0.132
0.55
99.962
99.8
99.67
99.996
Ref. [7], 2010
0.35
1.2
100
NO
43
70
3
99.957
This work
0.6
1.8
300
3.3
113
97
0.142
99.962
the results, it shows that VOUT varies 0.3 mV and 0.47 mV, respectively, when VIN changes from 2 to 5 V for ILOAD D 1 mA
and ILOAD D 300 mA. When VIN D 2.5 V, VOUT varies about
1.02 mV when the load current changes from 1 to 300 mA. A
performance comparison with recent published linear regulators suitable for fast transient applications is given in Table 1.
5. Conclusion
An LDO regulator with a fast transient response is presented in this paper. The design details, including the transient response, small-signal response and steady state performance, have been presented. Both the simulation and experimental results confirm that with the joint efforts of the dualloop based structure, the dynamic biased circuit and an adapted
Miller compensation technique, the load transient response has
been enhanced significantly. Both the line and load regulations
are also improved due to the sufficient loop gain provided by
the dual feedback loops. Meanwhile, the quiescent current and
dropout voltage are maintained at low levels to achieve a high
power efficiency.
References
Fig. 17. (a) Measured line regulation for ILOAD D 1 mA and ILOAD D
300 mA. (b) Measured load regulation when VIN D 2.5 V.
cuit simulation is conducted to compare the line regulation of
the proposed LDO structures with a voltage follower based
LDO. The results are consolidated and shown in Fig. 14(b).
4. Experimental results
To verify the concept of the proposed linear regulator, a
prototype is implemented using 0.6-m CMOS technology.
Figure 15 shows the die photograph. The system was designed
to source a nominal output current of 300 mA with a 3.3 F
load capacitor. The minimum dropout voltage is approximately
200 mV. The maximum current efficiency is 99.962%. Figure
16 shows the measured load transient response when the loading current switches between 1 and 300 mA. The voltage spike
and the recovery time of the proposed LDO are about 97 mV
and 0.142 s respectively. The measured line and load regulations are shown in Figs. 17(a) and 17(b), respectively. From
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