International Journal of Research in Signal Processing, Computing & Communication-System Design
ISSN: 2395-3187
Volume: 01, Issue: 02, July-December, 2015
Design and Analysis of High Performance and
Low Power
Current Mode Logic CMOS
1
A. Rajesh1, Dr. B. L. Raju2, Dr. K. Chenna Kesava Reddy3
Assoc. Prof., ECE, ACE Engineering College,Hyd., rajeshakula07@gmail.com
2
Principal, ACE Engineering College, Hyd, blraju2@gmail.com
3
Ex-Principal, JNTU College Of Engineering,Jagityal,kesavary@yahoo.com
Abstract
With the scaling down of CMOS
transistors, many issues, once considered negligible, now
have become a factor in design. Some of these problems are
leakage current and power consumption. The solution this
paper will address is using current mode logic as opposed to
traditional voltages. We also begin by analyzing 180nm
MOSFETs and will continue to work down to lower channel
lengths. MOS Current-Mode Logic (MCML) is an
alternative logic designing style that provides true
differential operation, low noise level generation and noise
immunity
I.
Introduction
The recent advances in VLSI technology have allowed
rapid growth in the area of portable electronic devices. Laptop
computers, cellular phones, and personal desktop assistants have
all become commonplace items in people's lives. One of the
primary consumer complaints of these devices is the short
battery life and/or the extra weight of the batteries due to the
high power consumption of the circuitry. As CMOS process
technology scales and demand for more processing power
increases, it can be shown that the power consumption of future
IC's will increase over time if significant architectural changes
are not made [1]. It is therefore critical in future circuits that
power be minimized beyond the traditional constraints of
packaging cost and heat dissipation.
As device density increases, it is also extremely
desirable to integrate analog and digital circuitry onto the same
die for many DSP and communications systems. High levels of
integration will be required in order to reduce total system area
and drive down production costs. This integration has been
delayed due primarily to the difficulty in designed high precision
analog circuitry in the presence of extremely hostile digital
switching noise. These difficulties will also increase as process
technology scales due to fundamental challenges in high
precision analog design at low supply voltages in digital CMOS
technology. Either significant advances in analog design
techniques will be required or digital designers will be forced to
adapt their design style or process technology.
The scaling down of CMOS transistors has posed
new problems for designers. As the limits of size are being
reached, new logic styles will be needed to continue the trend.
Current mode logic (CML) was researched in the past, but may
offer a solution for today’s technology. CML implements some
analog components to compute logic. Typically, CML refers to a
logic style where voltages values still determine the logic values
of the inputs and outputs, but current is only used as an
intermediate variable. The basic structure consists of differential
pairs with dual outputs. The inputs steer the current down one
branch or the other to compute logic [3].
When designing High-Speed ICs with classical
CMOS technologywe encounter the problem that delay limits the
switching speed of the gate. We can improve the propagation
delay times via correctly sizingour transistor, as large W/L ratios
will result in a faster switching gate, but also in a bigger power
consumption, as we will see later.Some techniques developed to
improve the design of High-Speed circuits(as Complementary
Pass-Transistor Logic (CPL) or DifferentialCascode Voltage
Switch Logic (DCVSL)) showed that when differential signals
are used in the circuits, a compact design, a better noise
immunityand, in short, a better gate for this kind of High-Speed
operationcan be obtained. MOS Current-Mode Logic circuits
provide true differential operation,have the feature of low noise
level generation, and have static power dissipation: the amount
of current drawn from the power supply does not depend on the
switching activity. Due to this, MCML gates have been
discovered to be useful for analog and mixed-signal ICs.
This paper focuses on “true” CML where the input and
output values are actually currents .The basic method of
computation is current mirrors, which pass values by mirroring
currents through other transistors. CML offers a number of
advantages such as a reduced number of transistors and a smaller
area [1]. Also, given a supply voltage, the performance of a
CML gate can be optimized for delay, power, and the switching
noise. Previously, with static CMOS, the only real parameter that
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could be changed was the size. With a control over the current,
current as a parameter can be used to increase performance [1].
However, there are some drawbacks that will have to be
overcome. The supply current of a CML gate is independent
operating frequency; there will be static power dissipation.
However, at higher frequencies less power is dissipated than the
static CMOS counterparts [5]. This will lead a reduction in
voltage supply and current. However, scaling down these
parameters will lead to a greater impact of leakage current. In
particular if the nanoAmpere level is the target, it will be about
the same magnitude of the leakage current. Thus, the circuit
become less robust and is more prone to errors.
II. Current Mode Logic Gates
This ideal gate is presented in figure .1 below and consists of
three main parts: the pull up resistors, the pulldown network
switch, and the current source.
•
Static power dissipation.
•
More elaborated design process.
•
Larger number of design parameters.
•
Larger layout area because of the PMOS (resistors).
•
Larger interconnect area: differential routing.
As stated before the inputs and outputs to CML gates are
currents. A number of different implementations have been
explored; depending on the gate, logic “1” could be presence of
current with logic “0” being absence of current or visa versa.
As the communications industry is moving to faster
data speeds and from parallel- to serial-based technologies, the
variety of interfacing standards has led to concerns on how to
interface these different logic levels together. The main three
priorities for the industry have been to increase performance,
decrease power consumption, and reduce cost.
Earlier
technologies, such as emitter-coupled logic (ECL), used an
inconvenient negative power supply rail, which at
the time had the advantage of improved noise immunity. Since
the implementation of positive-supply technologies such as TLL
and CMOS, the older technologies no longer provide a benefit,
as a system using them would require several power supplies
including the –5.2 V or –4.5 V needed for ECL.
Fig.1 Ideal MOS Current Mode Logic
The inputs to the pull down network (PDN) are fully differential.
In other words, the true and complement off all logical inputs
must be presented to the gate. The PDN can implement any logic
function but must have a definite value for all possible input
combinations. In general, the design of the MCML pull down
network is similar to other differential logic styles such as
differential cascode voltage switch logic (DCVSL) or differential
split-level logic (DSL).
Advantages:
•
Differential circuit operation.
•
Low voltage swing - suitable for high speed.
•
Weak dependence of propagation delay on fanout load
capacitance(compared to CMOS).
As a result, ECL migrated to positive/pseudo emittercoupled logic (PECL), which allowed designers to move away
from this negative supply rail and simplify board layout. The
principle behind PECL was simply to keep the same output
swing of 800 mV, but shift it to a positive voltage by using a 5-V
rail and ground. Low-voltage positive/pseudo emitter–coupled
logic (LVPECL) is the same concept as PECL, but uses a 3.3-V
supply rather that the 5-V one. This resulted in a power
consumption reduction relative to PECL.
Additionally, as more and more designs use
CMOS-based technology, new high-speed drivers have been
introduced, such as current mode logic (CML), voltage mode
logic (VML), and low-voltage differential signaling (LVDS).
This has led to many combinations of switching levels within a
system that need to interface with each other.
Different types of drivers and receivers can be interfaced,
especially if ac-coupling is used.
When using ac-coupling, the drivers and receivers are treated
separately. AC-coupling is commonly used:
To interface different technology types
To interface different signal voltages e.g., 3.3-V driver
and 2.5-V receiver
•
Robust performance and better noise immunity.
•
Constant current drawn from the power source.
To interface different ground references between
driver and receiver
•
Does not generate significant switching noise.Power
dissipation superior to classical CMOS especially at
high operating speeds.
Note that when ac-coupling is used, the driver and
receiver can be treated separately
•
Disadvantages:
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Fig.4 MOS Current Mode Logic for AC Coupling
Fig.2.Structure for a CML Output Stage
The Low voltage differential signalling have CML
drivers that are built from an open-drain differential pair and a
voltage-controlled current source using NMOS transistors. The
outputs (Output+ and Output–) require pullup resistors to VDD
because the NMOS transistor can drive only falling edges
efficiently and needs the pullups to help drive rising edges. The
voltage-controlled current source is used to vary the amount of
current used to drive the load, because the output voltage swing
is load dependent. The load resistors and the external reference
resistor can then be chosen to optimize output voltage swings.
Current Mode Logic Driver-DC Coupled
CML drivers that use open-source NMOS transistors. In order to
drive rising edges, the drivers must have pullup resistors to
VDD. These pullup resistors should be equal to ZO to avoid
unwanted reflection due to unmatched lines.
Fig.5 MOS Current Mode Logicdifferential signalling
IV.Simulation Results
These are the simulation results for MOS Current Mode Logic
Differential Signalling using ideal current source.
Vdd=1.8V
Z0=50 ohms
Rload=50 ohms
Ibias= 16MA
For an input of Logic ‘0’
V1=Vdd
Fig.3 MOS Current Mode Logic for DC Coupling
Current Mode Logic (CML) Driver—
then V2= Vdd-(Ibias /2* Rload)
For an input of Logic ‘1’
V2=Vdd
then V1= Vdd-(Ibias /2* Rload)
AC-Coupled
In the case of ac-coupling, the CML driver again needs to be
pulled to VDD because the rising edge still needs to be driven.
On the receiver side, since the capacitor removes the dc
component of the incoming signal, the termination resistor
should be connected to a voltage that is set to the receiver
common-mode input voltage.
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Fig.6 Current Mode Logic Differential signalling
Fig.8 Current Mode Logic Differential signalling using
current mirror
Fig.9 Simulation Results of Current Mode Logic Differential
signallingfor output swing of 400mv
Fig.7 Simulation Results of Current Mode Logic Differential
signalling
V. Conclusions and Proposals
Based on our simulation, if CML is used in a high
frequency, high performance task, it has an advantage over static
CMOS. However, the robustness of the circuit still remains an
issue. It is greatly affected by leakage current and bias voltage.
In these cases static CMOS these problems for the most part do
not exist. These problems also made the CML gate difficult to
implement. From the tests that were run, it appears that CML
circuits may perform poorly if put in long chain.
In these preliminary tests, we used ideal current sources
whenever they were drawn that way in the figures. These will
have to later be replaced by MOS current sources. We believe
this will actually help, because MOS current sources themselves
have leakage current, whereas ideal current sources do not.
Biasing is another concern with the circuits. As lower voltage
and currents are applied, the precision of the bias voltage
becomes ever more important. It will clearly have a great effect
as the smaller transistors are used.
V. References
Fig.8 Current Mode Logic Differential signalling_2
[1] Ismail Enis Ungan and Murat Askar, A Wired-AND CurrentMode Circuit Technique in CMOS for Low-Voltage, HighSpeed and Mixed-Signal VLSIC, Analog Integrated
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Circuits and Signal Processing, pp. 59-70, November 18,
1996.
[2] K. Navi, A. Kazeminejad, and D. Etiemble, Performance of
CMOS Current Mode Full Adders, Proceedings of The
Twenty-fourth International Symposium on MultipleValued Logic, pp.27-34, May 27, 1994
[3] Jason M. Musicer, Jan Rabaey, MOS Current Mode Logic
for Low Power, Low Noise CORDIC Computation in
Mixed-Signal Environments, Proceedings of ISLPED,
2000, pp.102-107, July 26-27, 2000
[4] Jan Rabaey’s EE241 slides
[5] Vasanth Kakani, Delay Analysis and Optimal Biasing for
High Speed Low Power Current Mode Logic Circuits, 2004
IEEE International Symposium on Circuits and Systems.
IEEE Part Vol. 2, pp. II-869-872, May 23-26, 2004.
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