High-speed Serial Interface
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High-speed Serial Interface Lect. 6 – TX Driver and Equalizer 1 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Block diagram • Where are we today? Serializer Tx Driver Channel Rx Equalizer Deserializer Clock Recovery PLL Tx 2 Sampler Rx High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Classic output driver • An inverter can be used as voltage-mode output driver R R TTL output buffer 3 CMOS output buffer High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Classic output driver • It is difficult to use inverter-style output driver in high-speed applications – Full-swing logic is speed-limited because of slow switching time of inverter-style driver – Impedance matching is not easy • Transistors have variable output resistances during output voltage transients 4 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Single-ended signaling • • • Signal is transferred via single channel Simple but … Threshold should be generated in RX side. – Logic levels in TX may not be same as in RX side • Supply and ground levels are different for RX and RX sides • Poor noise immunity – Noises are added while signals travel through channel 50-Ω Channel 5 High-Speed Circuits and Systems Lab., Yonsei University Threshold generated in RX 2013-1 Differential signaling • Differential signals are transferred via two adjacent channels – Each signal has opposite logic level – Ex) twisted pair, differential PCB lines Positive channel Negative channel Differential 100Ω 6 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Differential signaling • Larger signal swing and self-reference – Signal = (positive signal – negative signal) Decision margin enhanced – threshold= (positive signal + negative signal)/2 • Common-mode noise rejection – Noise usually affects both positive and negative channels – Subtraction rejects common-mode noise Common-mode noise Positive channel Negative channel Differential 100Ω 7 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Current-mode driver • Reduced switching time – Current-steering: Switching current path while source current is kept constant. – Switching time is reduced since current source is not turned-off • Disadvantage I+ – Differential signaling is required. – Static current causes static power consumption Usually larger power consumption than voltage-mode 8 High-Speed Circuits and Systems Lab., Yonsei University I- Ibias 2013-1 50-Ω termination • Why 50Ω? – Historical issue • In early microwave systems, it was known that – 33Ω shows best performance in power transfer – 75Ω shows best performance in signaling – For convenience, 50 Ω was selected instead of medium value, 54 Ω • Nowadays, almost all high-speed instruments are 50Ω-based Significant for high-speed serial interface – In CATV systems, 75-Ω termination is still used 9 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 50-Ω termination • Tx-side termination topology – Voltage-mode driver has small output impedance Series termination 50-Ω Channel 50Ω 50Ω Voltage-mode Driver (Ro=0Ω) – Current-mode driver has large output impedance Parallel termination 50-Ω Channel Current-mode Driver (Ro=∞Ω) 10 50Ω High-Speed Circuits and Systems Lab., Yonsei University 50Ω 2013-1 DC- and AC-coupling • AC coupling with a series capacitor – Both TX and RX are possible – Common-mode voltage can be separately controlled in both side – Coupling capacitor can causes low-frequency loss Capacitance > 100nF is generally used. 50-Ω Channel 50Ω 50Ω Voltage-mode Driver 50-Ω Channel Current-mode Driver 11 50Ω High-Speed Circuits and Systems Lab., Yonsei University 50Ω 2013-1 DC- and AC-coupling • AC coupling cannot be used if consecutive identical bits are transmitted 8B/10B coding for many standards 50-Ω Channel 50Ω 50Ω Voltage-mode Driver 50-Ω Channel Current-mode Driver 12 50Ω High-Speed Circuits and Systems Lab., Yonsei University 50Ω 2013-1 Push-pull driver • 2 current sources 13 IN+ Positive channel 100Ω – Current path switching – Upper and lower pairs – Same rising and falling time INfor each differential signal – Upper PMOS pair can be replaced by NMOS pair to enhance switching time – Head room problem in lowINvoltage technologies – Used in Low-Voltage Differential Signals (LVDS) standard – TX termination? Negative channel IN+ Ibias High-Speed Circuits and Systems Lab., Yonsei University 2013-1 CML (Current-Mode Logic) driver • Loaded by 50ohm resistor VDD 50Ω 50Ω Positive channel Negative channel IN+ IN- Ibias VSS 14 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 100Ω – Current steering – Both side are terminated by 50Ω – Output voltage can be both DC, AC-coupled – Used in most high-performance serial link TX equalization • Channel causes ISI on received signal. – High-frequency loss in channel eye-diagram closed Tx Driver 15 Channel High-Speed Circuits and Systems Lab., Yonsei University Rx Sampler 2013-1 TX equalization • TX driver can be also channel equalizer – TX driver can enhance high-frequency components before traveling through channel. Tx Driver 16 Channel High-Speed Circuits and Systems Lab., Yonsei University Rx Sampler 2013-1 How to reject ISI? • FIR filtering – Forcing cursors to 0 can be implemented by FIR filtering. – ISI can be removed since we know input data in TX-side – Tx-side FIR filtering can include pre-cursor Subtract pre-cursor + Output Data - C-1 C0 D-1 Input Data (Digital) 17 Subtract Subtract 1st post-cursor 2nd post-cursor Main cursor C1 D0 1-bit Period Delay C2 D1 1-bit Period Delay D2 1-bit Period Delay High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Feedforward vs Feedback • DFE Decision Input Data (Digital) Channel + - - C3 C2 D3 Output Data (Digital) C1 D1 D2 1-bit Period Delay 18 Sampler Equalization 1-bit Period Delay High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Pre-/De-Emphasis – Tx FIR is often called Pre-/De-Emphasis • De-emphasis: to reduce low-frequency components • Pre-emphasis: to enhance high-frequency components – High-frequency component is transition bits Normal Waveform Nominal swing Nominal swing De-emphasis Waveform Pre-emphasis Waveform 19 Nominal swing High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Circuit implementation • Current-mode drivers can be easily used for pre/de-emphasis – It is very easy to modify drivers into current-mode adder including controllable gain VDD 50Ω Positive channel Negative channel D 0+ D 0- D 1- D 1+ Main cursor C0 100Ω 50Ω 1st post-cursor C1 VSS 20 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Circuit implementation • Simultaneous implementation of pre-/de-emphasis – D1=D0 Vout,diff = +/-50 x (C0-C1) De-emphasis – D1≠D0 Vout,diff = +/-50 x (C0+C1) Pre-emphasis – Level difference is defined as sum and subtract VDD 50Ω Positive channel Negative channel D 0+ D 0- D 1- 100Ω 50Ω D 1+ 50x(C0+C1) 50x(C0-C1) Main cursor C0 1st post-cursor C1 VSS 21 High-Speed Circuits and Systems Lab., Yonsei University -50x(C0-C1) -50x(C0+C1) 2013-1 Tx- vs. Rx- equalization • Tx equalization – Consumes large power – Enlarged output signal improves SNR at Rx side – Easy implementation • Rx equalization – Relatively low power consumption – More complex implementation (especially DFE) – For best performance, LE and DFE combination 22 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Design example “4-Channel 3.2/6.4-Gbps Dual-rate Transmitter” 김두호, 최우영 대한전자공학회 논문지 2010 4ch transmitter with 1-tap pre-emphasis Dual-rate (3.2/ 6.4 Gbps) 130nm CMOS technology / COB package 600mW dissipation @1.2V power supply 23 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Design example • 4-channel transmitter sharing a clock generator – 2:1 serializer function is included in pre-emphasis circuit – Displayport application 24 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Design example • Clock generator performance – PLL jitter is main performance metric of transmitter evaluation. 3.2Gb/s 25 6.4Gb/s High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Design example • De-emphasis waveform 3.2Gb/s 26 Vswing=600mVdiff / De-emphasis=1/3 Vswing=600mVdiff / De-emphasis=1/2 Vswing=600mVdiff / De-emphasis=2/3 Vswing=600mVdiff / De-emphasis=1 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Design example • De-emphasis waveform 6.4Gb/s 27 Vswing=600mVdiff / De-emphasis=1/3 Vswing=600mVdiff / De-emphasis=1/2 Vswing=600mVdiff / De-emphasis=2/3 Vswing=600mVdiff / De-emphasis=1 High-Speed Circuits and Systems Lab., Yonsei University 2013-1
