Board-Level Test Technologies
Extending IEEE Std. 1149.4
Analog Boundary
Modules to Enhance
Mixed-Signal Test
Uroš Kač and Franc Novak
Florence Azaïs, Pascal Nouet, and Michel Renovell
Jozef Stefan Institute
LIRMM
with support from component manufacturers as well as EDA tool and test equipment providers. Its mixed-signal twin, on
the other hand, has had a much harder
time finding its way into real-life applications. Although research has focused
on IEEE 1149.4,5,6 and technology
demonstrator chips for evaluating its proposed features exist,7,8 Dot 4 lacks support in standard catalog devices, making it difficult for
designers to include a standardized mixed-signal test
infrastructure in their systems. The absence of commercial Dot-4-compliant devices could be due to the
test infrastructure’s complexity and its potential impact
on proven analog and mixed-signal designs. The benefits of including overhead logic in the circuit must justify the effort required to do so. For example,
applications aided IEEE 1149.1’s acceptance by
demonstrating its value not only in the design testability domain but also in areas such as design validation,
debugging, and in-system configuration of programmable devices.9
The work of Sunter and colleagues on a general-purpose Dot-4-compliant IC attempts to improve the standard’s status.9,10 As designers demonstrate the benefits of
practical mixed-signal designs and present interesting
applications based on the Dot 4 infrastructure, interest in
the standard will increase. Several researchers have
already reported innovative Dot-4-based measurement
procedures.9,11,12 We describe a Dot 4 test chip with extensions to the original 1149.4 test infrastructure that expands
possible practical applications of the standard.
Editor’s note:
Will it or won’t it? The 1999 IEEE 1149.4 Standard for a Mixed-Signal Test Bus
is on the cusp of industrial acceptance, but it’s not clear whether industry will
pick it up. This study, by two leading European research institutes, delves
into the details of hardware implementation and, in so doing, contributes to
the growing literature on this topic.
—R.G. (Ben) Bennetts, Bennetts Associates
INCREASINGLY DENSE and complex electronic
designs have made established in-circuit test (ICT) techniques more costly and difficult to implement. Several electronic systems manufacturers, such as Philips and IBM, have
proposed an innovative boundary scan method to improve
design controllability and observability. The method is
based on ICT techniques, but it substitutes physical nails
with an on-chip shift register placed around the IC core
boundary. This boundary scan register captures IC input signals and applies test vectors on IC outputs through its parallel I/Os. Test data is shifted in and out through a simple
serial interface, eliminating the need for direct physical
access.1 In 1990, as part of the Joint Test Action Group’s
(JTAG) initiative, the IEEE adopted the approach as IEEE
1149.1.2 Because IEEE 1149.1 addressed only digital circuits,
designers soon began developing equivalent test structures
for mixed-signal circuits and corresponding measurement
methodologies.3 Standardization efforts on an IEEE-1149.1compatible test bus that would improve mixed-signal
design testability at both the device and the assembly level
led to the IEEE 1149.4 (known as Dot 4) standard in 1999.4
The IEEE 1149.1 boundary scan standard has
become a widely accepted design for digital circuits,
32
0740-7475/03/$17.00 © 2003 IEEE
Copublished by the IEEE CS and the IEEE CASS
IEEE Design & Test of Computers
Implementing the Dot 4 test chip
Common reference voltage
VH
Pin5
Core5
Pin4
Core4
Pin3
VTH
ABM5
ABM6
ABM4
ABM7
ABM3
ABM8
Pin6
Core6
Pin7
Core7
Pin8
Core8
AB1
Core3
VG
VL
Pin2
ABM2
Core2
Pin1
ABM1
Core1
Pin9
ABM9
Core9
AB2
We approached the design of the Dot 4 test chip in two
stages. Our preliminary chip, shown in Figure 1, adheres
to the standard IEEE 1149.4 architecture. Thus, we can
assess the actual characteristics of complex mixed-signal
cells—analog boundary modules (ABMs) and a test bus
interface circuit (TBIC)—and identify possible design inefficiencies and necessary modifications. To simplify design
debugging, we implemented the test access port (TAP)
controller, instruction and bypass registers, and decoder
off chip with a programmable logic device (PLD).
The design follows schematic representations of the
boundary scan register modules proposed in the IEEE
1149.4 standard. We implemented three main cells: the
ABM, the TBIC, and the test control circuitry, each comprising several submodules. Because we wanted users to
be able to test the Dot 4 infrastructure in their own designs,
we didn’t include an analog functional core. Although
IEEE 1149.4 lets designers implement conceptual switches differently, transmission gates are most appropriate for
CMOS-based devices. Figure 2 shows an ABM cell’s analog-switching architecture.
We implemented the preliminary chip in 0.8-micron
Austria Microsystems (AMS) CYE technology. The relatively high internal resistance exhibited by standard
AMS library switch cells required that we modify the
design to obtain transmission gates suitable for inclusion in the ABM/TBIC analog-switching architecture.
Similarly, because standard cell comparators would
occupy an unacceptably large silicon area, we designed
a custom comparator, which satisfies our requirements
both in terms of silicon area and electrical characteristics. Table 1 compares the library and modified
switched cell. Table 2 compares the standard library
and custom comparators.
AT1
AT2
TBIC
Dot 4 test chip
TDI
Mode1
TDO
Update_DR
Clock_DR
Shift_DR
Mode2
Common test control signals
TAP controller
Complex programmable logic device
AB
ABM
AT
TAP
TBIC
TDI
TDO
Analog bus
Analog boundary module
Analog test pin
Test access port
Test bus interface circuit
Test data input
Test data output
Figure 1. Preliminary test chip block diagram.
We use this chip to assess complex mixedsignal cell characteristics and identify design
deficiencies and modifications.
Table 1. Comparison of area and resistance between library and modified switch cell.
Cell
Surface area (µm2)
Dimensions (µm)
RON at VDD (Ω)
TG2B (library)
16.2 × 34.5
559
1,620
TG_inv (modified, integrated inverter)
26.8 × 39.7
750
750
Table 2. Comparison between library and custom comparator implementations.
Offset
Voltage
Vout min
Vout max
Vth min
Vth max
Surface
(µV)
gain AV (dB)
(mV)
(V)
(V)
(V)
area (µm2)
Comp01B (library)
27
87
3
5
0.1
4.4
= 23,000
Comparator (full custom)
92
61
17
5
0.1
4.6
= 2,800
Cell
March–April 2003
33
Board-Level Test Technologies
Reference voltages
VH
VTH
VL
modified the ABM cell in three key ways:
VG
■
SH
SL
Switching
architecture
SG
SD
Pin
Core
SB1 SB2
AB2
AB1
Control-decoding
logic
Mode2
Mode1
■
■
Update_DR
Clk
D
D
Shift_DR
G
D
Clk
D
D
D
Clk
B1
D
D
Clk
B2
D
D
Update
register
To TDO
We excluded the core disconnect
switch from the ABM switching
architecture and implemented it as
a separate cell consisting of a lowresistance (RON < 50 Ω) CMOS transmission gate, where RON is the
transmission gate resistance during
the ON state. Users can take advantage of this low-resistance switch or
implement the core disconnect facility in their own analog designs.
We added two switches to provide
ABM analog test bus multiplexing.
We added switches to connect the
ABM comparator’s inverting input to
either VTH or one of the VH, VL, or VG
common reference voltages.
Applying the extended ABM
functionality
Figure 4a shows how digital boundary
modules isolate the core from external cir0
From TDI
Clk
Clk
Clk
Clk
cuitry during internal test (Intest). During
Clock_DR
digital Intest, digital boundary modules
Analog boundary module
isolate the core from the I/O pins while
the tester applies test vectors and moniFigure 2. Schematic representation of an analog boundary module (ABM).
tors responses. On the other hand, accordWe divided the ABM into four submodules to simplify future modifications
ing to IEEE 1149.4, the analog INTEST
of the design.
instruction keeps external circuitry connected to the analog core. This requires
Synthesizing the control logic and registers was rel- controlling the external onboard circuitry to provide
atively straightforward. Figure 3 shows the test chip lay- appropriate operating conditions to the core or to ensure
out. Altogether, we laid nine ABM cells and one TBIC that the inputs are quiescent.
To circumvent this practical limitation in the origon an active area of 1,980 × 1,980 square microns, featuring 39 pads connected to five control signals (Mode1, inal ABM structure, we introduce two additional
Mode2, Update_DR, Shift_DR, and Clock_DR); two digi- switches, SB1_INT (internally switch to bus 1, AB1)
tal test signals (TDI and TDO); two digital power supply and SB2_INT, which bypass the core disconnect
lines (VDD and GND); two analog power supply lines switch (SD), as Figure 4c illustrates. This lets design(VDDA and GNDA); two analog test signals (AT1 and AT2); ers open SD during the INTEST instruction, eliminatand 18 pairs (pin and core) of ABM functional signals. ing the need to control external circuitry and
We directly synthesized the TAP controller, bypass and simplifying test development.
The proposed ABM modification does not replace
instruction registers, and instruction decoding logic from
RTL VHDL source code and programmed them into a the original INTEST instruction but rather adds an
Xilinx XC95108 complex PLD for a total of 38 macro cells. instruction, letting the designer perform Intest with the
The second version of the Dot 4 test chip incorpo- core disconnected from the surrounding circuitry. For
rates both analog and digital components and includes extended Intest procedures on a multiple input analog
extensions that let us implement alternative test and core, this approach is limited: The analog stimulus genmeasurement procedures. To realize this version, we erator can drive only a single input through the analog
1
34
Data
CTRL
Bus1
Bus2
Control
register
IEEE Design & Test of Computers
VL
Pin3
Pin7
Core1
Core7
Pin2
Pin8
Core1
Core8
Pin1
AT1
Core0
AT2
Pin0
VDDA
VDDA
VSS
VSS
Shift_DR
D
Shift_DR
Clock_DR
VSS
Figure 3. Preliminary test chip layout. Nine ABMs and one
TBIC cell are laid out starting from the bottom left. To
simplify debugging, we did not include the TAP controller on
the chip.
VH
VL
VG
G
SH
Core
SL
SG
SD
Pin
D
Pin ON
Core
1
Clk
From TDI
Mode2
VDD
Mode1
VSS
Scan_in
V
VDD
VTH
0
1
G
Pin6
Core6
Mode
Pin OFF
VG
Core3
To TDO
Pin
VTH Pin4 Core4 Pin5 Core
VH 5 VH
Scan_out
test bus. We therefore include switch SG_INT, which
connects the remaining core inputs to the known reference voltage, VG, as Figure 4c shows.
The original and modified ABM architectures suit
different types of test strategies. The modified ABM
structure allows system-wide functional reconfiguration, which might prove useful in analog functional
tests. As Kac et al. have demonstrated, designers can
reconfigure select analog functional blocks into a selftesting structure by establishing connections via the
Dot 4 analog test bus, and thus perform efficient go/nogo functional tests.13
Consider, for example, a device with an active resistor-capacitor (RC) filter core, as depicted in Figure 5
(next page). The core input and output are connected
to ABMs. By connecting the filter to an external circuit
(an equalizer) via the Dot 4 analog test bus, we can perform an oscillation-based test. We can then measure the
resulting frequency onboard with a simple digital
counter and compare it to a preloaded reference value.
An experiment verified this idea’s feasibility. Figure 6
shows the resulting oscillation, and Table 3 gives measurement results, where Rb determines the equalizer
voltage gain and fOSC denotes the resulting oscillation
frequency.
Update_DR
Clk
External
load
Clock_DR
(a)
(b)
VTH
VH
SH
VL
SL
SB1
SB2
AB1
AB2
VG
SG
Pin
Pin OFF
SD
SG _INT
Core
External
load
(c)
SB1
SB2
S1_INT
S2_INT
AB1
AB2
Figure 4. Isolating the core during Intest procedures: digital boundary module (a), ABM switching architecture
(b), and modified ABM switching architecture (c).
March–April 2003
35
Board-Level Test Technologies
IC
ABM1
Analog
core
(RC filter) ABM
2
AB2
External
circuitry
AB1
AT1
TBIC
Equalizer
System test bus
AT2
Figure 5. Active resistor-capacitor (RC) filter functional test. We connect the filter to an equalizer using the Dot 4
analog test bus, then perform the oscillation-based test.
VH
IC1
Voltage
comparator
logic signal
(Cmp)
VTH
IC2
Vshort
ABM11
RSHORT<<RON+RPAD
SH
CMOS
switch
RON
Out1
VTHvariations
ABM21
Cmp21
In1
1
Pad
RPad
VshortH
CPad
PAD
VshortL
Pad
ABM12
RON
Pad
Out2
In2
Cmp22
SL
(a)
ABM22
(b)
VL
Vin
0
VL
VTHmin
VTH
VTHmax
VH
Figure 6. IEEE 1149.4 interconnect test (Extest): A bridging fault produced an intermediate-level voltage on
analog input pins (a). Variations in ABM comparator threshold levels can lead to a fault passing undetected (b).
Table 3. Measurement results for direct and analog test bus connections.
Connection type
Rb (kΩ)
fOSC (Hz)
Direct
241
1323
Via analog test bus
297
1323
In the original IEEE 1149.4 ABM structure, the control-decoding logic derives the control signals for
each switch from the update register contents and
the global mode signals, both of which the TAP
36
instruction decoder supplies (Figure 2). The extended ABM switching architecture requires additional
control signals, which can be provided in different
ways. Because switches (SB1, SB2, and SG) and
(SB1_INT, SB2_INT, and SG_INT) represent two complementary groups, they can use the same update
register codes for the control, provided the instruction decoder supplies an additional global control
signal (Mode3) during the extended INTEST instruction. Table 4 shows how we modified the equations
for this instruction.
IEEE Design & Test of Computers
The hardware overhead is therefore relatively
small, encompassing the additional ABM switches, the
modified ABM control-decoding logic, and the additional global control line. Because switches SB1_INT,
SB2_INT, and SG_INT introduce additional parasitic
capacitances to the signal path, minimizing their
impact on the analog design functionality requires
careful modeling.
Our second modification to the ABM cell lets us
compare analog input signals to multiple voltage levels.
We add switches CG, CL, CH, and CTH, where C is compare, to the ABM switching structure, as Figure 7a illustrates. These switches connect the comparator inverting
input to either VTH (mandatory) or one of the VH, VL, or
VG common reference voltages (our extension). This
feature augments the diagnostic capability of interconnect test (Extest).
Assume the tester encounters a bridging fault during
Extest, as Figure 6a illustrates. In the preliminary chip
implementation (see Figure 2), we implemented SH and
SL with identical CMOS transmission gates. These gates
exhibit substantial ON-resistance and are connected in
series with reference voltage sources. As IEEE 1149.4 notes,
the voltage at the combined (shorted) net will be at some
value between VH and VL. Designers should choose a compare voltage, VTH, that is clearly different from the possible
input voltage levels. On the other hand, IEEE 1149.4 limits
the value of VTH value to the range, (VH + VL)/2 ± (VH – VL)/4.
Suppose the resulting voltage of the bridging fault depicted
in Figure 6a is near the threshold voltage VTH of IC2. As
Table 4. Control equations for the extended INTEST instruction, where
B, C, and D refer to update register cells (shown in Figure 2), and M
refers to mode.
Switch
SG
Original equation
–
SG = CDM1M2
SB1
SB1 = B1M1
SB2
SB2 = B2M2
SG_INT
NA
SB1_INT
NA
SB2_INT
NA
Modified equation
–
––
SG = CDM1M2M3
––
––
SB1 = B1M1M2 M3
––
––
SB2 = B2M1M2 M3
–
––
SG_INT = CDM1M2M3
––
SB1_INT = B1M1M2M3
––
SB2_INT = B2M1M2M3
Figure 6b shows, variations in comparator threshold levels
cause the ABM21 comparator to identify the input voltage as
high logic and the ABM22 comparator as low logic. Hence,
the fault can pass undetected.
If we shift the comparator threshold voltage to level
VH2 in ABM21 and VL2 in ABM22, we can clearly detect the
bridging fault, as Figure 7b illustrates. Dot 4 states that
VH and VL should always be available on both input and
output pins and can be pin specific—that is, they do
not have to be the same on all pins. Therefore, designers can choose appropriate VH2 and VL2 values for IC2
input pins (In1, In2) such that the comparators maintain
a sufficient noise margin for both fault-free input voltage levels (VH and VL). Because Extest does not require
high-precision voltage levels, simple MOS voltage
dividers can generate VH2 and VL2 on chip. Alternatively,
external sources can supply the required multiple voltVoltage
comparator
logic signal
(Cmp)
VG VL VH
VTH
VH2
IC2
ABM21
ABM
CG CL CH CTH
SG SL SH
Vcmp
Pad
Cmp
SB1
(a)
Cmp22
ABM22
Vcmpcontrol
VTH
VH2 VH1
1
Pad
In2
AB1 AB2
VIn1
0
VL1
Core
SB2
Vshort
Cmp21
Vshort
SD
Vin
Cmp21
In1
1
VL2
Cmp22
Vshort
VIn2
0
VL1
VL2
VTH
VH1
(b)
Figure 7. Controlling VTH during interconnect test (Extest): Added switches CG, CL, CH, and CTH connect the
comparator inverting input to either VTH or VH, VL, or VG (a); shifting the comparator threshold voltage to level VH2
in ABM21 and VL2 in ABM22 makes the bridging fault easily detectable (b).
March–April 2003
37
Board-Level Test Technologies
FUTURE WORK will focus on functional reconfiguration
strategies exploiting the proposed core disconnect feature. In particular, we shall explore possible reconfigurations of different types of analog circuits into
oscillation-based test structures. We also plan to work
on applications of the modified ABMs that allow testers
to compare analog input signals with multiple voltage
levels. In addition to the enhanced interconnect test we
describe, the comparator input can be connected to different sensors, thus allowing the system to monitor its
environment via the Dot 4 infrastructure.
■
Table 5. Control equations for the modified EXTEST instruction.
Switch
SH
Original equation
SG
SH = CDM1M2
–
SL = CDM1M2
–
SG = CDM1M2
CH
NA
CL
NA
CG
NA
CTH
NA
SL
Modified equation
––
SH = CDM1M2M3
–
––
SL = CDM1M2M3
–
––
SG = CDM1M2M3
CH = CDM1M2M3
–
CL = CDM1M2M3
–
CG = CDM1M2M3
––
CTH = M3
Acknowledgments
ages through additional, common voltage reference
pins.
Like the modified INTEST instruction, the modified
EXTEST instruction requires additional control signals,
which can be similarly provided. Switches SH, SL, and
SG on the input pins are always open during conventional Extest; consequently, a common signal can disable them and the modified EXTEST instruction can
use their update register codes to control switches CH,
CL, and CG. Again, we combine the global mode signals with the codes to produce the switch control signals, as Figure 7 shows. Table 5 shows how we changed
the control equations to support the modified EXTEST
instruction.
Figure 8 depicts a trivial implementation of the modified ABM control-decoding logic.
We performed this work as part of the bilateral
French-Slovenian Proteus project, which is supported
by the French Ministry of Foreign Affairs and the
Slovenian Ministry of Education, Science, and Sport.
References
1. R.G. Bennetts, IEEE 1149.1 Test Access Port and
Boundary-Scan Std., DFT Technology Backgrounders,
Feb. 2001, http://www.semiconductorfabtech.com/dft/
tutorial/bscan.PDF.
2. IEEE Std. 1149.1-2001, IEEE Standard Test Access
Port and Boundary-Scan Architecture, IEEE, 2001.
3. K.P. Parker, J.E. McDermit, and S. Oresjo, “Structure
and Metrology for an Analog Testability Bus,” Proc. Int’l
Test Conf. (ITC 93), IEEE Press, 1993, pp. 309-317.
SD
SG_INT
CG
CL
CH
SG
SL
SH
SG2_INT
SB2
SB1
SG1_INT
CTH
Switch control signals
Control-decoding
logic
Mode1
Mode2
Mode3
Update_DR
Clk
D
D
Clk
C
D
Clk
B1
D
Update
register
Clk
B2
D
From control register
Figure 8. Modified ABM control-decoding logic for extended Intest and Extest.
38
IEEE Design & Test of Computers
4. IEEE Std. 1149.4-1999, IEEE Standard for a MixedSignal Test Bus, IEEE, 1999.
5. A. Cron, “IEEE 1149.4—Almost a Standard,” Proc. Int’l
Test Conf. (ITC 97), IEEE Press, 1997, pp. 174-182.
6. K.P. Parker, The Boundary-Scan Handbook: Analog and
Digital, Kluwer, 1998.
7. “JTAG Analog Extension Test Chip: Target Specification
for the IEEE P1149.4 Working Group,” Preliminary
Review 012, Keith Lofstrom Integrated Circuits, Beaver-
Franc Novak heads the Computer
Systems Department at the Jozef Stefan Institute and is an associate professor on the Faculty of Electrical
Engineering and Computer Science at
the University of Maribor. His research interests include
electronic testing and diagnosis, fault-tolerant computing, and DFT of analog circuits. Novak has a PhD in
electrical engineering from the University of Ljubljana.
ton, Ore., 1998; http://grouper.ieee.org/groups/1149/4/
kl1p.html.
8. K.P. Parker et al., “Design, Fabrication, and Use of
Mixed-Signal IC Testability Structures,” Proc. Int’l Test
Conf. (ITC 97), IEEE Press, 1997, pp. 489-498.
9. S. Sunter et al., “A General Purpose 1149.4 IC with HF
Analog Test Capabilities,” Proc. Int’l Test Conf. (ITC 01),
IEEE Press, 2001, pp. 38-45.
10. National Semiconductor, “Mixed-Signal Test, and
the IEEE 1149.4 Standard,” http://www.national.com/
appinfo/scan/.
Florence Azaïs is a researcher for
the National Council for Scientific
Research (CNRS) in the Microelectronics Department of LIRMM (the
Laboratory of Computer Science,
Robotics, and Microelectronics in Montpellier, France).
Her research interests include fault modeling and
mixed-signal circuit testing, especially DFT and BIST
techniques. Azaïs has a PhD in electrical engineering
from the University of Montpellier.
11. K. Lofstrom, “Early Capture for Boundary Scan Timing
Measurements,” Proc. Int’l Test Conf. (ITC 96), IEEE
Press, 1996, pp. 417-422.
12. S. Sunter and B. Nadeau-Dostie, “Complete, Contactless
I/O Testing—Reaching the Boundary in Minimizing Digital
IC Testing Cost,” Proc. Int’l Test Conf. (ITC 02), IEEE
Press, 2002, pp. 446-455.
13. U. Kač et al., “Alternative Test Methods Using IEEE
1149.4,” Proc. Design, Automation, and Test in Europe
(DATE 00), IEEE CS Press, 2000, pp. 463-467.
Uroš Kač is a research assistant at
the Jozef Stefan Institute in Ljubljana,
Slovenia, where he is also pursuing a
PhD. His research interests include
high-level synthesis, mixed-signal test,
and online/concurrent built-in self-test (BIST). Kač has
an MS in electrical engineering from the University of
Ljubljana.
March–April 2003
Pascal Nouet is a researcher at
LIRMM and an associated professor
at the University of Montpellier’s Institute for Engineering Sciences. His
research interests include analog circuit design and test, and design, test, modeling, and
characterization of monolithic microelectromechanical
systems. Nouet has a PhD in microelectronics from the
University of Montpellier.
Michel Renovell heads the Microelectronics Department at LIRMM. His
research interests include fault modeling, analog testing, and FPGA testing. Renovell has a PhD in electrical
testing from the University of Montpellier.
Direct questions and comments about this article
to Uroš Kač, Jozef Stefan Institute, Jamova 39, 1000
Ljubljana, Slovenia; uros.kac@ijs.si.
39