Vol. 37, No. 1
Journal of Semiconductors
January 2016
A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT
switch
Zheng Zonghua(郑宗华)1; 2 , Sun Lingling(孙玲玲)2; Ž , Liu Jun(刘军)2 ,
and Zhang Shengzhou(张胜洲)1; 2
1 Institute
of VLSI Design, Zhejiang University, Hangzhou 310027, China
Key Laboratory for RF Circuits and Systems of Ministry of Education, Hangzhou Dianzi University,
Hangzhou 310037, China
2 The
Abstract: A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple
capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion
loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the
switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can
greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and
exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8–3 dB at 30–65 GHz by layout
simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps < 4 dB at 30–64 GHz. The measured
isolation is better than 25 dB at 30–64 GHz and the measured return loss is better than 10 dB at 30–65 GHz. A
measured input 1 dB gain compression point of the switch is 13 dBm at 52 GHz and 15 dBm at 60 GHz. The
simulated switching speed with rise time and fall time are 720 and 520 ps, respectively. The active chip size of the
proposed switch is 0.5 0.95 mm2 .
Key words: feed-forward compensation; series-shunt; single-pole double-throw (SPDT) switch; CMOS
DOI: 10.1088/1674-4926/37/1/015001
PACS: 84.32.Dd
EEACC: 2570D
1. Introduction
With the development of wireless communication technology, the demand of a broad bandwidth and high data rate wireless local area network (WLAN) systems is growing rapidly.
The spectrum around 60 GHz (frequencies of 57–64 GHz) has
been released for unlicensed in North America and Korea, 59–
66 GHz in Europe and JapanŒ1 . The scaling down of CMOS
technologies shows great agreement for integration of the RF
transceiver on a single die. A SPDT transmit/receive (T/R)
switch can be employed so that a single antenna can be shared
between the transmitter and the receiver to save area and cost
of the chip.
The T/R switch is an important function block in any
time-division duplexing (TDD) based RF transceiver frontend, which consists of one transmission branch and one reception branchŒ2 . There is still great challenge for designing
of millimeter-wave T/R switch with low insertion loss, high
isolation, and large power-handling capability, since the coupling of the RF signals to the semi-conductive silicon substrate increases significantly with the frequency increasing in
the CMOS process. By now, several switches for v-band radios have been demonstrated in the CMOS processŒ3 6 . In
Reference [3], Ta et al. demonstrated a 60-GHz series-shunt
SPDT switch in 130-nm CMOS, which exhibits an insertion
loss from 4.5 dB to 5.8 dB, and isolation from 24.1 to 26 dB.
The SPDT switch in Reference [4] had an insertion loss of
less than 3.3 dB from 50 to 94 GHz and isolation higher than
27 dB from 50 to 110 GHz with the traveling wave concept
topology. Tang et al. proposed a traveling-wave single-pole
double-throw (SPDT) switch using slow-wave coplanar waveguidesŒ5 , which reached an insertion loss of 2.8 dB and an isolation of 20 dB at 60 GHz. In Reference [7], Yeh et al. designed
the resistive body floating by using a large resistor to bias the
bulk to improve power handling capability (P1dB / of the switch
in the modern triple-well CMOS process.
In this paper, a high performance T/R SPDT switch is
demonstrated which is implemented in the TSMC 90 nm
CMOS process. By using the proposed feed-forward compensation network and the body-floating technique, the seriesshunt topology switch can be adopted in 60 GHz. The measured insertion loss achieves 2.45 dB at 52 GHz and keeps
< 4 dB at 30–64 GHz, the isolation is better than 25 dB at 30–
64 GHz at the Tx mode, which somewhat deviates from the
layout simulation results of an isolation of 27 dB at transmitter
mode (Tx), and the insertion loss of 1.8–3 dB at 30–65 GHz;
the results are analyzed.
2. Circuit design
The circuit schematic is shown in Figure 1. The seriesshunt topology has been demonstrated as an effective way to
design the SPDT switchŒ2 . Series transistor M1 is in deep triode while series transistor M2 is in cut-off in the transmit mode.
Meanwhile, M3 and M4 are in cut-off while M5 and M6 are in
deep triode in the transmit mode. But this typology is only ef-
* Project supported by the National Natural Science Foundation of China (Nos. 61331006, 61372021).
† Corresponding author. Email: sunll@hdu.edu.cn
Received 9 March 2015, revised manuscript received 25 May 2015
© 2016 Chinese Institute of Electronics
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J. Semicond. 2016, 37(1)
Zheng Zonghua et al.
Figure 1. Circuit schematic of proposed SPDT T, R switch.
fective for low RF frequency because of the high insertion loss
caused by the series switch and substrate parasitics in high frequency. This design adopts double-shunt topology, and each
shunt transistor (M3, M4, M5, M6) is connected with an inductor (L1 , L2 ) which is implemented by one microstrip transmission line. A loss compensation technology is proposed to
reduce the insertion loss. The feed-forward compensation network is composed of a couple capacitor (C1 , C2 ), a paralleled
MOSFET (M7, M8) and a paralleled inductor (L3 , L4 ). The
reason why the compensation network can improve the performance of the SPDT switch are given as follows. One reason is
that it can reduce the loss by coupling some signal to the M7
and M8 for amplifying through the gate couple capacitance.
The other reason is that it makes the on-state resistor small by
a paralleled resistor when the compensation MOS transistors
(M7, M8) are on, and the inductance L3 and L4 together with
the total capacitance will result in parallel resonance, which
can improve the isolation. The advantage of this method is that
it not only can improve the isolation of the SPDT when the
shunt MOS transistor is turned on for low resistor, but also can
form the artificial transmission line facilitating the signal to
pass through when the shunt MOS transistor is turned off as a
capacitor. Besides, resistive body floating (RBF) is also introduced by grounding the bulk with a large resistor, which can
allow a negative signal swing larger than the reverse breakup
voltage of the parasitic junction diodes in the source-bulk and
drain-bulk. By which, one can alleviate distortion and increase
the power handling capabilityŒ7 .
The gate bias (0 V/1.2 V) is applied through a large resistor (5 k/ to prevent RF signal leakage. The size of MOS
transistors is chosen carefully. To provide a very low resistance
in the on-state, the transistor is typically chosen with a large
width, but this leads to increase the parasitic of capacitance at
high frequencies, which can have a large impact on the insertion loss. Besides, concerning the power-handling capability,
large devices are used for series transistors, and a small size
is used for the shunt ones. The total gate width of the NMOS
transistors used in this design M1 and M2 is 30 m with a unit
finger length of 2 m, M7 and M8 is 36 m with a unit finger length of 2 m, and M3–M6 is 20 m with a unit finger
length of 2 m, selected by a layout simulation in Cadence. The
on-state shunt transistor resistance (Ron / is 6.9 , which is so
Figure 2. Measured and simulated insertion loss of the SPDT switch
for the Tx mode.
small that it can short the RF signal to the ground to improve the
isolation, and the off-state shunt transistor capacitance (Coff / is
around 31.8 fF, together with the inductor L1 and L2 as the
matching networks.
3. Experimental results and performance analysis
The proposed broadband SPDT switch was implemented
using the 90 nm CMOS process. The switch is designed to 50 
characteristic impedance on each port. All the passive components are simulated by ADS Momentum to get .S2P files, and
co-simulate with the MOSFETs in Cadence. Figure 2 indicates
the designed switch with the layout simulation insertion loss
from 1.8–3 dB and isolation of 21–32 dB at 30–65 GHz. The
measured minimum insertion loss is 2.45 dB at 52 GHz and
keeps < 4 dB at 30–64 GHz. Figure 3 shows that the return
loss of the transmitter port and the antenna port are better than
10 dB at 30–64 GHz. The input 1 dB compression point of the
switch reaches 13 dBm at 52 GHz and 15 dBm at 60 GHz as
shown in Figure 4. The simulated switching speed of the SPDT
switch at 52 GHz is shown in Figure 5. The rise time and fall
time are 720 ps and 520 ps, respectively. The switching speed
can be improved by decreasing the values of the gate resistors.
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J. Semicond. 2016, 37(1)
Zheng Zonghua et al.
Figure 3. Measured and simulated return loss of the SPDT switch for
the transmitter port and antenna port.
Figure 5. Simulation of switch’s speed using a 4 ns 50% duty pulse.
Figure 6. (Color online) Microphotograph of switch. The total area is
0.5 0.95 mm2 .
Figure 4. Measured output power versus input power of the SPDT
switch for the Tx mode.
Figure 6 shows a photograph of the proposed SPDT switch.
The total area of the switch is 0.5 0.95 mm2 with the test
pads. The performance comparison of this SPDT switch with
previous ones is listed in Table 1.
The results show that, compared with other recently published SPDT switches, the proposed SPDT switch has better performance in bandwidth and low insertion loss and high
isolation by layout simulation. But the measured results have
some deviation from the simulation, especially after 52 GHz,
this may be caused by the model accuracy of the MOSFET and
the effect of the test pads. To verify this, we test the S parameters of some 15 fingers with a unit finger length of 2 m
RF NMOS from 0.1–67 GHz. As shown in Figures 7 and 8,
the measured S11 and S22 deviate from the model of the RF
NMOS when the frequency is above 20 GHz.
4. Conclusion
A high performance SPDT switch using a novel compensation network in the double shunt topology has been designed
and measured. The proposed compensation method can make
the series-shunt topology switch effective and work in high frequency. The switch can attain the better insertion loss and isolation performance than conventional switches in broadband.
Figure 7. (Color online) S11 and S22 comparison of the RF NMOS in
Smith chart (finger D 15, width D 2 m).
The power handling reaches the 13 dBm at 52 GHz which is
sufficient for most short-range communication systems.
Acknowledgment
The authors would like to thank the Southeast China University for their test support and Lin Xuan from Hangzhou Dianzi University for the measurement help.
References
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J. Semicond. 2016, 37(1)
Parameter
Technology
Frequency (GHz)
Insertion loss (dB)
Isolation (dB)
Input P1dB (dBm)
Size (mm2 )
Topology
Zheng Zonghua et al.
Table 1. Comparison of recently published SPDT switches.
Reference [3]
Reference [4]
Reference [5]
Reference [8]
130 nm
90 nm
65 nm
45 nm SOI
57–66
50–94
60
DC–60
4.5–5.8
3.3
2.8
< 2.5
24.1–26
27
20
> 25
4.1
15
16.3
7.1
0.68 325
0.57 0.42
0.54 0.78
0.18 0.22 Core
Series-shunt
Traveling wave concept Traveling wave concept Series-shunt
This work
90 nm
30–64
<4
> 25
13
0.5 0.95
Series-shunt
Figure 8. (Color online) S11 and S22 comparison of the RF NMOS in real and image (finger D 15, width D 2 m).
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[4] Chao S F, Wang H, Su C Y, et al. A 50 to 94-GHz CMOS SPDT
switch using traveling-wave concept. IEEE Microwave Wireless
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[7] Yeh M C, Tsai Z M, Wang H, et al. Design and analysis for
a miniature CMOS SPDT switch using body-floating technique
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[8] Parlak M, Buckwalter J F. A 2.5-dB insertion loss, DC–60 GHz
CMOS SPDT switch in 45-nm SOI. Compound Semiconductor
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