MOS-Inverter - RIT - Rochester Institute of Technology
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MOS Inverters ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING MOS Inverters Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Email: Lynn.Fuller@rit.edu Department webpage: http://www.microe.rit.edu 4-5-2016 MOS-Inverters.ppt Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 1 MOS Inverters OUTLINE Introduction Voltage Transfer Curve (VTC) Noise Margin Inverter Current vs. Vin PMOS Inverter NMOS Inverter CMOS Inverter Pseudo CMOS References Homework Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 2 MOS Inverters INTRODUCTION There are many ways to make an inverter. In this document we will investigate various MOS inverters, their voltage transfer curve, current, noise margin, speed etc. The inverter is the simplest logic gate to analyze and can give useful results for the comparison of different inverter designs and fabrication technologies. TRUTH TABLE SYMBOL VIN VIN VOUT VOUT 0 1 Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 3 1 0 MOS Inverters INVERTER TYPES - VOUT VS VIN (VTC) +V +V 0 0 +V 0 0 +V 0 +V 0 0 -V 0 VO VIN +V 0 VIN PMOS ENHANCEMENT LOAD Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller +V +V +V VIN CMOS 0 VO VO SWITCH +V -V +V +V VIN -V VO VIN VO NMOS NMOS ENHANCEMENT DEPLETION LOAD LOAD Page 4 MOS Inverters VOLTAGE TRANSFER CURVE NMOS-RESISTOR LOAD VOUT +VDD VOUT VIN Voh Idd +VDD R VOUT VIN Slope = Gain VoL NMOS-M1 VIN RESISTOR LOAD 0 0 Vinv Vih ViL +V NML, noise margin low, D0 =ViL-VoL Rochester Institute of Technology Microelectronic NMH, noiseEngineering margin high, D1 =VoH-ViH © April 5, 2016 Dr. Lynn Fuller Page 5 MOS Inverters CALCULATION OF VTC +VDD VOUT +V R M1 Off VOUT VIN M1 Saturation NMOS-M1 M1 Linear VIN 0 RESISTOR LOAD 0 Vth +V First figure out if the transistor is sub-threshold or off, Vgs < Vth and Vgd < Vth non-saturation, Vgs > Vth and Vgd > Vth saturation region, Vgs > Vth and Vgd < Vth Note:Rochester VinInstitute = Vgs, Vout = Vds, therefore Vgd = Vin-Vout of Technology Microelectronic Engineering Vth might be +1volt © April 5, 2016 Dr. Lynn Fuller Page 6 MOS Inverters CALCULATION OF VTC +VDD VOUT +V R ID M1 Off VOUT VIN M1 Saturation NMOS-M1 M1 Linear VIN 0 RESISTOR LOAD 0 Vth +V Next calculate Vout = VDD – ID R using the correct equation for ID for the transistor depending on region of operation Saturation Linear (Non-Saturation) ID = µW Cox’ (Vg-Vt)2 ID = µW Cox’ (Vg-Vt-Vd/2)Vd 2L L Institute of Technology Rochester Microelectronic Engineering Cox’ = Cox/Area = or/Xox © April 5, 2016 Dr. Lynn Fuller Page 7 MOS Inverters CALCULATION OF VTC M1 in Saturation Vout = VDD – R ID = V - R µW Cox’ (Vin-Vt)2 2L Cox’ = Cox/Area = or/Xox o = 8.85e-14 F/cm r=3.9 for oxide Xox = gate oxide thickness W= width of MOSFET L=Length of MOSFET Vt = Threshold Voltage Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 8 MOS Inverters CALCULATION OF VTC M1 in Non-Saturation Vout = VDD –ID R Vout = VDD –ID R = VDD - R µW Cox’ (Vg-Vt-Vd/2)Vd L Kx Vo = VDD - R Kx(Vin-Vt-Vo/2)Vo Vo = VDD - R Kx(Vin-Vt)Vo- RKxVo2/2 0 = VDD - R Kx(Vin-Vt - 1)Vo- RKxVo2/2 a x2 + bx + c = 0 quadratic formula b2-4ac x = -b +/Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 2a Dr. Lynn Fuller Page 9 MOS Inverters CALCULATION OF VTC M1 in Non-Saturation Vout = b2 +/b=(Vin – Vt + 1/KxR) b2 -2VDD/KxR 2a Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 10 MOS Inverters CALCULATION OF VTC Note: Equations only valid in specific regions Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 11 MOS Inverters LTSPICE – RESISTOR LOAD INVERTER - VTC Vout1 Id Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 12 MOS Inverters CALCULATION OF NOISE MARGINS Approach Take derivative set equal to -1 find VIL and VIH VOH and VOL Find point where Vin = Vout Find I Find Power Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 13 MOS Inverters SPICE CALCULATIONS FOR NOISE MARGINS RL = 1K VIL = 3.31 VIH = 6.95 VOH = 8.09 VOL = 3.37 D0 = VIL – VOL =3.31-3.73= -0.42 D1=VOH-VIH= =8.09-6.95=1.14 1 Max Gain = -1.32 2 Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 14 MOS Inverters SPICE CALCULATIONS FOR NOISE MARGINS RL = 10K 1 VIL = 1.0 VIH = 2.91 VOH = 10.0 VOL = 0.91 D0 = VIL – VOL =1.0-0.91= 0.08 D1=VOH-VIH= =10-2.91=7.09 Max Gain = -7.2 2 Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 15 MOS Inverters LTSPICE - INVERTER VTC – FOR DIFFERENT RL R=1K 5K 10k Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 16 MOS Inverters LTSPICE – INVERTER VTC FOR DIFFERENT W W =10µm 20µm 40µm Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 17 MOS Inverters VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD +V I M1 M1 VO VIN Vt VOUT I + V - +V 1/R Gain = W/L switch W/L load M2 & M1 Saturation M2 Off M2 M2 Linear NMOS ENHANCEMENT LOAD 0 VIN V Vt 0 Vt +V M2 is the switch and M1 is the load. The load limits the current when M2 is on. The load could be a resistor but an NMOS transistor with gate connected to the drain is smaller in size and also limits current. See the I-V characteristics. In the first quadrant the transistor approximates the resistor. However, Vout high is below VDD by the threshold voltage of M1 Cox’ = Cox/Area = or/Xox Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 ID = µW Cox’ (Vg-Vt)2 2L Saturation Dr. Lynn Fuller Page 18 MOS Inverters DERIVATION OF GAIN EXPRESSION +VDD M1 VO VIN M2 Assume Vout = Vin and both transistors are in saturation for the steep part of the VTC. The current in M1 is equal to the current in M2 is equal. Also assume Vt is the same for both transistors. I2 = I1 µW2 Cox’/2L2 (VG-Vt)2 = µW1 Cox’/2L1 (VG-Vt)2 W2 /L2 (VG-Vt)2 = W1/L1 (VG-Vt)2 But, VG2 is VIN and VG1 = VO +Vt (W2 /L2) (VIN-Vt)2 = (W1/L1) (VO +Vt -Vt)2 Gain = d VO/d VIN Gain = Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 W2/L2 W1/L1 Dr. Lynn Fuller Gain = Page 19 W/L switch W/L load MOS Inverters VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD W/L switch Gain = W/L load G=2.2 G=5.5 G=9.5 Note: increasing L of the load is equivalent to increasing R Rochester Institute of Technology Microelectronic Engineering of a resistor load, Vout high is Vdd – VtM1 , Gain is shown. © April 5, 2016 Dr. Lynn Fuller Page 20 MOS Inverters VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD AND V++ GATE BIAS +V V++ M1 VO VIN M2 NMOS ENHANCEMENT LOAD V++ GATE BIAS W/L switch Gain = W/L load M2 is the switch and M1 is the load. The load limits the current when M2 is on. The load could be a resistor but an NMOS transistor is smaller. M1 is always on because the gate voltage is above the supply voltage. (Vgs is always above the threshold voltage. Vout max is the supply voltage. The threshold voltage of M1 depends on source to substrate voltage for M1. Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 21 MOS Inverters VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD AND V++ GATE BIAS W/L switch Gain = W/L load G=2.2 G=5.5 G=9.5 Note: increasing of the load is equivalent to increasing R Rochester Institute of L Technology Microelectronic Engineering of a resistor load, Vout high is Vdd, Gain is shown. © April 5, 2016 Dr. Lynn Fuller Page 22 MOS Inverters VTC NMOS INVERTER – NMOS DEPLETION LOAD +V I I M1 VO VIN Vt + V - W/L switch Gain = W/L load 1/R M2 NMOS DEPLETION LOAD V Vt M2 is the switch and M1 is the load. The load limits the current when M2 is on. In the first quadrant the transistor approximates the resistor. M1 is always on because its threshold voltage is set to zero or slightly negative by ion implant. Note: transistor M1 symbol has solid line between D and S. Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 23 MOS Inverters VTC NMOS INVERTER – NMOS DEPLETION LOAD * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology .MODEL RITSUBN7D NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=-1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) Need a new SPICE model for the Depletion mode NMOS. New model name and negative VTH0. Using ion implant the VTH0 can be made negative. Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 24 MOS Inverters VTC NMOS INVERTER – NMOS DEPLETION LOAD D D W/L switch Gain = W/L load D G=2.2 G=5.5 G=9.5 Note: increasing L of the load is equivalent to increasing R Rochester Institute of Technology Microelectronic Engineering of a resistor load, Vout high is Vdd, Gain is shown. © April 5, 2016 Dr. Lynn Fuller Page 25 MOS Inverters VTC PMOS INVERTER- PMOS ENHANCEMENT LOAD -V I -I M1 VO VIN Vt + V - M2 PMOS ENHANCEMENT LOAD 1/R W/L switch Gain = W/L load -V Vt M2 is the switch and M1 is the load. The load limits the current when M2 is on. The load could be a resistor but a PMOS transistor with gate connected to the drain is smaller in size and also limits current. See the IV characteristics. In the first quadrant the transistor approximates the resistor. However, Vout high is below VDD by the threshold voltage of M1 Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 26 MOS Inverters VTC PMOS INVERTER- PMOS ENHANCEMENT LOAD Note: Supply and input V is negative W/L switch Gain = W/L load Gain = 2 Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 -10 Volts is Logic High 0 Volts is Logic Low Dr. Lynn Fuller Page 27 MOS Inverters GAIN OF 2 INVERTER Vdd Wu= 2l (20 µm) W/L switch Gain = W/L load Lu = 4 l (40 µm) (80 µm) Vout Wd= 4l (40 µm) Vin Ld = 2l (50 µm) Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 (20 µm) Gnd Dr. Lynn Fuller Page 28 MOS Inverters INVERTER LAYOUT L = 40µm W = 20µm L = 20µm W = 50µm W/L switch Gain = = 2.34 W/L load Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 29 MOS Inverters GAIN OF 3 INVERTER TEST RESULTS Theoretical Gain = - 3 Actual Gain = -2.64 W is smaller than drawn because of lateral diffusion ~2u Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 30 MOS Inverters CMOS - CALCULATION OF VTC +V +V VOUT nmos off PMOS nmos & pmos saturation VO VIN nmos sat pmos linear NMOS pmos sat pmos nmos linear off CMOS VIN 0 0 V-Vthp Vthn First figure out if the transistor is sub-threshold or off, Vgs < Vth and Vgd < Vth non-saturation, Vgs > Vth and Vgd > Vth saturation region, Vgs > Vth and Vgd < Vth Note: Vin = Institute Vgs,ofVout = Vds, therefore Vgd = Vin-Vout Rochester Technology Microelectronic Engineering Vth might be +1volt © April 5, 2016 Dr. Lynn Fuller Page 31 +V MOS Inverters CMOS INVERTER VOUT +V VOUT VIN +V Imax Voh Idd Slope = Gain VO VIN Idd VoL CMOS VIN 0 0 +V Vih ViL Vinv Rochester Institute of Technology NML, noise margin low, D0 =ViL-VoL Microelectronic Engineering NMH, noise margin high, D1 =VoH-ViH © April 5, 2016 Dr. Lynn Fuller Page 32 MOS Inverters LTSPICE – CMOS INVERTER NML,Rochester noise margin low, D0 =ViL-VoL = 2.2-0.5 = 1.7 Institute of Technology NMH,Microelectronic noise Engineering margin high, D1 =VoH-ViH = 4.5-2.5 = 2.0 © April 5, 2016 Dr. Lynn Fuller Page 33 MOS Inverters COMPARISON OF 10u, 1u AND 100n CMOS INVERTERS VDD = 5 volts VDD = 3.3 volts Imax=5.4mA Imax=100uA VDD = 2.5 volts Imax=21uA Gain=-90 Gain=-33 Gain=-6 RITALDN3/RITALDP3 L=10u W=880u L=10u W=880u RITSUBN7/RITSUBP7 Ln=1u Wn=2u Lp=1u Wp=2u EECMOSN/EECMOSP Ln=180n Wp=200n Ln=180n Wp=200n Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 34 MOS Inverters PSEUDO – CMOS There are situations where we want a large number of inputs. Rather than have CMOS where there will be many transistors in series (which will not work) we can use a single PMOS/NMOS transistor that is always on. +V +V Idd Idd VIN CMOS VA Pseudo CMOS Inverter Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Idd VO VO VO VIN +V Dr. Lynn Fuller VB VC Pseudo CMOS 4 Input NOR Page 35 VD MOS Inverters PSEUDO – CMOS INVERTER Gain = W/L switch = W/L load 2/2 = 2.2 2/10 Rochester Institute of Technology Microelectronic Engineering No advantages over CMOS inverter D0=1.0 , D1=3.0 © April 5, 2016 Dr. Lynn Fuller Page 36 MOS Inverters PSEUDO – CMOS NOR Gain = W/L switch = W/L load 8/2 =4 2/8 Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Note: noise margin ~ D0=1.3 , D1=2.8 max current drive 50uA static current not zero for Vout=low gate delay ? Dr. Lynn Fuller Page 37 MOS Inverters CMOS NOR-4 Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Note: noise margin ~ D0=1.2 , D1=3.2 max current drive 50uA static current is zero gate delay ? Dr. Lynn Fuller Page 38 MOS Inverters PSEUDO CMOS NAND Gain = W/L switch = W/L load 6/2 = 3 2/6 Sweep M7, M2 and M6 together Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 39 MOS Inverters PSEUDO CMOS NAND 2/2= 1.7 Gain = W/L switch = W/L load 2/6 Sweep M7 only, M2 and M6 off Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 40 MOS Inverters PSEUDO CMOS NAND 6/2= 1.7 Gain = W/L switch = W/L load 2/2 Sweep M7, M2 and M6 together Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 41 MOS Inverters PSEUDO CMOS NAND 2/2= 1.0 Gain = W/L switch = W/L load 2/2 Sweep M7 only, M2 and M6 off Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Does not work L of M1 needs to be larger (Gain too low) Dr. Lynn Fuller Page 42 MOS Inverters PSEUDO CMOS NAND 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 This is how to check truth table Rochester Institute of Technology Microelectronic Engineering Gain = 5.5 © April 5, 2016 Dr. Lynn Fuller Page 43 MOS Inverters REFERNCES 1. Hodges Jackson and Saleh, Analysis and Design of Digital Integrated Circuits, Chapter 4. 2. Sedra and Smith, Microelectronic Circuits, Sixth Edition, Chapter 13. 3. Dr. Fuller’s Lecture Notes, http://people.rit.edu/lffeee Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 44 MOS Inverters HOMEWORK – MOS INVERTERS 1. Using SPICE obtain the VTC for a CMOS inverter with gate lengths of ~1um. Let the width of both transistors be 2um Determine the noise margins. Determine the maximum current and voltage gain. (Use the SPICE models given below) Make appropriate assumptions. 2. Repeat problem 1 for gate L and W of ~200nm. 3. Given the layout shown below of a CMOS inverter find L, W, AD, AS, PD, PS. 4. The schematic below is for a tristate inverter. This device should be able to make the output high or low when the enable (EN) is high. When the enable is low the inverter is effectively disconnected from the load (high impedance, Z). Use SPICE to show that this circuit operates as intended. Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 45 MOS Inverters INVERTER LAYOUT Vout Vin +V Idd PMOS Vout Vin NMOS CMOS TRUTH TABLE VIN 0 1 W = 40 µm Lpoly = 2.0µm VOUT 1 0 Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 46 MOS Inverters HOMEWORK – MOS INVERTERS +V EN VIN EN VIN 0 0 1 1 0 1 0 1 VO High Z High Z 1 0 VO EN C Tristate Inverter Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 47 MOS Inverters SPICE MODELS FOR CD4007 MOSFETS *SPICE MODELS FOR RIT DEVICES - DR. LYNN FULLER 8-7-2015 *LOCATION DR.FULLER'S WEBPAGE - http://people.rit.edu/lffeee/CMOS.htm * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1 .MODEL RIT4007N7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54 NRD=0.54 .MODEL RIT4007P7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8 +VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94 Rochester Institute of Technology +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 pCLM=5 Microelectronic Engineering +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) © April 5, 2016 Dr. Lynn Fuller Page 48 MOS Inverters SPICE MODELS FOR MOSFETS * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology .MODEL RITSUBN7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology .MODEL RITSUBP7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 +VTH0=-1.0 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 49 MOS Inverters SPICE MODELS FOR MOSFETS *4-4-2013 LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology .model EECMOSN NMOS (LEVEL=8 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *4-4-2013 LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology .model EECMOSP PMOS (LEVEL=8 +TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) * Rochester Institute of Technology Microelectronic Engineering © April 5, 2016 Dr. Lynn Fuller Page 50
