IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 6, JUNE 2009
675
p-Channel Ge MOSFET by Selectively
Heteroepitaxially Grown Ge on Si
Hyun-Yong Yu, Masato Ishibashi, Jin-Hong Park, Masaharu Kobayashi, and Krishna C. Saraswat, Fellow, IEEE
Abstract—We successfully demonstrate Ge pMOSFET integrated on Si. In this process, Ge is grown selectively on Si on
patterned SiO2 by heteroepitaxy, and pMOSFET is fabricated
with gate dielectric stack consisting of thin GeO2 and Al2 O3
and Al metal gate electrode. Fabricated devices show ∼80%
enhancement over the Si universal hole mobility. These results are
promising toward monolithically integrating Ge MOSFETs with
Si CMOS VLSI platform.
Index Terms—Anneal, dislocation, germanium, heteroepitaxy,
hydrogen, MOSFET, selective growth.
I. I NTRODUCTION
A
S SILICON CMOS devices approach their fundamental
scaling limit, diverse research is being done to introduce
novel structures and high-carrier-mobility materials such as Ge
to devices in order to overcome this limit [1]–[3]. Monolithic
integration of Ge with Si devices could provide alternative
solutions for system-on-chip applications [4]. Moreover, highperformance short-channel Ge devices are demonstrated [5]–
[8]. In order to integrate Ge devices with Si CMOS for highperformance applications, it is critical to develop new methods
for heteroepitaxial Ge growth technology. This is not straightforward due to a large lattice mismatch between Ge and Si. As a
result, several heteroepitaxial techniques have been introduced
to grow Ge on Si, and a high-quality Ge layer has been obtained.
For example, employing superlattice buffer layers to grow Ge
layers effectively reduces the large lattice mismatch between Si
and Ge [9]. Cyclic thermal annealing and hydrogen annealing
are other methods of heteroepitaxial growth [10], [11]. Also,
the molecular beam epitaxy method is yet another instance of
Ge growth on Si, which creates thin strain-relaxed buffers on
silicon substrates [12]. Also, the heteroepitaxy necking method
by selective growth of Ge in SiO2 trenches on Si has been
thoroughly studied [13], [14]. These high-quality Ge layers on
Si can be used to fabricate germanium-on-insulator (GOI) substrates, and very good transport properties for GOI p-MOSFETs
have already been reported [4]–[6].
Manuscript received February 23, 2009; revised March 22, 2009. Current
version published May 27, 2009. This work was supported in part by MARCO
Interconnect Focus Centers and in part by the Stanford University INMP
program. The review of this letter was arranged by Editor M. Ostling.
H.-Y. Yu, J.-H. Park, M. Kobayashi, and K. C. Saraswat are with the Department of Electrical Engineering, Stanford University, Stanford, CA 94305 USA
(e-mail: yuhykr@stanford.edu; jhpark9@stanford.edu; masaharu@stanford.
edu; saraswat@cis.stanford.edu).
M. Ishibashi is with the Center for Integrated Systems, Stanford University,
Stanford, CA 94305 USA and also with Renesas Technology Corporation,
Hyogo 664-0005, Japan (e-mail: ishibashi.masato@renesas.com).
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2009.2019847
Fig. 1. (a) Cross-sectional TEM image of ∼500-nm selectively grown
heteroepitaxial Ge layer on Si by the MHAH method. (b) Cross-sectional
schematic of selectively grown Ge layer on Si at the small window size.
Recently, we have developed the selective epitaxial Ge
growth method using the selective multiple hydrogen annealing for heteroepitaxy (MHAH) technique to grow high-quality
single-crystal Ge on Si. The selective MHAH technique naturally provides a device isolation structure. In this letter, we
demonstrate Ge pMOSFETs by selectively growing Ge through
patterned SiO2 on Si, a promising approach for the monolithic
integration of Ge with Si CMOS VLSI platform.
II. S ELECTIVE H ETEROEPITAXIAL G ROWTH
We begin the process with lightly doped n-type (100) bulk
silicon wafers. A 500-nm-thick SiO2 film was thermally grown
on the Si substrate at 1100 ◦ C and was then patterned by
dry etching, followed by wet etching to define the desired
locations for Ge growth. Ge epitaxial layers were selectively
grown directly on Si through the patterned SiO2 windows.
For obtaining light n-type doping, arsine was used during the
deposition process. The initial arsenic-doped Ge layer was
grown at 400 ◦ C at 8 Pa, yielding a 400-nm-thick film. This
was followed by annealing for 30 min at 825 ◦ C in H2 ambient.
The growth temperature was then decreased to 600 ◦ C, and Ge
growth was continued for the formation of 1-μm-thick in situ
arsenic-doped Ge layer, followed by another 825 ◦ C hydrogen
annealing.
The root-mean-square roughness of the resulting film was
determined to be ∼0.8 nm by atomic force microscopy scans
by 10 × 10 μm2 area. Due to the multistep Ge growth and hydrogen annealing, the grown layer showed low defect density,
having a threading dislocation density count of ∼1 × 107 cm−2
based on the plan-view TEM. A lower defect density can also
be achieved at the smaller window size because dislocations
glide during annealing, and they are trapped (311) facet surface
near SiO2 , which is generally away from the device fabrication
region, as shown in Fig. 1 [13], [14].
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IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 6, JUNE 2009
Fig. 2. (a) Four-point probe measurement of boron-implanted Ge after FGA annealing, showing the reduction in sheet resistance. (b) Junction current density of
the P + /N junction after 400 ◦ C annealing for 30 min.
III. D EVICE F ABRICATION
pMOSFETs using GeO2 and Al2 O3 as the dielectric and aluminum(Al) as the gate electrode were fabricated. The selective
epitaxial Ge layer was in situ doped with As during the deposition step, resulting in an n-type Ge substrate having a doping
density of 3 × 1016 /cm3 . The surface of Ge was oxidized at
400 ◦ C for 90 s in a TEL Trias SPA Plasma Processing System
using oxygen radicals to obtain a GeO2 passivation layer, and
then, a 4.5-nm Al2 O3 high-k gate dielectric was deposited by
atomic layer deposition at 350 ◦ C using Al(CH3 )3 and O3 .
The dielectric substrate interface Dit from Al/Al2 O3 /GeO2
on the epitaxial Ge layer was ∼ 3.5 × 1011 cm−2 eV−1 , which
is similar to the Dit value of the same gate stack on bulk Ge
[15]. Al was deposited as a gate electrode. After gate definition,
boron (BF2) was implanted to form self-aligned source/drain.
The dopants were activated by forming gas annealing (FGA) at
400 ◦ C for 30 min. After annealing, the contact windows were
opened, and Ti/Al ohmic contacts were deposited and patterned
by the liftoff process. The fabricated devices have a ring-type
structure with 15 μm of gate length.
IV. R ESULT AND D ISCUSSION
In Fig. 2(a), four-point probe measurements show a huge
reduction in sheet resistance after FGA annealing at and beyond
380 ◦ C. Annealing at temperature above 400 ◦ C does not show
significant changes in sheet resistance. Annealing temperatures
as low as sub-400 ◦ C have been reported in fabrication of
Ge MOSFETs [16], [17]. As shown in Fig. 2(b), with a postimplant anneal at 400 ◦ C for 30 min, the p + /n-junction diodes
on the selectively grown Ge substrate have a low leakage
current density of 10−4 A/cm2 with high Ion /Ioff ratio, which
is considered acceptable for device operation.
Fig. 3(a) and (b) shows the measured ID /IS −VG and ID –VD
characteristics, respectively, of the Ge pMOSFETs with W/L
ratio of 200 μm/15 μm. The gate leakage current is shown to
be as low as ∼ 10−9 A/cm2 . This gate leakage is negligibly
small compared to the drain or source current. Because offcurrent minimization and the maximization of Ion /Ioff ratio
are among the challenging issues concerning Ge and GeOI
pMOSFETs, the Ion /Ioff measurement is performed and shown
in Fig. 3. In Fig. 3(a), the Ge pMOSFET provides a reasonable
Fig. 3. (a) Measured ID /IS −VG characteristics at −1.1-V drain bias and
(b) measured ID –VD characteristics for Ge pMOSFET with LG = 15 μm.
Ion /Ioff ratio of 6.3 × 103 at −1.1-V drain voltage and shows
the off-current density of 2 × 10−4 μA/μm with 15-μm gate
length. In addition, it exhibits a high Ion (1.39 μA/μm at −3-V
gate voltage) in the drain current measurement. The difference
between source and drain currents at low gate voltage is due to
the junction leakage current of drain and substrate.
To determine the effective mobility (μeff ), the drain current
(ID ) and inversion charge (Qn ) equation was employed for
μeff = ID /(W/L)VDS Qn [18]. ID as a function of gate bias
(VG ) was measured at a drain–source voltage of −50 mV. Split
C–V measurements were carried out at 100 kHz using a ramp
rate of 50 mV/s to measure the inversion charge in the channel,
for Qn = Cinv dVg . In Fig. 4, effective mobility versus effective
E-field is extracted from the 15-μm-gate-length pMOSFET.
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YU et al.: p-CHANNEL Ge MOSFET BY SELECTIVELY HETEROEPITAXIALLY GROWN Ge ON Si
Fig. 4. Effective hole mobility as a function of effective field measured from
Ge pMOSFETs and Si universal hole mobility.
For comparison, the Si universal hole mobility is also shown.
Ge pMOSFETs show ∼80% mobility enhancement over the
Si universal hole mobility. A peak mobility of 391 cm2 /V · s
at 0.051 MV/cm was observed, as shown in Fig. 4. To the
best of our knowledge, this is one of the highest mobilities
reported on unstrained-channel Ge pMOSFETs [16], [17],
[19]–[22]. A similar peak hole mobility of ∼400 cm2 /V · s
has been recently reported for Ge pMOSFET using thermally
oxidized GeO2 interfacial layers [22]. Our results also outperform the data of p-MOSFETs on MHAH-grown Ge layer on
Si with GeOx Ny gate dielectrics [20]. However, short-channel
p-MOSFETs show relatively low mobility due to the substrate
doping to control the short-channel effect [5]–[8]. This high
effective mobility indicates the high quality of the Ge layer on
Si by the selective MHAH technique.
V. C ONCLUSION
We have successfully demonstrated high-mobility Ge pMOSFETs with high-k dielectric and metal gate by selectively
growing Ge through patterned SiO2 on Si using the selective
MHAH technique, which allow a high-quality Ge layer on Si.
The hole mobility is enhanced by ∼80% compared to the Si
hole universal mobility.
ACKNOWLEDGMENT
This work was performed at the Stanford Nanofabrication
Facility.
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