Mixed-Signal Design
Choosing RF CMOS or SiGe BiCMOS in
mixed-signal design
Deciding what technology to choose for fast-moving targets is not trivial,
especially in the commercial space where the price, time to market, and the
performance of the chip can make or break a product, and sometimes the
company. This article attempts to analyze these issues from the perspective
of a fabless design house. It discusses key issues that need to be considered
when deciding what technology to choose for mixed-signal or wireless systemon-a-chip design. The article reviews the basic performance criteria and
characteristics in an easy to understand language, and describes how they
affect the performance of chips.
By Adam H. Pawlikiewicz and David Hess
O
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Frequency (GHz)
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Maximum Application
ver the last decade, the advances in silicon-germanium (SiGe)
BiCMOS technology has been phenomenal. From its humble
beginning in the late 1980s when it was looked at as nothing more
than a scientific excercise at a few research labs, namely at IBM
in the United States and Temic in Europe, to today where it is on
the road map of every major semiconductor company. Present-day
SiGe BiCMOS processes integrate high-performance heterojunction
bipolar transistors (HBTs) with state-of-the-art CMOS technology.
With each generation of the technology, the feature size leads to
higher speeds and lower power consumption. One of the most quoted
figure of merit (FoM) is the cut-off frequency - f T of the HBT that
increased from roughly 47 GHz in the 0.5 µm generation BiCMOS
process to unheard of 210 GHz in the 0.13 µm process.
Usually, the natural progression at the semiconductor companies
was to develop a CMOS process first and then add more complex
HBT devices that would give the needed performance for the RF
applications. That combination was good when the feature sizes of
0.35 µm would give a speed of ~25 GHz on the NMOS device but
around 50 GHz from the HBT device. However, with a decrease in
the feature size, CMOS device speed improved enormously, as well.
For instance, FoM f T increases to more than 60 GHz at 0.18 µm
feature size. With such an improvement in NMOS speeds the possibility
of designing not only the logic but also the analog blocks of the RF
circuits became quite obvious. The majority of today’s applications
could be covered with such devices. Moreover, further advances in
the logic processes with the CMOS scaling pushes the mixed-signal
designers toward these newer CMOS-only processes that provide the
minimum speed for the application in mind.
However, the speed of the device is not the only FoM the designer
has to deal with. Other specs that are as important if not more are
maximum frequency of oscillation (fT and fmax) device transconductance
(gm), output conductance (go) matching, and 1/f noise and NF characteristics. Dynamic range is also important, along with other economic
issues such as time to market, system specs and cost.
In subsequent paragraphs, we shall address these aspects from the
designer’s point of view. Hopefully, that discussion will help the decision makers select the optimal process for the intended application.
In the process, we shall look at the quantifiable variables such as the
specs of the RF CMOS with high-quality passive devices compared
to SiGe BiCMOS processes that are uniquely fit for the high-speed
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SiGe BiCMOS
RF CMOS
3
0
500
350 250 180 130
Geometry Size (nm)
90
Figure 1. Maximum application frequency for CMOS and SiGe BiCMOS by
transistor size (fT/8).
applications. The discussion shall be centered on the high-performance
SiGe BiCMOS technologies compared to the advanced CMOS technologies. It is implicitly assumed that in both cases the same number
of high-quality passive elements are available. If that assumption is
not met, it is not the active device performance but the quality of the
passive component that might dictate the choice of the technology, since
for mixed signal, or SoC designs, they are extremely important.
Technical considerations
In today’s environment the choice comes down to either bipolar
transistor (in BiCMOS) vs. the field effect transistor (FET) in CMOS.
Moreover, since the invention of SiGe HBT, and the exponential
growth in their applications, the BiCMOS process providers are almost
exclusively concentrated on the SiGe BiCMOS rather than plain
Si BiCMOS technologies of the past. One can start the process by
comparing the electrical specs of the FET CMOS against the bipolar
available in the BiCMOS process.
Historically, the shrinking of plain vanilla CMOS processes was
motivated by increasing chip complexity and pricing pressures. These
forces made the foundry providers shrink the device size, increase
the yield and build circuits on larger wafers. With the maturity of the
given logic process, and the need for even further scaling to satisfy
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March 2006
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130
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Masking Layers
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180n
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(k$)
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500n
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1991
1995
1999
2003
the market for the logic and memory products, came a realization that
the older technologies can still be useful for the mixed and analog
applications. Thus, came the addtional bipolar modules with highquality passives, that extended the useful life of the technology
for analog, mixed-signal applications.
In those instances, the bipolar transistors gave the speed required
for the mixed and wireless applications, the passives allowed for the
SoC integration and the CMOS covered the logic requirements of the
chip. Thus, for the first 0.35 µm SiGe BiCMOS process developed
at Atmel, the Ft of the HBT device exceeded 45 GHz as compared to
the Ft of the 0.35 µm NMOS, which was barely more than 20 GHz.
However, with the further shrinking of the analog CMOS process to
0.18 µm, we can deliver the speed at 60 GHz, quite comparable with the
speed (70 GHz) of the newer HBTs built on the 0.35 µm process.
Such an increase in the speed of the CMOS transistor made it
possible to replace the bipolar device and to design the entire analog
and digital parts on the CMOS process alone.
These two contenders are usually spaced by a two-generational gap,
i.e., 0.18 µm RF CMOS vs. 0.35 µm BiCMOS, (or 0.13 µm RF CMOS
vs. 0.25 µm SiGe BiCMOS) one has to compare the characteristics of
the 0.35 µm HBT transistor to 0.18 µm RF CMOS device.
BJT vs. FET
A better way to judge a given device as an amplifier is to look at
its internal self gain defined as the ratio of transconductance over
the output conductance (gm/go). Transconductance is an ability of
the device to source the current and the output conductance tells us
how well that current is sourced with swings in the output voltage.
Due to the exponential relationship between the output current in
response to the input voltage of the bipolar device, its transconductance
is much better than that of an FET where the relationship is only
quadratic. Ultimately, the transconductance (g m) of the bipolar
transistor is proportional to the Ic current of the device.
gm (BJT) = q * IC/kT
(1)
whereas the transconductance of the FET is proportional only as the
square root of its drain current,
gm (FET) = Const * SQRT (ID)
(2)
Roughly at its peak operating current the BJT achieves about three
times the transconductance, and thus three times the drive capability
of an FET.
Output (Ic vs. Vce or Id vs. Vds) characteritics of the device dictate the output conductance gO. The flatter the current with the output
voltage the higher the output resistance and the smaller the output
conductance Ro = 1/go. SiGe BiCMOS processes offer quite a few
knobs for the device designer to improve that characteristic as well.
Ge concentration and then the varying concentration of that modify
the electric field across the base and thus the carrier concentration
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Sige/BiCMOS
CMOS
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2007
Figure 2. Mask cost trends by CMOS transistor node.
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350
300 250 200
Geometry (nm)
150
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Figure 3. At a given node, CMOS typically requires less masking steps
than SiGe/BiCMOS. This generally results in lower wafer costs and
faster manufacturing cycle times. However, the number of masking steps
increases with CMOS scaling and, given the masking cost increase per
node, the cost advantage offered by CMOS begins to erode as geometries
decrease.
that improves the early voltage (flatness of the output characteristics
of the device).
CMOS devices with gate length 2 generation smaller than the
HBT’s leads to higher transconductance and thus speed. However,
for analog applications, FET devices need to be modified through
addtional processing steps to increase the breakdown voltage (eg.,
dual oxide technology), as well as additional implants to fight the
short channel effects (e.g., halo implants and to control punch through).
Ultimately, some of these steps lead to lower gm/go ratio than otherwise
could be possible.
Nevertheless, as far as the internal self gain is concerned, the bipolar
transistor always wins when biased at the same current level as FET,
due to its superior transconductance over the FET.
FT and Fmax figures of merit
The most quoted FoMs between different processes is the cut-off
frequency (fT) and the maximum frequency of oscillation (fmax)
With each process shrinks, the lateral and vertical scaling led to lower
parasitics and thus to faster speeds for the CMOS and BiCMOS devices.
Furthermore, SiGe BiCMOS offered additional knobs in modification
of the doping SiGe base layer, that led to the increase in the electric
field. That combined with the reduction in the graded base width,
as well as the addition of carbon to decrease Boron out-diffusion,
improved the base transit time—further increasing the device speed.
Subsequent reduction in the epi layer thickness led to the decrease in
the collector transit time—and thus an increase in fT. The relationship
between the device speed – fT and the device transconductance can
be described as
fT = gm/(2π ∗ (CBEdepletion+ CBEdiffusion + CBC))
(3)
for the bipolar device and
fT = gm/(2π (CBS+ CGD))
(4)
in the FET case.
All of these advances resulted in the overall reduction of
the parasitics of the bipolar transistor, especially in the base, collector
and emitter resistances (RB, RC, RE) and total collector-base capacitance (CCB). Coupled with the increased fT, this reduction in parasitics
is expected to lead to an increased fmax (maximum frequency of
oscillation), since the relationship between these two figures of
merit is described by the following equation.
fT = 1/2π * 1/(RE CBE+ RE CBC + τBase + τCol)
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15%
Normalized die area
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38%
8
60%
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Starting
node
2 node
decrease
Area digital (80%)
Area analog (20%)
Starting
node
2 node
decrease
Area digital (50%)
Area analog (50%)
Starting
node
2 node
decrease
Area digital (20%)
Area analog (80%)
Figure 4. Die area reduction achieved for a two-node CMOS geometry shrink for various percent mix of analog and digital in an SoC design.
fmax = SQRT (fT /(8π* CCB RB))
(5)
Conversely, with each shrink in the critical dimensions (Leff) the
field effect device gains current sourcing capability (~Weff/Leff) and
then with its transconductance (gm) the speed (fT). CMOS devices
have a similar relationship, between fT and fmax, but this time the
base/collector capacitance is replaced by the gate/source capacitance
and the base resistance is replaced by the source resistance.
fmax = fT/2*SQRT ((Ri+Rg+Rs)Gds +2π fTRGCGD))
(6)
Properly optimized transistor, of either kind, can deliver higher frequency of oscillation - fmax than the maximum cut-off frequency fT.
In many circuits, this is a more important consideration than the
actual fT, which does not take into account the need to push and pull
currents in the circuits through the loads.
Matching using HBTs and FETs
Matching is one of the most important FoM in the analog world.
In the case of the bipolar devices, the matching of Vbes is determined
by the doping profiles of the p/n junctions across the emitter/base.
With each technology improvement, these doping levels are increasing
and, therefore, the matching improves as well.
On the other hand, in the CMOS devices, the equivalent is Vt
matching. That parameter depends more on lateral dimensions of the
devices, such as L and W of the gate, as well as the doping levels in the
active device. These are much less stable from device to device and,
therefore, the matching of the bipolar devices is superior as compared
to the CMOS devices.
That limitation eliminates the application of CMOS-only technologies in high-precision applications such as ADC and DAC converters. However, for the majority, applications where one can live with
poorer matching of the CMOS devices the circuits designed in
CMOS-only technologies sanction quite alright albeit, with much
worse performance.
Noise and NF considerations
The discussion on noise should be divided between low-frequency
noise (1/f or flicker noise) and the high-frequency noise wherein a
different type of the FoM is needed, such as NF.
Let us start with the 1/f noise. That one is especially important in
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applications such as LNAs and VCOs where the low-frequency noise
is visible at the high frequency due to the mixing. Mixing or subsequent signal processing can shift the low-frequency noise spectrum to
the center of the carrier frequency, potentially causing jitter, as well
as interfering with adjacent channels, and lowering the final signal
to noise ratio (SNR).
Bipolar and FET devices have distinctively different areas where
the noise generators are located. In bipolar transistors, the 1/f noise is
mostly generated in the emitter/base junction. FETs on the other hand
are surface conduction devices where the current flow is affected by the
properties of the Si/SiO2 interface. The quality of the p/n junction and
the quality of the oxide interface dictate the power of the 1/f noise.
Present-day HBT devices have a clean Si/SiGe interface and their
noise properties are significantly better than the 1/f noise generated in
the CMOS devices. Moreover, generation-to-generation scaling in FETs
moves oxide interfaces even closer to the active channel, resulting in
worsening of 1/f noise performance.
When looking at high-frequency noise, another FoM is used, namely
NF. That quantity compares the SNR at the output of the amplifier to the
same at the input of the device. It gives us the ability of the amplifier
to amplify the signal without adding any noise to it. NF depends on the
intrinsic properties of the device, namely emitter resistance—RE, base
resistance - RB, internal capacitances and transconductance gm.Although
complicated, the relationship is such that the lower the parasitics (RE,
RB, CCB) and the higher the transconductance the lower the NF.
The SiGe bipolar device features several intrinsic properties that
make it particularly attractive for low-noise circuits. First of all, the
addition of Ge made it possible to heavily dope the base of the device
without the increased hole injection into the emitter. Heavier doping
decreases the base resistance and, therefore, lowers the thermal noise
of the base. That leads to heavier doped in-situ doped poly emitters,
which also allows for heavier doping that leads to lower RE.
A second source of high-frequency noise in the BJT devices is the
shot noise generated by the carriers crossing the p/n junctions. The
shot noise in the base depends on the magnitude of the base current
(IB) injected into the emitter. Due to the beneficial aspects of the
heterojunction, the injection of holes from the base into the emitter
is significantly reduced for a given IC current. That minimizes the
noise contribution when measuring the S/N ratio on the device input.
Furthermore, the high amplification capability of the bipolar devices
with even better performance of the HBTs contribute to high power
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gain at typical frequencies of interest. This
high gain allows an input signal to be amplified to much larger levels before the addition
of thermal and shot noises, therefore, reducing
the impact of these noises on the output SNR
and thus improving the NF.
CMOS devices also exhibit improvement
in NF with shrinking due to the same effects. Lower effective gate lengths increase
the device transconductance and, therefore,
its amplification ability. Moreover, heavier
doping of the source and drain regions improve
the RS and RD parasitics that degrades the SNR.
Ultimately, though, the SiGe HBT device most
likely will give a better performance in that
aspect as well.
Another form of noise, often discussed
but somewhat misunderstood, stems from the
noise entering the active devices by picking the
stray signals traveling through the substrate.
These signals are generated somewhere else
on the chip by fast digital gates or the output
power stage of the analog stage or anywhere
else where the drains and the collectors of
the transistors are capacitively coupled to the
substrate. Noise of that type should be shielded
by the addition of the isolation structures, such
as trenches, doped poly layers, N+ buried
layers and reversely biased junctions. One
needs to investigate if the processes under
consideration have these additional layers
available for isolation of sensitive parts of
the circuits.
Other technical considerations
The holy grail of integration is to have a
whole set of different chips integrated into
one. Having a high-performance BiCMOS
technology enables a designer to create a wide
variety of circuit types integrated together
on the same chip to form a complete system.
Usually, the CMOS devices are used for
integrating digital logic functions with highspeed bipolar analog circuits. This allows fully
integrated system-on-a-chip products, with
the CMOS performing the lower-frequency
baseband signal processing.
With CMOS-only processes the analog
functions need to be done with the FET transistors. As discussed, that is more difficult due to
gain, matching and noise. However, in a few
instances such as ADCs, they are ideal, since
CMOS devices draw no current, a prerequisite
for not disturbing the input signal.
ESD protection is an important factor in
chosing what technology to use for wireless,
mixed-signal applications. The BiCMOS process is more complex and, therefore, offers a
few layers more that could be tapped as the
diodes for the ESD protection. CMOS-only
processes have less of those to use but a clever
designer can compensate the lack of the layers
with a better ESD layout for circuit protection.
Economic considerations
There have been significant strides made in
CMOS and BiCMOS process scaling. CMOS
gate lengths have shrunk, gate oxide thickness
has decreased, and power supply voltages have
dropped. These improvements have provided
increased die density, faster transistors and
lower power consumption. However, scaled
CMOS in analog circuits does not provide as
obvious a benefit because the passive components that do not scale. Scaled CMOS does,
however, provide a speed advantage. A general
guideline for matching the technology speed
to the system speed (application frequency)
requirement is to choose a technology with
an Ft eight to 10 times greater that the system
operating frequency. Figure 1 displays fT as a
function of transistor size. SiGe-BiCMOS has
a speed advantage over CMOS at every node
but when CMOS is scaled by two generations,
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March 2006
its speed is almost equivalent.
Though the cost of CMOS scaling can be
significant at node introduction, these costs
quickly decrease as the node matures. A
part of this price significance can be attributed
to mask costs. Figure 2 is a linear plot of
mask costs for various CMOS nodes, and
the projected cost decrease for each node
from node introduction to 2006. The figure
also shows that, even at maturity, mask
costs remain elevated as compared to the
prior nodes.
At a given node, CMOS typically requires
less masking steps than the SiGe/BiCMOS as
shown in Figure 3. This generally results in
lower wafer costs and faster manufacturing
cycle times. However, the number of masking
steps increases with CMOS scaling and, given
the masking cost increase per node, the cost
advantage offered by CMOS begins to erode
as geometries decrease.
Additionally, CMOS scaling may not
proportionally scale with the die. Though the
die in a digital CMOS design will shrink by
about 50% at each node, die shrink in a mixedsignal SoC due to CMOS scaling depends
greatly upon the percent analog-to-digital mix
and how much of the analog area is dominated
by passive components. Passive components
largely consist of inductors, capacitors and
resistors. The relationship between inductance, and the radius and number of turns, of
an on-chip inductor is
.
Given this relationship, the inductor design
is not dependent upon the factors involved
in CMOS scaling. Likewise, capacitors and
resistors are area-dependent components.
Therefore, the benefit of scaled CMOS in the
analog portion of the die depends upon how
much of the analog area is dominated by the
passive components. The net affect of CMOS
scaling on die size for a mixed signal design,
as a percentage of digital and analog circuits,
can be approximated by assuming the digital
portion of the die area of a mixed signal design
shrinks by x% for each node, (In this example,
x = 50) and assuming the shrink of the analog
area is passive component limited. The impact
on die size using these assumptions is shown
in Figure 4. As shown, while some mixedsignal system designs will show little benefit
from CMOS scaling, those systems with large
digital areas will benefit the most.
Conclusion
CMOS and SiGe/BiCMOS technologies are both used in mixed-signal designs.
BiCMOS has been used when the system
design requires high-performance analog and
does not require high density logic. BiCMOS
technology offers advantages of high speed
combined with high drive capability and
low noise. CMOS has appeared in mixedsignal system designs requiring high density
logic with smaller analog sections. CMOS has
advantages of low power, low wafer cost at a
comparable node, and short fab cycle times.
While the ultimate selection will be based on
system specifications, the noted differences
between performance and economics also
need to be considered. RFD
ABOUT THE AUTHORS
Adam H. Pawlikiewicz is a manager of
the BiCMOS technology development
group at Atmel Corp., Colorado Springs,
Colo. He can be reached at apawlik@cso.
atmel.com.
David Hess is a marketing manager at
Atmel Corp., Colorado Springs, Colo.
He can be reached at dhess@cso.atmel.
com.
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