Faculty Name
A.R. ASWATH
Designation
Professor & Head
Educational Qualification
Experience in Years
Area of Interest
Email Id
M.Tech, M.S., Ph.D, LMISTE,
MIE, MIEEE
21
VLSI and Embedded System
aswath.ar@gmail.com
International Journal:
1. “CNTFET Modeling and Performance Analysis of Device Characteristics”,
International Journal for Scientific Research & Development, ISSN: 2321-0613. Vol.2,
Issue 11, pp.84-87, 2015.
2. A. R. Aswatha, Dr. T. Basavaraju and S. Sandeep kumar, “Fast and Efficient OnChip Interconnection Modeling for High Speed VLSI Systems”, International Journal
of Electronics, Circuits and Systems, Vol. 2, No. 3, pp 140-143, 2008.
3. A. R. Aswatha, Dr. T. Basavaraju
and
N. Bhaskara Rao,
“Optimal
Processors based on Effective Communication Loads, International Journal
Electronics, Circuits and Systems, Vol. 2, No. 3, pp 127-131, 2008.
4. A. R. Aswatha, Dr. T. Basavaraju “Optimum Buffer Insertion in RLC Global
Interconnects for Minimum Propagation Delay” Internal Journal of computational
science, Vol.3, No.3, pp 325- 334, 2009.
5. A. R. Aswatha, M. Puttaraju, A. B. Kalpana, an Implementation of Integral L o w
Power Techniques for Modern Cell-Based VLSI Designs International Journal of
Computer and Electrical Engineering (IJCEE) Vol.3. No.3, pp 394-397, June 2011.
6. A. R. Aswatha, P. Rajeshwari and R. Ramesh, “An approach to design Flash
Analog Digital Converter for High speed and Low Power Applications,”
International Journal of VLSI design & Communication systems (VLSICS) Vol.3.
No.2, pp.125- 131, April 2012.
7. A. R. Aswatha Satish Shet K, “An ARM based Implementation of Adaptive DCT
Based Steganography,” International Science Press IJOSHRM, VOL.2 No.1-2.2012,
pp.59-68.
8. A. R. Aswatha, Sonia C.V, SAALTm: An Android Application to Locate and Track
Mobile Phones” International Journal of Engineering Trends and Technology
(IJETI), Vol.4, Issue.5, pp.1864-1868, May 2013.
9. A. R. Aswatha, Akshatha Ural H, “Providing service Differentiation in IEEE
802.16 Mesh Networks using FEBA”, International Journal of Innovative Research
& studies, Vol.2, Issue.6, ISSN 2319- 9725, pp.461-469.June 2013.
10. A. R. Aswatha and Shashidhar H R, “An Hardware Implementation of Palm
Recognition using 1-D DWT”, International Journal of Systems, Algorithms and
Applications, vol. 3, Issue 13, pp. 43-45, June 2013.
11. A. R. Aswatha, Rajeswari P, “Performance Analysis of Flash Analog to Digital
Converter with Track and Hold Circuit using CADENCE PSPICE”, Engineering
science and Technology: International Journal (ESTIJ), ISSN: 2250-3498, Vol.3, No.3,
pp.485-491, June 2013.
INTERNATIONAL CONFERENCE:
1. A. R. Aswatha, Sandesh R. S. and Chethan Kumar P, “A Low Power High “peed
64 bit ALU using 180nm”, International Conference on Advances in Computing,
Chikhli, India, Feb 21-22, 2008, pp.654-657.
2. A. R. Aswatha, Dr. T. Basavaraju and “. Sandeep kumar, “Fast and Efficient OnChip Interconnection Modeling for High “peed VLSI Systems”, Proceedings of
world Academy of Science, Engineering and Technology Rome, Italy, Vol. 28, pp
478- 481, April 2008.
3. A. R. Aswatha, Dr. T. Basavaraju and N. Bhaskara Rao, “Optimal Placement of
Processors based on Effective Communication Load”, Proceedings of world Academy
of Science, Engineering and Technology Rome, Italy, Vol. 28, pp 325-329, April
2008.
4. A. R. Aswatha, Dr. T. Basavaraju and S. Sandeep kumar, “Fast and Efficient OnChip Interconnection Delay Modeling for High speed VLSI Systems”, International
Conference on Emerging Trends in Engineering and Technology,2008, Nagpur,India,
July 2008, 978-0-7695- 3267-7/08 $25.00 © 2008 IEEE, PP.414-417.
5. A. R. Aswatha, Dr. T. Basavaraju and Kalpana A.B, “Efficient Power Modeling for
On- chip Global Interconnect” IEEE Midwest Symposium on Circuits and Systems,
Knoxvile, Tennessee USA, August,2008 2008.978-1-4244-2167-1/08/$25.00@2008
IEEE, PP.458-461.
6. A. R. Aswatha, Dr. T. Basavaraju, “Faster Delay Modeling and Power Optimization
for On-chip Global Interconnect” 2008 IEEE International Conference on
Semiconductor Electronics, Johar Bahru, MALAYSIA, 25-27 Nov 2008,1-42442561-7/08/$20.00@2008 IEEE, pp.82-86.
7. A. R. Aswatha, Sandeep. R, and Narayan T Deshpande “Design and Analysis of a
New Load less 4T SRAM cell in Deep Submicron CMOS Technologies”, 2009
International Conference
on Emerging
Trends
in
Engineering
and
Technology(ICETET-09), India Nagpur, India, PP.414-417, July2008].
8. A. R. Aswatha, Chaten. B. R, “FPGA Implementation of Vector Quantization for
Image Compression” International Conference on communication, computation,
control and Nanotechnology, Bhalki, India, ICN-2010. PP.418-424.
9. Sathish Shet K, Sanjaya Nagendra, Dr. A R Aswath “An ARM Based
Implementation of Adaptive DCT Based steganography” –International conference on
Computational Intelligence & information Technology-ICCIIT -2012 held on 2nd &
3rd March 2012, Organized by INFO institute of Engineering sathya road,
Kovilpalayam, Coimbatore 641107.ISBN 81-903041-9-4, Umayam publications, pp
IP01-IP05
10. Sachin J Katharki, Shashidhara H R, Dr. A R Aswath, “Digital Design of finger
print recognition based on Eigen Vector transform”, Proceedings of International
Conference on Electrical and Electronics Engineering (ICEEE-2012), 30th June
2012, Mysore-India, PP 114-118
11. A. R. Aswatha Vivekananda M, “Performance Analysis of Resources,”
International Conference on Advanced Computing and Information Technology
(ICACIT-2013) Bangalore, pp.134- 136, 2013.
12. A. R. Aswatha and “onia C.V, “SAPt: A stolen Android Phone Tracking Application,”
International Conference on Recent Trends in Engineering & Technology (ICRTET),
pp.236- 240, March 2013.
13. A. R. Aswatha and Shashidhara. H. R, “Digital Design of Fingerprint Recognition
Based on Eigen Vector Transform,” International conference on Electrical and
Electronics Engineering, pp.114- 118.2013.
14. A. R. Aswatha and Shashidhara. H. R, A Theoretical Survey on Face Recognition and
Markov Chains,” International conference on smart structures & systems (ISSS2013), pp. 41-50. March 2013.
15. Shilpa B M, Shashidhara H R, Dr. A R Aswath, “A Theoretical Study on Palm
Print Identification”, 2013 International Conference on smart structures & systems
(ISSS-2013), March 28 – 29, 2013, Chennai, INDIA, PP 46-50. (Soft copy)
16. A. R. Aswatha and Satish Shet K “Hardware Architecture for Image Steganography
based on LSB Technique,” International conference on Electrical Engineering and
Computer Science, pp.16- 19. June 2013.
17. Shashidhara H R, Shilpa B M, Dr. M V Latte, Dr. A R Aswath, “Hardware
Implementation of Palm Recognition using 1-D DWT”, International conference
on Electrical, Electronics and Computer Science-2013 (ICEEC-2013) held at
Hyderabad on 8th of June 2013, Organized by Association of Scholars and
Professionals (ASP), ISBN: 978-93-83060-04-7, PP 12-15. (Soft copy)
18. A. R. Aswatha and Shashidhar H R “Digital Design of Face Identification based on
Markov Chain Monte Carlo Method,” International conference on Electrical
Engineering and Computer Science, pp.9-11. June 2013.
19. Sathish Shet K, Dr. A R Aswath “VLSI Implementation of Image Steganography
Algorithm.” International Conference on Convergence of Science, Engineering &
Management (ICCSEM - 2013), Dayananda Sager College of Engineering, 26th
and 27th September, 2013, PP 177.
20. Shashidhara H R, Dr. A R Aswath, “A Novel Approach to Circular Edge
Detection for Iris Image Segmentation” Fifth International Conference on Signals
and Image Processing, ICSIP-2014, IEEE Computer Society, held at BNMIT,
Bangalore on 8th to 10th Jan 2014, PP 316-320.
21. Rahul R, Dr. A. R. Aswath “A Novel Approach for Efficient Decentralized
Averaging in Wireless Packet Network” International Conference on Advances in
Computer & Communication Engineering, ACCE-2014, Vemana Institute of
Technology, Bangalore on 21 & 22 April 2014, pp.232-235.
NATIONAL CONFERENCES:
1. A. R. Aswatha and Chethan Kumar P, “Digital Data Subsystem Design for Passive
RFID tag”, National Conference on Advanced VLSI / DSP Bangalore, pp.26-31,
January 22-25, 2008.
2. A. R. Aswatha and Chethan Kumar P, Sandesh. R. S, a low power, High Speed 64 bit
ALU using 180nm. National Conference on Advanced VLSI / DSP Bangalore, pp.4346, January 22-25, 2008.
3. A. R. Aswatha and N. Bhaskararao “Binary Data sequence reordering to minimize the
total hamming distance”, National Conference on VLSI and Communication
Kottayam, pp.214-218, March 14-15, 2008.
4. A. R. Aswatha, Sandeep.R, and Narayan T Deshpande, “Design and Analysis of
1Kbit low power “RAM using a new loadless 4T “RAM cell”, National conference
Emerging trends in engineering technology and applications-2009 (NCETETA-09),
Bangalore.pp.182-188.
5. Sathish Shet K, Sanjaya Nagendra, Dr. A R Aswath “Theoretical survey on Soc
based implementation of Digital Image Steganography”, at 2nd National Level
Technical paper presentation on 14/10/2011 organized by SJB institute of
Technology, Bangalore, 560060.
6. A. R. Aswatha and Imesagla, Color Extended Visual Cryptography using Error
Diffusion, National Conference on current trends in computer science and Engineering
(CSECONF- 2012), Bangalore, pp.198-200,2012.
7. Mohan G, Shashidhara H R, Dr. A R Aswath, “CMOS based Processing Unit of
Bio- Potential Acquisition Device”, Proceedings of National Conference on
Advanced Communication Trends (ACT’12), 23rd and 24th Aug 2012, RRCE,
Bengaluru, India, PP 155-160.
8. Sachin J Katharki, Shashidhara H R, Dr. A R Aswath, “Intellectual property of
fingerprint recognition based on Karhunan-Loeve Transformation”, Proceedings
of National Conference on Advanced Communication Trends (ACT’12), 23rd and
24th Aug 2012, RRCE, Bengaluru, India, PP 150-154.
9. A. R. Aswatha and Sonia C.V Anti- Theft Application for Smart phones, National
Conference on recent Trends in Communication and Networking (NCRTCN-2013)
Bangalore, pp.108-111, 2013.
10. A. R. Aswatha, Akshatha Ural H, “Differentiation Services with a Bandwidth
Allocation Algorithm in IEEE 802.16 Mesh Networks”, National Conference on
Electronics, Communication and Advanced Networks, ECAN’2013, pp.12-15