1
Hybrid Extraction Method for Determining Circuit Elements of AlGaN/GaN HFETs
By QIAN FAN, JACOB H. LEACH, Student Member, IEEE AND HADIS MORKOç
ABSTRACT: The developments in AlGaN/GaN heterojunction
field effect transistors (HFETs) are beginning to allow harnessing
of the great potential of this technology in high power RF
applications. However, the integration of HFETs into a circuit
environment requires accurate small and large signal modeling of
the device operating under various biasing conditions. The
conventional small signal equivalent circuit modeling methods
consist of “cold” measurements for extracting parasitic elements,
and on-bias measurements in determining the intrinsic device
circuit elements. Also, the optimization routines are often
explored directly using the “hot” measurement data to minimize
errors. In this paper, an 18-element small signal equivalent
circuit model for AlGaN/GaN HFETs is proposed and
implemented, and contrasted to various de-embedding methods.
Among the methods treated, the hot-FET optimization extraction
based on the parasitic capacitances obtained from cold
measurements leads to the smallest error between the simulated
S-parameters and the measured ones at all bias points employed,
with an average error of about 5%. This hybrid extraction
algorithm is strengthened by imposing constraints to avoid any
non-physical convergence. We note that the extrinsic parasitics
determined by this method differ considerably from the values
obtained by cold-FET measurements, which implies that the
assumption on the bias independency for extrinsic parameters in
the latter method might be questionable for AlGaN/GaN HFETs.
KEYWORDS: Gallium Nitride, Heterojunction Field Effect
Transistors, Equivalent Circuits, Small Signal, Parasitic
I. INTRODUCTION
T
HE AlGaN/GaN HFETs have already demonstrated many
advantages over GaAs-based devices for microwave
power applications due to the unique properties of GaN-based
materials such as high breakdown voltage, high carrier
concentration and along with reasonable carrier mobility, and
high thermal conductivity as described in [1]. A typical
AlGaN/GaN HFET device structure along with its conduction
band diagram is shown in Fig. 1. Because of the strong
spontaneous and piezoelectric polarization of GaN and its
ternary, a high density two dimensional electron gas (2DEG)
is induced at the heterojunction interface and confined in the
triangular potential well due to the large band discontinuity.
The high electron velocity, which is estimated above 107 cm/s,
bodes well for high frequency operation, and the large
breakdown voltage allows for high power applications to be
exploited. In this endeavor, the GaN-based HFETs exhibit
great potential in RF power and switching applications. With
the rapid development of semiconductor epitaxy, device
processing, and system integration, an industrial supply chain
for GaN power devices is emerging.
Fig. 1 The schematic of AlGaN/GaN HFETs structure, conduction band
diagram and electron distribution.
It should be noted, however, that any successful system
level design of power amplifiers, oscillators, or mixers
requires accurate empirical device modeling, which must
provide a circuit level description of a device's nonlinear
properties. In this vein, small signal equivalent circuit
modeling plays an important role in gaining the much needed
insight into device nonlinearity at least in the static sense
when carried out at different bias conditions. Clearly, the
validity of device modeling is dependent on the accuracy of
the small signal extraction routine employed.
Standard small signal extraction methods [2], [3] are
well-established for GaAs HFETs or SiC MESFETs.
Basically, the equivalent circuit can be divided into the
intrinsic part, for which the values are a function of bias, and
the extrinsic part that has no dependence on the bias
conditions. Usually each element is obtained by fitting the
scattering parameters measured directly from the device.
Accurate measurement of S-parameter is imperative for
determining the equivalent circuit parameters realistically
which in turn paves the way for the extracted values to have
any physical significance. Although not without controversy, a
good step in this direction is “cold” measurements under
channel pinch-off biasing conditions (VDS = 0V, VGS ≤ 0), at
which the intrinsic circuit part can be simplified, is crucial for
extracting the bias-independent extrinsic parameters such as
parasitic resistances or capacitances. With the parasitic
elements determined, confidence in determining the other
parameters from s-parameter can be enhanced.
The above mentioned extraction methods have been applied
to GaN based HFETs [4], [5]. The most comprehensive model
for a GaN HFET is proposed by Jamdal and Kompa in [6] and
consists of 22 distributed elements, which is reliable, general,
and applicable for large signal case as well. The circuit model
for GaN HFETs is often more complicated than traditional
2
FETs in order to account for behavior somewhat unique to
GaN such as the gate leakage current, self-heating, or
defect-induced dispersion effects [7], [8]. The validity of the
extraction of the bias-independent parasitic elements using the
cold-FET methodology on GaN HFETs is still under some
question [9], perhaps due to the relatively high contact
resistance for GaN ohmic metallization [10].
Some hot-FET extraction methods have been reported in
[11], [12], which attempt to optimize and calculate the
equivalent circuit elements including both the intrinsic and
extrinsic ones directly from data measured at the operation
bias point. Full optimization procedures, in which the
optimization algorithm used determines each and every
element, are typically reported to provide very high agreement
between simulation and measurement. However, the problems
of non-physical or initial value dependent convergence shown
in [13] make these methods less desirable, particularly if
verification over a wider bias and scaling range is desired.
In this paper, we propose and implement an 18-element
small-signal model for GaN HFETs, and consider various
extraction methods. A hybrid extraction technique combining
a cold measurement together with an optimization routine is
developed which leads to a better agreement between the
measured and simulated S-parameters compared with
conventional cold measurements. It also provides better
accuracy over the entire range of biasing conditions.
II. DEVICE PROCESSING AND CHARACTERIZATION
The Al0.25Ga0.75N/GaN heterojunction FET structure used in
this investigation was grown on c-sapphire by low-pressure
metal-organic chemical vapor deposition (MOCVD). First a
300 nm semi-insulating AlN buffer layer was deposited at
1050 ºC, followed by a 3 µm thick un-doped GaN layer and a
thin AlN spacer with thickness ~1-2 nm. Next the 20 nm
Al0.25Ga0.75N barrier layer was grown, intentionally doped
with Si to 8×1017 cm-3, which does not really add much to the
2DEG next to the much larger polarization induced charge,
followed by a 2 nm un-doped GaN cap layer.
The temperature dependent transport properties from this
structure are shown in Fig 2, as determined by Van der Pauw
patterned Hall measurement. The room temperature electron
sheet concentration is 1.10×1013 cm-2, with the mobility of
1200 cm2/Vs. The HFET devices were fabricated by first
depositing the source/drain ohmic contacts using Ti/Al/Ni/Au
and rapid thermal annealing (RTA) at 800 ºC for 1 minute in
N2 ambient. Mesa isolation was then carried out by
dry-etching in a parallel plate RIE system using BCl3 plasma.
Finally, 2× 80 μm wide gates with a gate length of 1 μm were
defined and Ni/Au was deposited as the gate metal.
The DC performance of the devices was examined by a
Keithley parameter analyzer, as shown in the inset of Fig 2.
The appropriate quiescent point (Q-point) was determined to
be between VDS = 5 ~ 7 V, VGS = -2 ~ -4 V. The on-wafer
S-parameters of various devices from the same wafer were
measured by an HP (Agilent at the moment) 8510B network
analyzer with the highest frequency available being 20 GHz.
The cold pinch-off measurement was carried out at VDS = 0 V,
VGS = -7 V in order to subtract the pad parasitic capacitances.
2.4x10
13
500
V
GS
400
4
1.2x10
4
=0~-5V
300
2x1013
1.5x10
200
9000
100
1.6x10
13
0
0
2
4
6
8
V
(V)
DS
1.2x10
13
8x10
12
10
6000
3000
0
50
100
150
200
250
300
0
350
Temperature (K)
Fig. 2 The temperature dependent transport properties of the
AlGaN/AlN/GaN HFET structure. The insert shows the typical IV (DC)
characteristics of the HFETs.
III. EQUIVALENT CIRCUITS
As a three-terminal device, the extrinsic circuit for the FETs
must include three parasitic resistances and inductances
associated with each contact and wire connection. In principle,
these elements should be as small as possible, although for
wide band gap semiconductors the Ohmic contacts still require
some attention.
Regarding the capacitances, there are often two sets, namely
the parasitic capacitances introduced by the pad connection or
probe contacts described as Cgsp, Cdgp and Cdsp; and the those
accounting for the inter-electrode capacitances such as Cgsi,
Cdgi Cdsi. They are all implemented in [6], and the
de-embedding procedure (an optimization-based routine)
requires the initial values estimated from empirical
assumptions. In order to reduce the complexity of the
modeling procedure, the inter-electrode capacitances are often
neglected by many authors [14], [15] since these values are
always relatively small. In our effort, we propose an
equivalent circuit for the GaN HFET as shown in Fig 3. The
part outside the dashed box is the extrinsic one, in which the
Cdgp is also neglected in favor of the simplicity of optimization
routines as described below.
Rfdg
G
Lg
Rd
Rg
Cdg Rdg
V
Cgs
Rfgs
Ids
Ld
D
Cds
Rds
Ri
Cdsp
Cgs
Rs
Ls
S
Ids=gmVie-jωτ
S
3
Fig. 3 The proposed 18-elements small signal equivalent circuit for a
GaN-based HFET, within the dashed box is the intrinsic part.
For the intrinsic circuit model, the consistency between
GaN HFETs and GaAs- or SiC-based power transistors is
obvious. The traditional model often consists of 8 elements
with explicit physical significance. For example, the charging
resistance Ri represents the electron recombination with
donors in the depletion region under the gate; and the transit
time τ is the time it takes for the depletion region to respond to
the change in the gate signal. But for GaN HFETs, the
scenario is little more complicated. The differential resistances
introduced in [15], Rfdg and Rfgs, are necessary for
characterizing the current conduction through the gate diode.
Reference [14] even considered the possible existence of time
delays in the output conductance element (Rds). Addition of
uncertainties onto the intrinsic circuit, however, will overly
complicate the system of equations. To circumvent the
ensuing complexity, we will examine a 10-element intrinsic
circuit model similar to [6], which is believed to have
sufficient accuracy and also applicable for large signal
analysis.
IV. COLD-FET EXTRACTION
The key in the small signal de-embedding methodology lies
in the determination of extrinsic circuit elements. Therefore,
most efforts have concentrated on cold-FET measurements
(VDS = 0) at near-zero drain current conditions to signify the
parasitic parameters.
A. Parasitic Capacitances
The pad capacitances can be extracted under a pinched-off
“cold-FET” condition (VDS = 0, VGS <<0) at low frequencies
(in the MHz range) so that the influence of inductances can be
minimized. Under the pinch-off bias conditions, the channel
conductivity is negligible and the S-parameters measured
exhibit capacitive properties. Consequently, the equivalent
circuit complexity can be reduced as shown in the inset to Fig
4 if one considers only the imaginary part of the Y-parameters,
[3], with the assumption of a symmetric gate depletion region.
It then leads to the following relationships:
(1)
Im( Y11 ) = ω (C gsp + 2 ⋅ C b )
Im( Y12 ) = Im( Y21 ) = −ω C b
(2)
Im( Y22 ) = ω (C dsp + C b )
(3)
where Cb is all of the remaining capacitances of the circuit.
Cb
2.0x10 -3
C
Cb
C
gsp
dsp
-Im(Y )
12
1.5x10
-3
1.0x10
-3
5.0x10
-4
Im(Y )+Im(Y )
22
12
Im(Y )+2Im(Y )
11
0.0
0
9
2x10
9
4x10
ω(rad/s)
12
9
6x10
9
8x10
Fig. 4 Reduced equivalent circuit for pinch-off Cold-FET condition, and
the parasitic pad capacitances determined by linear regression at VDS = 0 V,
VGS = -7 V, frequencies from 150 MHz to 1.0 GHz.
The pad capacitances extracted from a typical device under
different bias conditions by calculating the slope of the
imaginary Y-parameters linearly fitted over frequency are
listed in Table 1. Higher applied biases result in stable values
of these parasitics. As suggested also in [16], a high gate bias
is desired to suppress the differential resistance and obtain the
values for parasitics accurately. But a high gate bias would
also introduce surface state-assisted tunneling charge and
ensuing current flow, and subsequent gate breakdown
problems, which, as we observed, fail to produce reliable
capacitance values for some devices.
Table 1
Gate Bias (V)
Cgsp (pF)
Cdsp (pF)
-5
0.095
0.102
-6
0.081
0.054
-7
0.069
0.062
-8
0.063
0.061
-9
0.067
0.057
The extracted pad capacitances under different pinch-off bias.
B. Parasitic Inductances and Resistances
The parasitic inductances and resistances are generally
measured under cold-FET conditions with large forward gate
bias (VDS = 0, VGS >>0) in order to reduce the depletion
capacitance to a large extent [17]. However, it has been
pointed out by many groups that this bias condition is not
applicable to GaN HFETs. Because of the existence of gate
differential resistances, it often requires very high forward
gate bias to eliminate the channel capacitive, which is usually
accompanied by the unrecoverable damage onto the gate.
Therefore, for GaN HFETs, the prevalent methods used to
extract these inductances and resistances are often conducted
at zero or small negative gate bias conditions. Another
advantage for these bias conditions is the ability to simplify
the circuit model to a symmetry form in favor of extraction.
Under such bias conditions, after de-embedding the pad
4
capacitances measured from Section IV A, the rest of the
device is modeled with equivalent circuit shown in Fig 5.
5.0x1011
G
Lg
Rg
ΔZg
Rd
Cd ΔZd
Cg
Ld
D
ωIm(Z )-ωIm(Z )
22
12
0.0
Cs
ωIm(Z 12 )
ΔZs
-5.0x1011
Rs
ωIm(Z 11 )-ωIm(Z 12 )
-1.0x1012
Ls
S
S
(a)
12
Fig. 5 Reduced equivalent circuit for low gate bias Cold-FET condition,
after removing the pad capacitances.
The residual intrinsic impedance terms (ΔZi=g,s,d) in Fig 5
are always treated as channel resistances. As such they have
no influence on the imaginary part of the Z-parameters, from
which the parasitic inductances are determined by linearly
fitting Im(ωZij) over ω2:
1
1
(4)
+
Im( ω Z ) = ω 2 ( L + L ) − (
)
11
s
g
Im( ω Z 22 ) = ω 2 ( L s + Ld ) − (
Im( ω Z 12 ) = ω 2 L s −
1
Cs
Cs
1.0x1022
1.5x1022
1
1
+
)
Cs Cd
(5)
(6)
(8)
(9)
Re( Z 22 ) = R s + R d + R ch
In order to determine four unknowns out of three equations,
various bias points need to be measured to interpolate Rs+Rd,
which was beautifully done in [4]. In our method, we
neglected the channel resistance at zero gate bias, as suggested
in [6], making the determination of parasitic resistances much
easier.
On the devices from which we extracted pad capacitances,
the parasitic inductances and resistances were calculated over
the high frequency range from 10 GHz to 20 GHz to minimize
the error from residual capacitive terms. Fig 6 shows the linear
fit of ωRe(Z) vs. ω, and ωIm(Z) vs. ω2 measured at zero gate
bias. If we neglect the residual terms, then the resulting
parasitics are: Rs = 4.45Ω, Rd = 5.47Ω, Rg = 3.69Ω, Ls =
6.82pH, Ld = 36.99pH, Lg = 52.19pH. As can be noted in Fig 6,
the curve fittings for gate parasitics show a larger spread.
They are also more sensitive to the frequency range in which
the fitting is performed, similar to what was observed in [21].
Therefore, the cold measurement method provides a better
accuracy and thus more confidence in the source and drain
parasitic resistances and inductances than those of the gate.
2.0x1022
ω (rad /s )
2
2
2
12
1x10
ωRe(Z12 )
11
8x10
ωRe(Z22 )-ωRe(Z12 )
Cg
The extraction of parasitic resistances, on the other hand,
depends on ΔZi which is expressed in various ways in
different reports. For example, from zero to a low negative
gate bias range, it follows:
(7)
Re( Z 11 ) = R s + R g
Re( Z 12 ) = R s + R ch / 2
-1.5x10
5.0x1021
11
6x10
11
4x10
ωRe(Z11 )-ωRe(Z12 )
(b)
11
2x10
10
8.0x10
1.0x10
11
11
1.2x10
1.4x10
11
ω(rad/s)
Fig. 6 (a) Parasitic inductances determined from cold measurement at VDS =
0 V, VGS = 0 V, at frequencies from 10 GHz to 20 GHz. (b) Parasitic
resistances determined under the same condition.
C. Intrinsic Circuit Extraction
With the knowledge of extrinsic parasitic parameters, the
intrinsic circuit elements shown in Fig 3 can be extracted from
the S-parameters measured under the working bias conditions.
After de-embedding the extrinsic components, the
Y-parameters for the intrinsic part of the device can be
expressed as:
⎡ ( jω C gs Ri− 1 ) + ( j ω C dg R dg−1 ) + R −fdg1 + R −fgs1
⎢
Yint = ⎢
g m e − jωτ
− ( jω C dg R dg−1 ) − R −fdg1
⎢ 1 + j ω C gs Ri
⎣
− ( j ω C dg R dg−1 ) − R −fdg1
R ds−1 + R −fdg1 + j ω C ds + ( j ω C dg
⎤
⎥
R dg−1 ) ⎥
⎥
⎦
(10)
with A B =
A⋅ B
.
A+ B
The intrinsic differential resistances (Rfgs and Rfdg) are first
estimated from Y11 and Y12 at low frequencies (in the
megahertz range), since the capacitance terms tend to vanish
at such low frequencies. Then, separating the real and
imaginary parts in Equation (10) paves the way for
5
determination of the rest of the eight intrinsic parameters [15].
The calculated intrinsic parameters for the same device are
listed in Table 2, where ΔS refers to the average error between
the calculated and measured S-parameters over the entire
frequency range.
G
Lg
Rd
Rg
Vi
Cdg
Ids
Cgs
Ld
D
Rds Cds
Ri
Table 2
4.45
Ls (pH)
6.82
Rs (Ω)
Ld (pH)
5.47
36.99
Rd (Ω)
Lg (pH)
3.69
Rg (Ω)
52.19
69.0
Rfgs (kΩ)
0.91
Cgsp(fF)
62.0
6.84
Cdsp(fF)
Rfdg (kΩ)
571.06
Ri (Ω)
8.62
Cgs (fF)
0.00
153.33
Cds (fF)
Rds (Ω)
76.44
23.02
Cdg (fF)
Rdg (Ω)
gm (mS)
41.57
ΔS
9.82%
τ (ps)
1.38
The extracted extrinsic parameters from cold-FET measurements, and
intrinsic parameters from determined S-parameters measured at VDS = 4
V, VGS = -3 V, frequencies from 2 GHz to 20 GHz.
V. HOT-FET EXTRACTION
Determination of parasitic circuit elements, as we can see, is
imperative for the whole de-embedding procedure. Instead of
cold measurements, hot-FET extraction methods attempt to
find out the parasitic parameters for the biased conditions.
This is necessitated due to the dependence of the FET’s
parasitics on bias [18]. Especially for the access resistances,
they have been reported to be more critical in GaN HFETs
than in other the material systems [9]. Consequently, we
examine two hot-FET extraction methods proposed by
Manohar et al. and Shirakawa et al. in [10] and [11]. The first
method is analytical fitting based while the second is pure
optimization based, as elaborated on below.
A. Analytical Method
For this method, in order to provide the analytical
expressions for the circuit elements, the model needs to be
simplified as shown in Fig 7. Assuming the pad capacitances
are known and de-embedded, the parasitic resistances and
inductances can then be correlated with the Z parameters of
the rest. Starting from the source pad extraction, it has:
Im( Z 12 ) C gd
(11)
=
X 1 + LS
ω
gm
Re( Z 12 ) =
C gd
gm
X 2 + RS
with
X 1 = sin( ωτ )[Im( Z 21 ) − Im( Z 12 )] + cos( ωτ )
[Re( Z 12 ) − Re( Z 21 )]
X 2 = ω cos( ωτ )[Im( Z 21 ) − Im( Z 12 )] − ω sin( ωτ )
[Re( Z 12 ) − Re( Z 21 )]
Rs
Ls
Ids=gmVie-jωτ
S
S
Fig. 7 Circuit model for analytical extraction method proposed in [10]
By linearly fitting Im(Z12)/ω on X1 and Re(Z12) on X2, the
source Rs and Ls can be extracted by extrapolation. Once Rs
and Ls are determined, the rest of the parasitic resistances and
inductances can be extracted by polynomial fitting over the
frequency on the real and imaginary parts of the following
equations:
Y
Z 12 − Z s
(15)
= − 12 ,int
Z 11 − Z s − Z g
Y22 ,int
Y
Z 12 − Z s
= − 12 ,int
Z 22 − Z s − Z d
Y11 ,int
(16)
Here Zi = Ri+jωLi (i = g, s, d).
Noting that the validity of equations (11) and (12) is based
on the assumption that (ωRiCgs)2 ~ 0, the linear regression is
best if done for frequencies below 5 GHz. For example, the
linear regression in determining the source resistance is
illustrated in Fig 8 using the data on the same device. The
intrinsic parameters are then calculated after the determination
of the parasitics. The transition time τ used for equations (13)
and (14) is initially set to be 1ps, and updated iteratively till its
convergence satisfied.
30
29.5
Y = 3.58+2.40 X
29
2
2
RS = 3.58 Ohms
28.5
28
(12)
27.5
(13)
(14)
27
9.6
9.8
10
10.2
10.4
10.6
10.8
11
X2
Fig. 8 The illustration of analytical method to determine source parasitic
resistance.
Table 3 shows all the calculated circuit parameters. Here,
some of the extracted parasitic resistances and inductances are
comparable with the results from cold measurements.
However, the parasitic inductances exhibit large variations and
fitting errors. The calculated inductances vary significantly
when different frequency ranges are used. Sometimes the
6
parasitic values obtained by this method are negative which is
non-physical even though extreme care was used in during
calibrations and measurements. Besides the possible reason
that the pad parasitics may change for hot-FET conditions
compared with cold-FET, the omission of the gate differential
resistances (Rfdg and Rfgs) , especially when they are in the
few kΩ range, may introduce considerable error to the
analytical expressions (11) and (12).
Re[ Y1 (ω + Δ ω ) − Y1 (ω )]
(ω + Δ ω ) Im[ Y1 (ω + Δ ω )] − ω Im[ Y1 (ω )]
C gs ⋅ Ri =
(18)
Moreover we find:
R −fgs1 = Re[ Y1 (ω )] − ω Im[ Y1 (ω )] ⋅ (C gs ⋅ Ri )
(19)
ω C gs = Im[ Y1 (ω )] ⋅ [1 + (ω ⋅ C gs ⋅ Ri ) ]
(20)
2
Table 3
3.58
Ls (pH)
85.54
Rs (Ω)
Ld (pH)
6.12
216.72
Rd (Ω)
Lg (pH)
0.00
Rg (Ω)
112.65
69.0
Cgsp(fF)
62.0
Cdsp(fF)
415.90
Ri (Ω)
11.07
Cgs (fF)
0.98
215.33
Cds (fF)
Rds (Ω)
71.23
Cdg (fF)
gm (mS)
28.84
ΔS
14.8%
τ (ps)
0.89
The calculated circuit parameters by analytical method, directly from
hot-FET data on the same device measured at VDS = 4 V, VGS = -3 V.
Pad capacitances obtained from cold measurements.
B. Optimization Method
In [11], a pure optimization procedure has been developed
to extract extrinsic and intrinsic parameters simultaneously for
the conventional GaAs HFETs, using the same equivalent
circuit shown in Fig 7. After de-embedding the parasitic
capacitances, the Z-parameters for the intrinsic and extrinsic
part are related by:
Z int = Z − Z ext
⎡ R + R s + jω ( L g + Ls )
=Z −⎢ g
R s + jω L s
⎣
R s + jω L s
⎤
R d + R s + j ω ( L d + L s ) ⎥⎦
(17)
The basic idea of the optimization procedure is to express all
of the intrinsic elements as functions of ω and an extrinsic
vector, Zext (Rd, Rg, Rs, Ld, Lg, Ls). By assuming that all
intrinsic elements are frequency independent, we can obtain
the optimized values for both the extrinsic and intrinsic
parameters through minimizing their variance over frequency.
It should be mentioned that the 7-variable intrinsic circuit
is not suitable for a GaN-based device. Especially Rfdg and Rfgs
are important in characterizing the current conduction of the
gate diode applicable for large signal analysis. We should also
note that the traditional optimization procedures can hardly
handle the 10-variable intrinsic circuit shown in Fig 3. This
has its genesis in the fact that it is impossible to express all 10
variables solely as a function of ω in light of the fact that there
are only 4 measured pieces of data, including the real and
imaginary parts, at each frequency.
Our approach is to find expressions for each of the intrinsic
circuit elements in terms of the intrinsic Y-parameters at
multiple frequencies. In other words, we chose a proper ∆ω so
that at each frequency ω, all the elements are determined from
both Y(ω) and Y(ω+∆ω). Taking the Rfgs, Ri, Cgs sub-circuit as
an example:
where Y1 = Y11,int+Y12,int. Similarly, the Rfdg, Rdg, Cdg
sub-circuit follows:
C dg ⋅ R dg =
Re[ Y2 (ω + Δ ω ) − Y2 (ω )]
(ω + Δ ω ) Im[ Y2 (ω + Δ ω )] − ω Im[ Y2 (ω )]
(21)
R −fdg1 = Re[ Y2 (ω )] − ω Im[ Y2 (ω )] ⋅ ( C dg ⋅ R dg )
(22)
ω C dg = Im[ Y2 (ω )] ⋅ [1 + (ω ⋅ C dg ⋅ R dg ) 2 ]
(23)
where Y2 = -Y12,int.
When programming, we also smoothed the calculated
values by averaging them within several adjacent data points
in order to reduce the scatter caused by any error in the
measurement. The rest of the 4 intrinsic parameters are
expressed as follows:
R ds− 1 = Re( Y22 ,int + Y12 ,int )
(24)
ω C ds = Im( Y22 ,int + Y12 ,int )
(25)
g m = (Y21 ,int − Y12 ,int ) ⋅ [1 + j ω (C gs ⋅ Ri )]
(26)
Im{( Y21 ,int − Y12 ,int ) ⋅ [1 + j ω ( C gs ⋅ Ri )]}
ωτ = tan −1
Re{( Y21 ,int − Y12 ,int ) ⋅ [1 + j ω (C gs ⋅ Ri )]}
(27)
The variance of each intrinsic element is:
N
εi =
∑ [ f (ω
k =1
i
k
, Z ext ) − f i (ω , Z ext ) ] 2
N −1
( i = 1, 2 , " 10 )
(28)
Here fi represents the analytical expressions of each intrinsic
parameter obtained from Equations (18) through (27). We
define a global weighted scalar as the objective function for
the optimization routine:
10
ε = ∑ Wiε i
(29)
i =1
The weighting factors are selected from the normalization of
minimum variance according to the optimization procedure
performed on each intrinsic parameter. In another word, if
ℜ(⋅) denotes the optimization routine, its output will give
both the minimized variance and corresponding optimized
7
extrinsic vector:
ℜ( fi , ε i , Z
Table 4
initial
ext
) → [εˆi ,
Z
optimized
ext
(30)
]
Then Wi is defined as:
Wi =
1
(31)
εˆi
To avoid any non-physical convergence, we also strengthen
the optimization routine by imposing the following inequality
constraints:
2.80
Ls (pH)
81.55
Rs (Ω)
Ld (pH)
3.94
180.91
Rd (Ω)
Lg (pH)
0.00
Rg (Ω)
13.61
69.0
Rfgs (kΩ)
0.93
Cgsp(fF)
62.0
22.96
Cdsp(fF)
Rfdg (kΩ)
489.26
Ri (Ω)
3.30
Cgs (fF)
0.00
197.17
Cds (fF)
Rds (Ω)
76.56
72.72
Cdg (fF)
Rdg (Ω)
gm (mS)
32.92
ΔS
3.86%
τ (ps)
0.51
The calculated circuit parameters by optimization method, directly from
hot-FET data on the same device measured at VDS = 4 V, VGS = -3 V.
Pad capacitances obtained from cold measurements.
200
Rdg without Rfdg
[ R d , R g , " , L s ] ≥ 0 and [ f1 , f 2 , " , f10 ] ≥ 0
(32)
Rdg = -Re(1/Y 12, int )
150
Rdg with Rfdg
A sequential quadratic programming (SQP) algorithm [19],
which is a generalization of Newton’s method, is utilized in
solving this constrained optimization problem. The objective
function and the constraints are replaced with the quadratic
and linear approximation, respectively. The convergence
properties of the algorithm can be improved by using a line
search with penalty parameters recommended in [20]. Noting
that it is a gradient-based method, the convergence of the
program relies on the continuity of the objective function.
Therefore, the measurements should be carefully conducted to
avoid large noise or the moving of the reference planes.
(a)
100
R without R
i
50
15
fgs
Ri with Rfgs
0
0
0
5
10
15
20
Frequency (GHz)
600
Cgs
400
Cold pinch-off
measurement
Hot
measurement
(b)
Start
Optimization
200
De-embedding
capacitances
contribution
Extract Cgsp, Cdsp
C
0
Find intrinsic
element fi
10
∑W ε
i =1
i i
as
objective function
Run optimization
Obtain optimized Zext
Calculate intrinsic parameters
Evaluate S-parameters
Update Zext
dg
Cds
Calculate intrinsic Zand Y-parameters
For i = 1~10
Set εi as objective function
Run optimization for fi
Obtain Wi
Set ε =
Set initial value for
Zext and ∆ω
-200
0
5
10
15
Frequency (GHz)
20
Calculate objective
function
40
Objective
< Criterion
15
N
Y Output data
End
10
30
(c)
5
Fig. 8 Flow chart diagram for the optimization extraction procedure.
In short, our optimization routine first finds the weighting
factors by minimizing the variance for each intrinsic element
over frequency. Then the weighted average error is set to be
the objective function, and the routine is run again to obtain
the globally optimized extrinsic vector. Finally, all intrinsic
parameters are calculated and the S-parameters are evaluated.
The flow chart demonstrating this extraction procedure is
shown in Fig 8. The calculated intrinsic and extrinsic
parameters are listed in Table 4.
20
0
10
-5
0
5
10
15
Frequency (GHz)
20
8
1/3S
21
5S
12
S
11
S22
(d)
Fig. 9 Optimized intrinsic elements from the data measured at VDS = 4 V,
VGS = -3 V, and frequencies from 2 GHz to 20 GHz. (a) Ri and Rdg, with
and without the differential resistances Rfdg and Rfgs considered. (b) Cdg, Cgs,
and Cds. (c) gm and τ. (d) Measured (×) and simulated (line) S-parameters
In Fig 9, we display some of the intrinsic parameters
determined by the routine. The calculated intrinsic parameters
have shown good frequency invariance properties. In order to
demonstrate the importance of the differential resistance
values, we also optimized and simulated a simplified intrinsic
circuit model without the differential resistances. Neglecting
them imparts a profound effect onto Rdg and Ri at lower
frequencies as shown in Fig 4 (a). A good agreement is
achieved between measured and simulated S-parameters with
only a 3.86% average error as indicated in Table 4, in 2 ~ 20
GHz frequency range with VDS = 4 V, VGS = -3 V.
conditions. Also for GaN HFETs, the effect of material defects
be also involved since the frequency range used for extrinsic
element extraction between hot and cold methods are different.
The error generated in the cold measurements could propagate,
affecting the accuracy of the intrinsic parameters obtained
thereafter.
From a mathematical point of view, the optimization-based
extraction routine will undoubtedly produce the smallest error
at one given bias condition. The method is more practicable if
its stability can be verified by testing whether the results
depend on the initial input vector. By selecting all zeroes,
random numbers, and results from the cold measurement as
the initial values for Zext, we found that for each bias, the
routine led to the same results regardless of the initial values
chosen. Furthermore, it is more meaningful to evaluate the
validity of this method at various bias conditions. Thus, 15
different bias conditions were tested for one device as shown
in Table 5. The overall simulation error is seen as
approximately 5%. In contrast, this error increases to more
than 10% for the corresponding bias points using the constant
extrinsic parameters from cold measurements. In large signal
device nonlinearity analysis, it is usually convenient to assume
the extrinsic parameters to be constant. If one were to do so by
taking the mean value of the extrinsic parameters over all bias
points as the set of bias-independent extrinsic parameters, the
error will increase, remaining below 9% for every bias
condition.
Table 5
VGS (V)
VDS (V)
3.0
VI. DISCUSSIONS AND CONCLUSIONS
Arguably, the equivalent circuit for a GaN HFET is slightly
more complicated than the conventional models for GaAs or
SiC devices. Consideration of the gate differential resistances
is necessary, which under the reverse bias conditions represent
leakage current paths of the gate Schottky diode. Due to the
defects and dislocations in the crystal and assistance from
surface states or traps, the leakage current term is always
non-negligible. Especially at low frequencies where the value
of ωC is small, the differential resistance term will dominate
the total conductance. Although the increase in the number of
circuit elements brings extra complexity in hot-FET extraction,
the intrinsic parameters can still be calculated via the
strengthened optimization routine.
By analyzing and comparing different small signal
modeling methods, we could examine the validity and
consistency of the results. In our GaN HFET device, the
parasitic resistances extracted under different techniques are
consistent, while the parasitic inductances show large
variation. Basically, the inductances calculated from hot-FET
models are always larger than that from cold-FET
measurements. This difference may reflect the change of the
pad parasitics under hot bias conditions compared with cold
4.0
5.0
6.0
7.0
-2.5
-3.0
-3.5
8.21, 0.93, 3.32
4.47%
2.72, 11.67, 3.95
5.47%
4.36, 6.32, 2.19
4.32%
0.00, 14.67, 3.63
5.42%
0.00, 4.19, 0.00
2.64%
Rs , Rd , Rg (Ω)
ΔS
8.34, 3.26, 4.19
6.71%
2.80, 3.94, 0.00
3.86%
0.00, 4.45, 3.58
5.32%
2.14, 6.65, 1.05
5.46%
0.00, 11.24, 2.44
5.76%
Rs , Rd , Rg (Ω)
ΔS
0.00, 8.73, 2.64
4.00%
3.43, 7.78, 1.13
5.73%
0.00, 4.83, 3.58
5.39%
2.20, 9.09, 2.50
5.34%
0.00, 0.00, 2.89
4.50%
Rs , Rd , Rg (Ω)
ΔS
Average: Rs = 2.28 Ω, Rd ＝ 6.52 Ω, , Rg ＝2.47Ω
The parasitic resistances and calculated S-parameters simulation error for
different bias conditions, from optimization method.
In all, we proposed an 18-element equivalent circuit model
to determine the small signal parameters for AlGaN/GaN
HEFTs. We find that the differential gate resistances must be
included in the intrinsic part of the circuit to take into account
the current conduction through the gate diode. Different
extraction methods were examined including the conventional
cold-FET measurements and hot-FET varieties.
A hybrid extraction method, which combines the cold-FET
measurements to obtain parasitic capacitances and hot-FET
9
data to calculate parasitic resistances/inductances, is
developed and capable to give the highest accuracy with an
overall error of approximately 5% without any dependence on
the initial trial value. The model utilizes data taken at multiple
frequencies to extract the intrinsic parameters. Additionally,
non-negative values for all the elements are imposed for the
nonlinear optimization routine. The program searches the
optimized extrinsic resistances/inductances by minimizing the
weighted variances of the intrinsic parameters, with the
weighting factors determined from a normalization process.
The extrinsic inductances show a notable difference
between the different methods. We believe that the
inductances extracted from the conventional cold
measurements are not accurate enough under operating bias
conditions. The values obtained from the conventional cold
measurements should be thoroughly validated by other
extraction methods. Our hybrid optimization routine can
generate more reliable extrinsic and intrinsic values for the
small signal equivalent circuit for AlGaN/GaN HFETs.
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
ACKNOWLEDGMENT
This work has been funded by a grant from the Air Force
Office of Scientific Research under the direction of Drs. K.
Reinhardt and D. J. Silversmith.
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Qian Fan received his B.S and M.S degrees
from Information and Electronic Engineering
Department, Zhejiang University, Hangzhou,
China. In 2004, he entered the Electrical and
Computer Engineering Department in Virginia
Commonwealth University and now is working
toward the Ph.D degree.
His current research interests include
GaN-based device fabrication; structure growth
(by MOCVD); device characterizations and
modeling.
Jacob H. Leach (Student Member,
IEEE) received B.S degrees in physics and
electrical engineering with honors from
Virginia Commonwealth University in 2004.
He earned the M.S. degree, also from Virginia
Commonwealth University in electrical
engineering in 2007. His current research
interests are in high frequency and transient
responses of GaN-based devices and their
applications.
Hadis Morkoç received the B.S.E.E. and
M.S.E.E. degrees from Istanbul Technical
University, Istanbul, Turkey, and the Ph.D.
degree in electrical engineering from Cornell
University, Ithaca, NY.
From 1976 to 1978, he was with Varian
Associates, Palo Alto, CA, where he was
involved in various novel FET structures and
optical emitters based on then new
semiconductor heterostructures. He held
visiting positions at the AT&T Bell
Laboratories (1978–1979), the California
Institute of Technology, Pasadena, and Jet
Propulsion Laboratory (1987–1988), and the Air Force Research
Laboratories-Wright Patterson AFB as a University Resident Research
Professor (1995–1997). From 1978 to 1997, he was with the University of
Illinois, Urbana. In 1997, he joined the newly established School of
Engineering, Virginia Commonwealth University, Richmond. He and his
group members have been responsible for a number of advancements in
10
compound semiconductor, including wide-bandgap nitride, heterostructures,
and devices. He has been a prolific writer with a number of books, review and
tutorial papers, book chapters, and journal publications. He is among the most
cited in the fields of engineering, physics, and materials science.
Dr. Morkoç is a Fellow of the American Association for the Advancement
of Science, a Life Fellow of the American Physical Society, and was a Fellow
of the IEEE through 2008, a member of Sigma Pi Sigma and Eta Kappa Nu,
and a Life Member of Sigma Xi and Phi Kappa Phi. He is listed in Who’s Who
in America, Who’s Who in the Midwest, American Men and Women in Science,
Who’s Who in Engineering, and International Men of Achievement.