ELEC 4707
Assignment 2
Miller’s Theorem, Switched
Caps and much more…
Submitted by:
Michael Gordon
231617
Due Date: Friday, March 28, 2003
Question 1
1.
ii and Ri might represent the output stage of the previous circuit. Ri would represent the
output resistance of the previous stage, and ii would represent Norton’s equivalent source
of the previous stage.
2.
The derivation of equation (2) from reference [5].
Pole equal to 1/RC. The first pole sp1 is located on the left side of Figure 1a from [5]. R =
R1 and C = C1 + Ceq. Where Ceq is the Miller’s equivalent capacitance of CC. According to
Miller’s theorem, Ceq = (1-A)CC. For the circuit in Figure 1a, the gain A = -gmR2.
Putting it all together
s p1 =
1
R1 C1 + CC (1 + g m R2 ) 
The above is equivalent to equation (2) from [5].
3.
(4a), (4b), and (4c) have been derived using Maple:
The above expression for Vo is equivalent to (4a) after the grouping of some terms.
4.
Pole splitting is accomplished by adding a compensation or a Miller’s capacitor
connecting the output and the input of an amplifier. Due to the Miller’s effect, the added
feedback capacitor increases the capacitance seen in the input of the amplifier and thus
the input pole moves to a lower frequency. It also has the effect of moving the output pole
to a higher frequency. This has a stabilizing effect on the circuit as unity gain with a
higher phase margin.
The following conditions are required for pole-splitting:
• The input dominant pole will move lower in frequency
• The output pole will move higher in frequency
• Miller’s Theorem can only be applied if A(s) is high and does not depend on the
feedback capacitor CC (for the desired frequency range of operation)
5.
According to [5], the statement “a careless application of the Miller effect may give
inaccurate results” refers to the fact that A(s) must be independent of the feedback
capacitor CC. From the circuit A ( s ) =
Vo ( s )
Vi ( s )
=
− g m R2 (1 − sCC / g m )
1 + s ( C2 + CC ) R2
, which violates the
condition that A(s) must be independent of CC. At DC1 frequencies the expression for
gain A(s) is simplified to A(s) = -gmRL. According to this analysis, Miller’s theorem can
only be applied at DC frequencies.
6.
From the article itself “the initial pole of an uncompensated amplifier remains dominant
after compensation”. If the dominant pole was at the input node of the amplifier, the
compensated amplifier will have its dominant pole at the input as well. Due to Miller’s
capacitance, a higher capacitance will be seen at the input node, which given the
relations of sp1 = 1 / RC, will push the input node pole closer to DC. The output node pole
on the other hand will be pushed to a higher frequency, thus the term “pole-splitting”.
Question 2
1.
Looking at the bode plot in Figure 2.2 in the assignment paper, the poles for the transfer
functions are:
sp1 = 1 krad/s
sp2 = 10 krad/s
2.
The zeros for the transfer functions are:
sz1 = 10 rad/s
sz2 = 1 Mrad/s
1
DC refers to low frequencies which is a relative term. It would normally be frequencies lower
than the dominant pole or zero
3.
The DC gain of the transfer function is 1V/V or 0dB.
4.
The transfer function in the Laplace domain for two cascaded first order filters is:
T (s) = K
( s + z1 )( s + z2 )
( s + p1 )( s + p2 )
5.
The total transfer function broken down to a product of two bilinear transfer functions is:
T ( s ) = K1
( s + z1 ) K ( s + z2 )
( s + p1 ) 2 ( s + p2 )
For the particular circuit presented in the question with the given gain, zeros, and poles,
the corresponding transfer function becomes
( s + 10 )
T (s) =
( s + 1000 ) ( s + 10 )
( s + 10 )
6
4
The bilinear transfer function of a first order amplifier is T(s) = -Z2 / Z1
For the first filter
( s + 10 )
Z2
=−
Z1
( s + 1000 )
(
(
s + 106
Z4
For the second filter
=−
Z3
s + 104
)
)
Thus the total transfer function would be T ( s ) =
Z2 Z4
Z1 Z 3
6.
The bilinear transfer function -Z2 / Z1 is equivalent to the ratio of admittances -Y1 / Y2.
One configuration of R-C components that can be used to realize the required transfer
function is
R
C
The equivalent admittance of the above configuration is Y = sC + 1/R. This can be used
to implement the required transfer function of the form a*s + b.
For the first bilinear filter
( s + 10 )
Y1
=−
Y2
( s + 1000 )
Y1 = s +10. C = 1, R = 1/10
Using a scale factor of 109, C1 = 1nF, R1 = 100MΩ
Y2 = s +1000. C = 1, R = 1/1000
Using a scale factor of 109, C2 = 1nF, R2 = 1MΩ
(
(
s + 106
Y3
For the second bilinear filter
=−
Y4
s + 104
)
)
Y3 = s +106. C = 1, R = 1/106
Using a scale factor of 1010, C3 = 100pF, R3 = 10kΩ
Y4 = s +104. C = 1, R = 1/104
Using a scale factor of 1010, C4 = 100pF, R4 = 1MΩ
7.
The full circuit will all the components labelled. This circuit might be impractical to design
on chip because of the high required capacitance values of 1nF and high resistor values
of 100MΩ.
1M
R4
1M
R2
1nF
Vin
100M
R1
100pF
10k
R3
C2
1nF
100pF
C1
C3
C4
Vout
The above circuit implements the required transfer function
( s + 10 )
T (s) =
( s + 1000 ) ( s + 10 )
( s + 10 )
6
4
8.
The implemented filter is a band-pass filter. The 3dB pass band from 1krad to 10krad/s is
amplified by 40dB, while all other frequencies experience 0dB amplification.
9.
There are two poles and two zeros in the transfer function. Mathematically it does not
matter how the poles and zeros are paired up and what the order of the bilinear filters is.
From a practical circuit design point of view, there is a difference however. It is best to
keep each pair of poles and zeros as close to each other as possible. This will limit the
amount of attenuation or amplification each stage experiences individually. Choosing the
pairing of the poles and the zeros and the bilinear filter order will affect the noise
characteristics of the circuit (high frequency noise or low frequency noise), and the
sensitivity of the circuit (noise floor sensitivity or compression point sensitivity).
10.
Since the R-C configuration chosen in part 6 is parallel in nature, switched capacitors can
be implemented because there will still be a feedback path through the fixed capacitors.
For a switched capacitor R = 1 / (fc · C), and thus C = 1 / (fc · R)
The switched-cap circuit which is equivalent to a resistor is
NMOS
C
NMOS
clkNOT
clk
The clocks are alternating and must not be overlapping.
The equivalent capacitance values for a 10MHz switching clock are:
Cs1 = 1 / 1 / (fc · 100MΩ) = 1fF
Cs2 = 1 / 1 / (fc · 1MΩ) = 100fF
Cs3 = 1 / 1 / (fc · 10kΩ) = 10pF
Cs4 = 1 / 1 / (fc · 1MΩ) = 100fF
Using switched capacitors improves the viability of the circuit since implementing a 100fF
capacitor is easier than implementing a 1MΩ resistor on chip. Furthermore the ratio of
Cs1/C1 is what determines the pole location, and ratio of capacitors can be controlled
much better on chip than absolute capacitance or resistance values. Still, implementing a
1fF capacitor might still be very hard because of the small value.
Question 3
A cascode current mirror is analyzed in this question with the following configuration
virtual
ground
If the AC component of the input current iin is 0, then the gates of the MOSFETs can be
approximated to be at virtual AC ground. The small signal model is shown on the next page.
Iout
Gate4
Vsg4gm4
Ro4
Gate2
Vgs2gm2
Ro2
Since both gates are at virtual grounds, Vgs2 is 0 and that current source is cancelled. Let a test
voltage Vout be applied at the output node. Let Vx denote the voltage at the middle node. The
following KCL equations can be derived:
iout + vx g m 4 = ( vout − vx ) / ro 4
( vout − vx ) / ro 4 = vx g m 4 + vx / ro 2
From the previous two equations and from analyzing the circuit vx = iout ro 2
Rout =
Equation (8) from [6] is CMRR =
vout
= ro 4 + ro 4 ro 2 g m 4 + ro 2
iout
2 RT g mi g ml
goi + g ol
RT, the resistance of the current sink is the only parameter concerning us.
The output resistance of the cascode current mirror can be rewritten if we let ro4 = ro2 and gm4 = gm
Rout = 2ro + ro 2 g m
The output resistance of a simple current mirror is just ro.
CMRRcascode RT ,cascode 2ro + ro 2 g m
=
=
CMRRsimple
RT , simple
ro
Assuming rogm >> 2
CMRRcascode
≈ ro g m
CMRRsimple
The improvement of the CMRR for a cascode current mirror over a simple current mirror is a
factor of rogm which is a very significant improvement. (can be a factor of 1000 or so)