Jonathan Roderick
Hakan Durmus
Scott Kilpatrick Burgess
Experiment #10
BJT Dynamic Circuits II
Introduction:
In the last lab, it was demonstrated that correctly biasing a BJT, a normally non-linear device, would allow you as a
circuit designer to model it as a linear element using the small signal model. Then, three different canonic cells of
the BJT were introduced, each configuration having its own different and specific small signal function. The
common-emitter, common-collector (a.k.a. emitter follower), and common-base BJT configurations were each
introduced and explored. The gain, input resistance, and output resistance were all easily found using the small
signal model with the right approximations. It was then concluded that these canonic cells have some limitations in
specific applications. In some cases, undesirable small or large resistance occurred in the input or output of these
cells. The limitations of these canonic cells can be improved by implementing more circuitry or combining canonic
cells in a certain way to capitalize on capturing the desired characteristics.
This experiment will introduce and explore two stage cells, two canonic cells connected together. Even though we
are making topologies larger, thus increasing the static power consumption, these two stage canonic cells will fulfill
performance standards where single canonic cells fall short. It should be noted that canonic cells are not usually
used alone in circuits, yet they are very important from an analysis point of view. Canonic cells are very useful for
analysis when dealing with complicated circuit topologies. By breaking complicated circuits down in to single
canonic cells, a very lengthy and exhausting analysis of a complicated topology may be avoided. By realizing what
each canonic cell contributes to the circuit, an analysis of a complicated architecture may be done virtually by
inspection.
Theory:
A common configuration in BJT technology is the Darlington configuration seen in figure 10.1. The Darlington
configuration is used to improve the input and/or output resistance and/or gain restrictions of single canonic cell BJT
amplifiers.
+Vcc
+Vcc
Rl
Rs
Voc
Q1
Q2
Vs
Ibias
Voe
Ree
-Vee
-Vee
Figure 10.1 A Darlington configuration.
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It should be noted: the current source, Ibias, shown in figure 10.1 could be a resistor that is generating the current Ibias .
However, a designer must make the resistance sufficiently large to avoid affecting the large driving point input
resistance that the Darlington provides. Since a large resistance usually doesn’t produce realistic biasing currents,
the current source, Ibias, is usually an active current sink.
The Darlington output can be taken from two different spots, each having a specific and different purpose. The first
output taken into consideration is the one at the collector of transistor Q2 (Voc ); this is shown in figure 10.2. This
makes the Darlington configuration a common collector common emitter amplifier.
+Vcc
+Vcc
rin
Rl
Voc
Rs
Q1
rout
Q2
Vs
Ibias
Ree
-Vee
-Vee
Figure 10.2 A common collector common emitter Darlington configuration.
It has all the advantages of a normal common emitter amplifier, but this two-stage configuration achieves a larger
input resistance than what is realized with a single common-emitter amplifier. The input resistance of a single
common-emitter canonic cell was shown in the last lab to be
rin = rb + rπ + ( β + 1)( re + rx )
(10.1)
Using what was learn in the previous labs about calculating input and output resistance, while ignoring Early effects,
it can be shown that the input resistance of the Darlington common collector common emitter amplifier is
rin = rb + rπ + ( β + 1){ re + [ rb + rπ + ( β + 1)( re + Ree )]}
2
(10.2)
Equation 10.2 shows that the input resistance of the Darlington connection can be considerably larger than the input
resistance of a single common emitter amplifier. Thus the Darlington configuration is a more ideal voltage amplifier
than the single common emitter canonic cell.
A second purpose of the Darlington configuration can be used by taking the output at the emitter of Q2 (Voe), seen in
figure 10.3. This Darlington configuration is nothing more than a common collector common collector amplifier. In
a sense, it is nothing more than a single common-collector, since the gain is still around 1 and it acts as a voltage
buffer. However, it has some improvements when it comes to input and output resistance.
+Vcc
+Vcc
rin
Rl
Rs
Q1
Q2
Vs
rout
Voe
Ibias
Ree
-Vee
-Vee
Figure 10.3 A common collector common collector amplifier.
Just as in the previous Darlington configuration (common collector common emitter amplifier) the input resistance
is larger and it can be found equivalent to equation 10.2. The output resistance (seen in equation 10.3) also has an
advantage, it can be found to virtually be independent of the source resistance, which was not the case in the single
common-collector amplifier. Due to the inherent large β of a BJT transistor, the dependence of the output resistance
on the source resistance, seen at the input of the topology, is negligible.
rout
rb + rπ + r y

rb + rπ +  re +
( β + 1)

= re +
( β + 1)
3



(10.3)
Another useful combination:
Another useful topology that is a combination of two canonic cells is the common emitter common base, seen in
figure 10.4. There are two basic advantages to this configuration. First, the output resistance is very high. Second,
it limits the Miller effect that is a common problem in the common emitter configuration. The latter is achieved by
making the node at the collector of Q1 low impedance with the connection of the low impedance emitter from Q2 .
The input resistance, output resistance, and gain derivations are left as an exercise in the pre-lab.
Q2
Vbias
rin
Vo
rout
Rs
Q1
Ree
Vs
.
Figure 10.4 Common emitter common base amplifier.
Conclusion:
The most important point that should be captured from this lab is not the understanding of topologies themselves
(i.e. Dalrington configuration). The most important lesson deals with overcoming the limitations of single canonic
overcome by utilizing more than one in a design. To be sure, a circuit designer is not limited to topologies that are a
combination of just two canonic cells, which were shown and discussed in this lab. There is no limit to the number
of canonic cells that a circuit designer may use in order to meet their system design requirements. However, the
more canonic cells in a design, the larger the power consumption, so one must find a reasonable tradeoff when
dealing with power limitations.
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Reference Reading
1)
John Choma, Jr. EE348 lecture notes. University of Southern California. Spring 2001.
2)
David Johns & Ken Martin. Analog integrated Circuit Design. John Wiley & Sons, Inc., New York, 1997.
3)
Paul R. Gray & Robert G. Meyer. Analysis and Design of Analog Integrated Circuits. John Wiley & Sons,
Inc., New York, 1993.
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Pre-lab
1)
Using the small signal model, ignoring Early effects, derive the gain, input resistance and
output resistance of the common-collector common-emitter Darlington configuration. Are these
results what you expected? Do you get the same results combining the canonic cell results
found in experiment #9?
2)
Using the canonic cells in experiment #9, find the input resistance, output resistance, and the
transconductance of the common-emitter common-base configuration seen in figure 10.4.
3)
Using the canonic cell results, ignoring Early effects, derive the gain, input resistance and
output resistance of a common-emitter common-collector (emitter follower) amplifier.
Compare the results you find to the gain, input resistance, and output resistance of a single
common emitter canonic cell. Do you see any advantages one has over the other? Will you run
into any potential problems if you just use a common emitter amplifier, rather than the common
emitter common collector amplifier (Hint: Load size?).
4)
Building upon the example in experiment #8 (figure 8.5), determine all the resistance values
that will correctly bias a common-collector common-emitter amplifier. Correctly bias each one
individually, and then connect the two using a coupling capacitor. The coupling capacitor
should be large enough where it will let a signal pass, but acts like an open circuit for dc biasing
conditions. Your design should have a gain magnitude of 5 and drive a resistance of 200Ω.
Using a 3kHz 100mV sin wave, verify your design works in Spice.
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Lab procedure
In this lab, we will be designing a two-stage amplifier by combing everything learned for the last three labs. The
first stage provides the large input resistance and the second provides the gain. We will be using 5 transistors in the
final circuit. The questions are in an order to take you through the design, so please don’t remove your circuits after
each stage is done.
1.
Build the current source in Figure 10.5 for a current output of 1 to 1.5mA. Note that the supply
voltages for this circuit is GND and Vcc =-5V. To have a large voltage swing at the collector of Q1 (for
later use), a good design approach is to choose the base voltage of Q1 as -4V.
Rc1
Io
Q1
Q2
RE1
R E2
-V ee
-Vee
Figure 10.5
2.
Build the two circuits in Figure 10.6a and 10.6b. Note that the voltage supplies are now Vcc=5V and
Vee = -5V (but the current mirror should keep its previous sources in Figure 1!). For Figure 10.6a let R
be 500. Apply a 1 V sinusoid input to the circuits. Which of the input resistance do you think is larger?
Why? Is there a significant difference between these values, why/why not?
+Vcc
Q3
Vo
Vs
RE2
-Vee
Figure 10.6 (a) Emitter follower with resistive biasing
7
Vcc
Q3
Vs
Vo
Rc1
Q1
Q2
Re1
Re2
-Vee
-V ee
Figure 10.6 (b) Emitter follower biased with current sink.
3.
Build the common emitter circuit shown in Figure 10.7 for a gain of 3. Keep the collector current of
the device around 1mA. It is a nice idea to keep the base voltage of Q3 around 2V. Use a large
capacitor Cc. To obtain a large input resistance choose Rq4 around 10 times larger than Re4. Measure
the gain of the circuit.
+Vcc
+Vcc
Rc4
Rq2
Vo
Cc
Q4
Vs
Rq1
-Vee
Figure 10.7 Common emitter amplifier.
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Re4
-Vee
4.
Join the circuits in figure10.6b and figure 10.7 as shown in figure 10.8. Measure the gain and the input
ac current. Compare your gain result with part 3 and ac input current result with part 2. Explain the
differences if any in your report.
V cc
Vcc
Vcc
Q3
Vs
R q2
Rc4
Vo
Cc
Rc1
Q1
Re1
Q2
R q1
R e4
R e2
Figure 10.8
5.
Now try to drive a 200O load with the circuit you have built so far (figure 10.8), make sure you use a
large coupling capacitor so you don’t disturb the biasing. What happens to the gain when you try and
drive a small load? Use what you have learned in the last three labs to modify figure 10.8 to drive a
200O load. Demonstrate that your design works. Your lab write up should include a complete
schematic of your new topology as well as its measured dc and ac performance.
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