LECTURE SUPPLEMENT #07
Canonic Cells of Analog Bipolar
Junction Transistor Technology
Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 90089–0271
213–740–4692 [USC Office]
213–740–7581 [USC Fax]
johnc@usc.edu
PRELUDE:
In this set of notes, we supplement our earlier analog MOS technology circuit disclosures
with analogous considerations of bipolar junction transistor (BJT) circuits. As in the
case of Lecture Supplement #06, we shall confine our investigations to linear amplifiers
that are generally operated at relatively low frequencies, for which the fundamentally
important properties remain input to output (I/O) gain, input resistance, and output resistance. We shall witness that many of the arguments and observations proffered here are
analogous to those invoked in the course of considering analog MOSFET circuit technology. For example, we shall confirm that the bipolar common emitter amplifier projects
properties that largely mirror those of the MOSFET common source amplifier, the bipolar emitter follower displays electrical properties that are akin to those of the MOSFET
source follower, the bipolar common base circuit is closely related to its MOSFET common gate counterpart, and so forth. We shall see that while the BJT boasts certain analog performance advantages over a comparably sized MOSFET, the basic circuit concepts and properties surrounding both device technologies are virtually identical.
December 2010/January 2011
Lecture Supplement #06
Canonic Analog MOS Cells
J. Choma
7.1.0. INTRODUCTION
As in the case of MOSFET technologies, the vast majority of analog bipolar junction
transistor (BJT) networks are interconnections of only three basic circuit cells. These canonic
architectures are the common emitter amplifier, the common collector amplifier, which is also
known as the emitter follower, and the common base amplifier. In the common emitter amplifier, the input signal earmarked for processing is applied with respect to circuit ground at the
transistor base terminal, while the output response to this applied signal is extracted as either a
signal current flowing in the collector lead or a signal voltage developed at the collector port
with respect to ground. The common emitter stage features a moderately large input resistance
and is therefore suitable for input signals applied as voltage sources. It offers a high output resistance, thereby implying that the signal response to an applied excitation is best extracted as a
current. It follows that the common emitter stage is effectively a transconductance amplifier, or
simply, a transconductor. The fact that the common emitter amplifier is optimally suited as a
transconductor does not mean that it cannot function as a voltage amplifier. Rather, it means
that because of its high output resistance, the small signal voltage gain, which is the ratio of output signal voltage -to- input signal voltage, is unavoidably dependent on the terminating load
resistance. Thus, the common emitter amplifier has limited, general purpose utility as a voltage
amplifier. Like its common source cousin, the common emitter amplifier manifests a low frequency output voltage response that is 180° out of phase with its applied input signal.
In the common collector amplifier, or emitter follower, the input signal is applied as a
voltage with respect to ground at the base terminal, while the resultant output response is a signal
voltage developed with respect to ground at the emitter terminal. The emitter follower functions
as a voltage buffer in that its input resistance is large, while its output resistance is low. The
emitter follower more closely reflects an idealized voltage buffer than does the MOSFET source
follower in that its I/O voltage gain is generally closer to one, at least at low frequencies, and its
output resistance is generally smaller. Like the source follower and in contrast to the common
emitter stage, the emitter follower offers no I/O phase inversion. This is to say that the emitter
voltage signal “follows” the base in that as the signal at the base rises (decreases), so does the
emitter terminal signal response rise (decrease) with this applied signal. Because of the slightly
less than unity voltage gain afforded by the emitter follower, it is seldom used as a standalone
amplifier. Instead, and as we shall demonstrate, the emitter follower behaves as a traditional
buffer that transforms a large source resistance to a significantly smaller output resistance,
thereby enabling the amplifier output port to drive a small load resistance or even a relatively
large capacitance excited by moderately high frequencies.
The input port of the common base amplifier is formed by circuit ground and the emitter terminal of the utilized BJT, while its output port is the collector terminal. Because the common base amplifier features a small input resistance and typically, a very large output resistance,
the input signal is generally applied as a current, and the output response is logically extracted as
a signal current. The I/O current gain presents no phase inversion to the network in which the
stage is embedded and is always less than, but generally very close to, one. In effect, the common base amplifier is the dual of the emitter follower. Recall that the emitter follower establishes high input resistance, low output resistance, and a voltage gain that approaches one. In
contrast, the common base configuration boasts moderately low input resistance, very high output resistance, and a signal current gain that tends toward unity. Because of these properties, the
common base amplifier can be thought of as a current buffer. Like the emitter follower, the
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common base amplifier most commonly appears in conjunction with a common emitter amplifier
in electronic systems for which the incorporated common emitter stage is asked to supply
substantial I/O transconductance to a relatively high resistance load.
Table (7.1) summarizes the foregoing generalizations by itemizing the basic low frequency properties of the three fundamental analog circuit cells of BJT technology. Interconnections of these three basic topologies, or simple variants of them, comprise better than 90% of the
analog BJT circuits that prevail in commercial, military, or space system applications.
Amplifier
Input
Resistance
Output
Resistance
I/O Phase
Inversion
Functional
Operation
Common
Emitter
High
High
Yes
Common
Collector
Common
Base
High
Low
No
Low
Very High
No
Transconductor;
Voltage
Amplifier
Voltage
Buffer
Current
Buffer
Table (7.1).
Summary of performance characteristics for the three basic circuit cells of analog BJT technology.
7.2.0. TRANSISTOR MODEL AND CIRCUIT ANALYSIS
Before embarking on our analog BJT circuit expedition, prudence dictates a review of
the small signal BJT model that we shall use to investigate the low frequency I/O properties of
several nominally linear active networks[1]. As a precursor to addressing the model, Figure
(7.1a) is submitted to display the circuit schematic symbol for an NPN bipolar device, while Figure (7.1b) is the corresponding circuit symbol for its PNP counterpart. Both of these figures
identify three static (or “DC” or “quiescent”) transistor currents whose indicated directional flow
pertains to a transistor biased in the active regime where linear processing of its applied input
signal is encouraged. These currents, whose indicated directional sense is independent of the
circuit architecture in which the transistor is embedded, are the collector current (Ic), the base
current (Ib), and the emitter current (Ie). Obviously, all three device currents are not independent
variables in that the currents must subscribe to Kirchhoff’s current law (KCL); specifically
Collector (C)
+
Vcb
−
Base (B)
+
Vbe
−
Emitter (E)
Ic
Ib
Emitter (E)
+
Vce
Ie
Base (B)
−
Collector (C)
(a).
+
Veb
−
Ie
Ib
+
Vec
+
Vbc
−
Ic
−
(b).
Figure (7.1). (a). Schematic diagram of an NPN bipolar junction transistor (BJT). The positive sense
of relevant voltages and currents manifested in the active regime are shown. (b). Schematic diagram of a PNP BJT. The positive sense of relevant voltages and currents
manifested in the active regime are shown.
I
e
= I +I .
c
(7-1)
b
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Clearly, a numerical awareness of any two of these three BJT currents stipulates the third current. Moreover, the collector and base currents are intertwined by the static current gain, hFE, in
accordance with
I
(7-2)
h
= c .
FE
I
b
In the active regime, hFE, which is known as the static common emitter gain, or DC beta, is a
dimensionless, positive number that is of the order of the high tens -to- low hundreds for conventional bipolar transistors. It should be noted that for silicon-germanium (SiGe) heterostructure
BJTs, hFE is typically of the order of a few -to- several hundred. It follows that with hFE large,
the base current in the active regime is considerably smaller than is the collector current. The
same comparison can be drawn between the emitter and base currents in that (7-2) and (7-1)
combine to deliver
I
e
= I +I
c
b
=
( hFE + 1) Ib .
(7-3)
Equations (7-2) and (7-3) compel
⎛ h
⎞
I = h I = ⎜ FE ⎟ I = α I ,
c
FE b
FE e
⎜ h +1⎟ e
⎝ FE
⎠
where
h
FE ,
α FE h +1
(7-4)
(7-5)
FE
which is commonly referenced as the static common base current gain, is nearly one owing to
large hFE. Thus, small base currents promote, in accordance with (7-4) and (7-5), a virtual identity between the emitter and collector currents when the transistor is biased to support nominally
linear I/O signal processing.
For the NPN transistor in Figure (7.1a), the voltages required to sustain the
aforementioned three transistor currents are the static base-emitter voltage, Vbe, and the static
collector-emitter voltage, Vce. More than merely sustaining these three currents in the polarity
directions delineated in Figure (7.1), biasing in support of nominally linear I/O signal processing
requires that Vbe be at least as large (but not very much larger) as the base-emitter junction turnon voltage, Vbeon. Voltage Vbeon is of the order of 700 or so millivolts (mV) for conventional
transistors and 800 mV or slightly larger for SiGe devices. Additionally, operation in the active
regime mandates that Vce be at least as large as Vbe. In short, an NPN BJT operates in its linear
regime if
V ≥ V
be
beon
(7-6)
.
V ≥ V
ce
be
Note that for Vce ≥ Vbe, the resultant collector-base voltage, Vcb, which is (Vce – Vbe), is at least
zero, thereby assuring zero or reverse biasing of the collector-base junction. For the PNP device
in Figure (7.1b), the equivalent active regime relationship to (7-6) is the constraint,
V ≥ V
eb
ebon
(7-7)
,
V ≥ V
ec
eb
where Vebon is the base-emitter junction turn-on voltage (about 700 mV), and Vec is the required
emitter-collector voltage. Similar to the NPN requirement of Vce > Vbe, Vec must be at least as
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large as Veb to foster PNP biasing in the active domain. Unless expressly stated otherwise, all
transistors encountered in the networks considered in this document are presumed biased in their
active regimes.
7.2.1. SMALL SIGNAL MODEL
When sufficiently small input signals are applied to a network that exploits BJTs biased
in their active regime, the equivalent transistor circuit underpinning network analysis is either of
the two structures offered in Figure (7.2). The small signal model in Figure (7.2a) uses a current
controlled current source (CCCS), βacI, across the collector-emitter port, where I is understood to
be the component of base current produced exclusively by the applied input signal; that is, I is
the signal component of the net base current. If ib denotes the net instantaneous base current at
any time subsequent to activating an input signal,
rb
rb
(B)
(C)
+ I
rπ
V
−
βac I
(B)
ro
(C)
+ I
rπ
V
gmV
ro
−
(E)
(E)
(a).
(b).
Figure (7.2). (a). Small signal model for either an NPN or a PNP BJT biased in its active regime.
The model features a current controlled current source (CCCS) at its collector-emitter port. (b). Alternative to the model of (a) in which a voltage controlled current
source (VCCS) is used at the collector-emitter port.
i
b
= I +I .
(7-8)
b
where Ib is the static, or quiescent, value of the base current. To the extent that the transistor
operates in a reasonably linear fashion, I is directly proportional to the input signal and, as is projected by (7-8), it superimposes with the static component of this base current. The parameter,
βac, in the model of Figure (7.2a) is called the small signal current gain, or simply, the small
signal beta of the transistor. This parameter is seen in Figure (7.2a) as a measure of the degree
to which the signal base current of the device couples to the collector circuit. It is therefore a
measure of the input -to- output gain that can be achieved with a BJT. Since large forward gain
requires commensurately large βac, the good news is that βac is proportional to the static current
gain, hFE, and is therefore a reasonably large number. But the bad news is that hFE, displays variances of up to 3 -to- 1 because of routine manufacturing tolerances. This uncertainty in hFE, and
thus in βac, derives from the inverse dependence of hFE on base width, whose typical submicron
dimension proves difficult to control during monolithic processing. The design lesson to be
learned from this engineering reality is that critically important measures of network I/O
performance must never be couched as a direct, non-adjustable proportion to βac. We shall learn
that judiciously applied feedback or, in the case of mixed signal electronics, appropriately implemented digital controllers, brought into play on a BJT network mitigates most of the deleterious
effects of βac uncertainties.
In Figure (7.2b), we see that the CCCS, βacI, in Figure (7.2a) appears to have been supplanted by a presumably equivalent voltage controlled current source (VCCS), gmV, where gm is
referred to as the forward transconductance, or simply transconductance of the BJT. Note that
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voltage V is the small signal voltage developed across resistance rπ in the directed polarity of
base -to- emitter. Since rπ conducts the signal base current, I, V is obviously rπ I, and as a result,
(7-9)
g V = g r I .
m
mπ
By comparison of the model at hand with that of the structure in Figure (7.1a), we conclude that
(7-10)
β ac ≡ g m rπ .
The small signal base-emitter junction resistance, rπ, is given approximately by
h n V
FE f T
,
r ≈
(7-11)
π
I
c
where nf is a junction injection coefficient that is very slightly larger than one, VT is the
Boltzmann voltage (≈ 26 mV at a junction temperature of 27 °C, or 300 °K), and Ic, of course,
represents the quiescent collector current conducted by the subject transistor in its active domain.
Note that rπ, like βac, is sensitive to the numerically unreliable static gain, hFE. In addition, rπ,
which typically assumes values in the range of a few thousand ohms, is inversely proportional to
the quiescent collector current. This current dependence logically promotes a need to design
BJT biasing subcircuits that promote nominally constant base-emitter junction resistance in the
face of junction temperature changes, poor power line regulation, and other environmental factors.
Since both βac and rπ are influenced strongly by parameter hFE, we expect, from (7-10)
that transconductance gm is unaffected by the tolerances implicit to hFE. This expectation is confirmed by the first order transconductance expression,
I
c .
(7-12)
g ≈
m
n V
f T
Like βac, gm, which is proportional to parameter βac, is a measure of the forward gain attainable
in a BJT. It is interesting that the BJT transconductance is nominally proportional to collector
biasing current, whereas in a MOSFET, the transconductance is proportional to the square root of
drain biasing current. Equation (7-12) therefore confirms that for a given biasing level, a BJT is
likely to deliver more forward gain than can a comparably sized and comparably biased
MOSFET. If the gain of a bipolar network is rendered proportional to gm, (7-12) suggests that a
temperature invariant gain requires a quiescent collector current designed to be proportional to
absolute junction temperature. In view of the direct dependence of the Boltzmann voltage on
absolute temperature, a collector current that is proportional to absolute temperature produces the
desirable result of a temperature invariant transconductance in (7-12). This sensible biasing approach is commonly referenced as a PTAT (Proportional To Absolute Temperature) strategy.
Observe in (7-11) that a PTAT quiescent collector current also establishes a temperature-invariant rπ.
Continuing with a discussion of the BJT models in Figure (7.2), ro is the Early resistance . It is linearly dependent on the Early voltage, which can be as large as at least the mid
tens of volts, and it is inversely proportional to the quiescent collector current. Typically, ro,
whose presence as a shunting element across the collector and emitter terminals renders the
CCCS and VCCS in the two subject models non-ideal current sources, is of the order of a few
tens of kilo-ohms. Unless extremely small geometry transistors are utilized, ro is generally sufficiently large to warrant its tacit neglect in many linear active networks.
[2]
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Finally, rb in the BJT models denotes the intrinsic base resistance. This resistance is
inversely dependent on the base-emitter junction cross section area, which infers potentially
large base resistance in minimal geometry transistors. The resistance is also somewhat dependent on transistor bias currents because of emitter crowding phenomena[3]-[4]. However, we generally ignore this current dependence by adopting the worst-case posture of setting rb to its maximum anticipated value. Maximal base resistance is viewed as the worst-case option for several
reasons. First, large rb reduces the available forward gain of a transistor circuit. A second reason
is that large base resistance exacerbates the electrical noise characteristics of the transistor,
thereby curtailing reliable detection of very small input signals. Yet another reason is that large
rb limits the maximum possible frequency at which greater than unity power gain is achievable
by the utilized transistor. Generally, the frequency at which the I/O signal power gain degrades
to unity (or 0 dB) is interpreted as the maximum practical frequency at which the subject transistor can operate productively.
Before proceeding to the amplifier analyses tasks lying before us, it is crucial to understand that the models appearing in Figure (7.2) are valid small signal equivalent circuits for both
NPN and PNP transistors. In an attempt to underscore this vital point, be aware that there are no
such things as a small signal NPN model and a small signal PNP model; there is only a BJT
small signal model. This assertion reflects the fact that the small signal components of transistor
currents in a small signal model are merely small electrical perturbations about respective quiescent operating points. These perturbations can be positive or negative, depending on the nature
of the applied input signal and the dynamics implicit to the architecture of the considered active
circuit. For example, it is perfectly fine if the small signal collector current flows out of the
collector of an NPN transistor, as long as the net collector current (quiescent plus small signal
components) continues to flow into the collector terminal. Thus, for either an NPN or a PNP device, the dependent source, βacI or gmV, is always directed from the collector -to- the emitter. It
is to be understood that the controlling current, I, in the βacI generator is always the small signal
current directed to flow into the base, regardless of the nature of the transistor. Moreover, the
controlling voltage, V, in the gmV generator is always the voltage dropped across resistance rπ
with a polarity that elevates the base side of rπ to a higher potential than that of the emitter side,
as shown in Figure (7.2b).
7.2.2. CIRCUIT ANALYSIS TACK
In the pages that follow, we shall study the I/O characteristics of the three canonic cells
of bipolar junction transistor technology. We shall also assess the performance of traditional
interconnections of these cells, as well as commonly encountered variants thereof. The attention
given herewith is limited to low frequency considerations, which is to say that the high frequency
effects of base-emitter junction, base-collector junction, and collector-substrate capacitances are
tacitly ignored except in a few cases where their appropriate consideration invigorates an otherwise moot point. Although the purist can argue that the neglect of device capacitances is potentially too much of an analytical simplification, the pragmatist can counter by assuring that proper
low frequency operation is a necessary (but admittedly not sufficient) condition for achieving
successful high frequency circuit performance. Moreover, the analytical tasks pursued in the
succeeding sections of material are not merely directed toward cataloguing a list of accurate
mathematical expressions for the performance metrics of the various canonic cells of bipolar
technology. To be sure, such a compilation is useful and important. But equally important is the
development of computationally efficient analytical skills that inspire an insightful understanding
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of both the attributes and the limitations of considered network topologies. Such insights can
support the expedient development of analytical procedures for assessing unfamiliar circuits or
networks that simply challenge their bookmarking as a conventional member of a canonic family.
In the process of studying a variety of bipolar networks, we shall come to realize that at
least four small signal I/O gains can be evaluated. The most common of these gains is arguably
the voltage gain. The voltage gain is a particularly meaningful I/O metric when the input port of
the considered amplifier presents a high input resistance to the signal source, and the output port
establishes a low output resistance for the load termination. In such circumstances, most of the
signal source voltage appears directly across the amplifier input port, while most of the signal
voltage response developed at the output port is transmitted directly to the load. We shall learn
that the emitter follower is a good example of a voltage amplifier. Whenever a low output resistance prevails, as it does in a high quality voltage amplifier, it is both natural and appropriate to
represent the output port by a Thévenin (voltage type) equivalent circuit.
A second type of amplifier that features low output resistance is the transresistance
cell, which converts an applied input current to an output voltage response. Accordingly, the
gain metric in a transresistance amplifier is the I/O transresistance ratio of output voltage response -to- applied input current. In contrast to the voltage amplifier, the input resistance to a
transresistance (transimpedance) amplifier must be small so that most of applied signal current
is manifested as an actual input current to the amplifier. Since the output response remains a
voltage, the output resistance is desirably small to facilitate voltage delivery to a broad variety of
load terminations.
The transconductance (transadmittance) amplifier exploits high input resistance and
high output resistance to convert an applied input voltage to an output port current response. The
common emitter amplifier functions well as a transconductance unit. Because the output port of
a transconductor features a high output resistance, it is expedient to represent the output port as a
Norton equivalent circuit.
Finally, the current amplifier, like the transconductance cell, boasts high output resistance so that the current response generated at the output port is all but completely delivered to
the load termination. But unlike the transconductor, the current amplifier features low input
resistance. The common base cell exemplifies a practical current amplifier.
7.3.0. COMMON EMITTER AMPLIFIER
Figure (7.3a) depicts the basic schematic diagram of a common emitter amplifier realized with a single NPN BJT, while Figure (7.3b) is the PNP alternative to this NPN configuration. In the discussion that follows, we shall focus analytically on only the NPN circuit. Similar
investigations executed on the PNP circuit confirm that over a frequency passband for which
transistor capacitances can be ignored, the gain, input resistance, output resistance, and related
other performance metrics for the PNP stage are identical in form to their corresponding circuit
performance expressions deduced below for the NPN topology.
We see in Figure (7.1a) that the common emitter amplifier utilizes two circuit resistances, Rl and Ree. The third resistance, Rs, should not be counted as a circuit element because
this resistance represents the internal Thévenin resistance of the signal source, Vs, whose voltage
is to be amplified by the subject analog cell. Resistance Rl, to which we shall refer as the
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collector load resistance, influences the biasing of the transistor, as well as the achievable voltage gain. Resistance Ree, which is termed an emitter degeneration resistance, also influences
both biasing and gain. The circuit can be realized with Ree = 0; that is, the emitter terminal of the
transistor can be connected directly to circuit ground. But in the configuration depicted in Figure
(7.3a), nonzero Ree serves to reduce the sensitivity of the voltage gain to certain transistor
parameters, and especially βac. This attribute is an important design issue for the precise numerical values of key transistor parameters are typically elusive because of either their somewhat
nebulous physical nature or the routine manufacturing tolerances pervasive of semiconductor
device and circuit processing. Among the prices paid for this laudable performance desensitization with respect to transistor parameters is a reduction (hence, the “degeneration” descriptive) of
the effective forward transconductance achieved by the circuit. The electrical noise performance
of the common emitter stage also suffers somewhat from the incorporation of an emitter
degeneration resistance.
+Vcc
+Vcc
Rl
Ree
Vo
Route
Rs
Rs
Vi
+
+
Vs
Vs
−
+
Vbb
Rine
Vi
Route
Vo
Rine
−
Ree
Rl
−
Vbb
−
(a).
+
(b).
Figure (7.3). (a). Basic circuit schematic diagram of a common emitter amplifier utilizing an NPN
bipolar junction transistor. (b). Basic circuit schematic diagram of a common emitter
amplifier utilizing a PNP BJT. In both diagrams, Rine and Route respectively symbolize
the common emitter driving point input and output resistances.
7.3.1. ANALYTICAL STRATEGY
Assuming that the biasing forged by the power supply voltages, Vcc and Vbb, ensure active regime transistor operation for all values of the applied input signal voltage, Vs, the small
signal equivalent circuit of either form of common emitter amplifier depicted in Figure (7.3) is
the network drawn in Figure (7.4). In the process of deducing this model, the power supply voltages in the schematic diagrams of Figure (7.3) are grounded. This action does not infer a tacit
neglect of these static supply line voltages. Rather, the action exploits the fact that the small signal, or signal-induced voltage changes, ΔVcc and ΔVbb, of these respective voltages are zero in
that Vcc and Vbb are presumably constant, time-invariant voltages. Moreover it is tacitly presumed that Vcc and Vbb behave nominally as ideal voltage sources, which is to say that their internal Thévenin impedances assume idealistic zero values. If these Thévenin impedances are not
negligible, the batteries or power lines supplying voltages Vcc and Vbb, must be replaced by their
respective source impedances.
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Rs
Vis
+
Vs
−
Rine
J. Choma
rb
+ I
rπ
V
−
Vos
βac I
Rl
ro
Route
Ree
Figure (7.4). Small signal model of either of the two common emitter amplifiers
depicted in Figure (7.3). The current controlled current source form,
as opposed to the voltage controlled current source topology, is
arbitrarily selected in this exercise. The transistors in Figure (7.3) are
presumed to operate in their active regimes for all values of the signal
source voltage, Vs.
In the interest of analytical clarity, we have replaced the indicated output voltage, Vo, in
Figure (7.3) by voltage Vos in the small signal model, where it is understood that Vos symbolizes
the small signal component of the net output voltage. In other words, Vo in Figure (7.3) is
V = V +V ,
(7-13)
o
oQ
os
which suggests that the signal component, Vos, of the output voltage is little more than a change
(positive or negative) about the quiescent output voltage, VoQ, established by the biasing subcircuit. In addition to this suggestion, another fundamental concept surfaces with respect to the
equivalent circuit in Figure (7.4). In particular, since this equivalent circuit delineates only node
and branch signal voltage and branch signal currents, the model is incapable of generating any
engineering information concerning either quiescent or net voltages and currents. Indeed, a
prerequisite governing the utility of the small signal model is a priori knowledge of the quiescent
circuit state, since the numerical values of several transistor parameters in the circuit model are
functions of quiescent variables. In short, we need to know the quiescent branch and node variables before we exploit the small signal model of an active network. The input port voltage, Vi,
in Figure (7.3) has, like the output port voltage Vo, been replaced by the signal component, Vis, of
net voltage Vi, as depicted in Figure (7.4).
Rather than risk obscuring an engineering understanding of the attributes and limitations of the common emitter cell by merely jumping into the circuit analysis of the model of Figure (7.4) to deduce pertinent amplifier performance metrics, we shall partition our analysis into
several steps. We shall start by deducing the driving point input resistance (“driving point”
means a resistance computation with the actual load termination across the output port), Rine.
This input resistance metric is an important amplifier property for it establishes the signal current
drain imposed on the signal source voltage, Vs. A significant current drain, which materializes
when the input resistance is small, suggests the propriety of driving the amplifier with a current
source, as opposed to the indicated voltage source. On the other hand, a small current drain,
which derives from high input resistance, establishes a voltage source as the preferred embodiment of the applied signal source. In Figure (7.4), the current supplied by the signal source is I,
which is actually the signal base current conducted by the utilized transistor. If Rine is large, I is
correspondingly small, which produces a small voltage drop across the internal source resistance,
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Rs. In turn, this small source resistance drop allows most of the Thévenin signal voltage, Vs, to
manifest itself as signal voltage Vis across the input port of the amplifier.
The next step to our analysis venture entails the deduction of an output port macromodel. This model can be either a Thévenin or a Norton topology. We shall make our selection
based on the evaluated common emitter output resistance, Route. If Route is found to be a large
output resistance, the Norton circuit is the preferred model embodiment of the output port since
most of the Norton (short circuit) output current would be delivered to the load termination, Rl;
otherwise a Thévenin topology is appropriate. Once the output port macromodel is selected, the
Norton current or the Thévenin (open circuit) output voltage can be determined and cast as a linear function of the applied input voltage, Vs. The constant of proportionality linking either the
Norton output port current to the input signal voltage or the Thévenin output port voltage to the
input signal effectively defines the maximum possible transconductance or voltage gain, respectively, that the common emitter cell is capable of generating.
7.3.1.1. Common Emitter Input Resistance
Figure (7.5a) is the model appropriate to the evaluation of the input resistance, Rine, of
the common emitter amplifier in Figure (7.3). Observe that the equivalent circuit at hand is simply the model drawn in Figure (7.4), with the Thévenin signal source circuit replaced by a
mathematical ohmmeter comprised of the independent current, Ix. This ohmmeter current gives
rise to voltage Vx, in disassociated polarity with current Ix. Resultantly, the desired input resistance is the voltage -to- current ratio, Vx/Ix. To facilitate establishing the equilibrium equations
that produce this voltage -to- current ratio, the currents flowing through all model branches have
been identified. In terms of these currents, Kirchhoff’s voltage law (KVL) gives
rb
Vx
Ix
+ Ix
rπ
V
βac Ix
Rl
ro
Rs
−
Il + βac Ix
Vis
+
Rine
Vs
Ree
Il
Ix−Il
(a).
−
Rine
= Vx /Ix
I
(b).
Figure (7.5). (a). Small signal equivalent circuit used in the computation of the driving point input resistance, Rine, of the common emitter amplifier in Figure (7.3a). (b). The input port macromodel
of the common emitter stage. The current, I, conducted by resistance Rine in this figure is
identical to the small signal base current conducted by the amplifier in Figure (7.3a).
0 =
V
x
( Ree + ro + Rl ) Il + ( β acro − Ree ) I x
= (r + r + R ) I − R I
b
ee x
ee l
π
.
(7-14)
If we solve the first of these two relationships for current Il in terms of Ix and substitute the result
into the second equation, we learn that
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R
ine
=
Canonic Analog MOS Cells
V
⎛ β r
⎞
x = r + r + ⎜ ac o + 1 ⎟ ⎡ R
π ⎜r +R
b
⎟ ⎣ ee
I
x
l
⎝ o
⎠
( ro + Rl )⎤⎦ .
J. Choma
(7-15)
As a check on our algebraic exercises, note that for βac = 0, which artificially nullifies the
dependent current source in Figure (7.5a), the input resistance in (7-15) becomes,
V
R
= x = r +r + R
r +R .
π
ine
b
ee o
l
I
(
x
)
This result complements engineering expectations since with βacIx = 0, resistances ro and Rl are
placed in series with one another, and in turn, this series interconnection shunts the emitter
degeneration resistance, Ree. Moreover, the shunt resistance that materializes from emitter to
ground appears in series with the net base resistance, (rb + rπ ), whence the foregoing test result
is rendered transparent.
Since Early resistance ro can be expected to much larger than any practical values of
the collector load resistance, Rl, (7-15) reduces to the simpler expression,
V
(7-16)
R
= x ≈ r +r + β +1 R .
π
ine
b
ac
ee
I
x
(
)
Assuming large βac, which is invariably true, both (7-16) and (7-15) project at least a moderately
large common emitter input resistance for reasonable values of Ree. Observe, however, in Figure
(7.3) that too large an emitter degeneration resistance is impractical because the resultantly large
static voltage developed across a large emitter degeneration resistance that is compelled to conduct a stipulated quiescent emitter current is likely to require an impractically large power line
voltage, Vcc. Moreover, large Ree engenders considerable thermal noise, thereby potentially
compromising the ability of the amplifier to detect and process very small input signal voltages.
The immediate implication of the foregoing input resistance calculation is the elegantly
simple input port macromodel depicted in Figure (7.5b). It is to be understood that the input port
current, I, conducted by resistance Rine in this model is identical to the small signal base current,
I, which is highlighted in the equivalent circuit of Figure (7.4). Additionally, the resultant input
port signal voltage, Vis, is now rendered immediately transparent; specifically,
⎛ R
⎞
ine ⎟ V ,
(7-17)
V = ⎜
is
⎜R + R ⎟ s
s⎠
⎝ ine
which confirms that if Rine is large enough to satisfy the inequality, Rine >> Rs, most of the applied signal voltage, Vs, is delivered directly to the input port of the amplifier.
7.3.1.2. Common Emitter Output Resistance
The analytical tack adopted to evaluate the input resistance of the common emitter unit
can be applied to the amplifier output port to arrive at an expression for the driving point output
resistance. The pertinent equivalent circuit is offered in Figure (7.6a), where the mathematical
ohmmeter now supplants the load termination resistance, Rl. The resultant Vx/Ix calculation is a
driving point output resistance because while the Thévenin signal voltage, Vs, is reduced to zero,
the loading incurred on the input port by the signal source resistance, Rs, is maintained. In terms
of the branch currents delineated in the diagram of Figure (7.6a), we have
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Canonic Analog MOS Cells
J. Choma
rb
Vx
+ I
rπ
V
−
ro
βac I
Ix
Ix − βac I
Ree
Ix+I
(a).
Rs
Vis
rb
+
Vs
rπ
V
−
0
+ I
βac I
ro
−
IN − βac I
Ree
Ix+IN
IN
(b).
Figure (7.6). (a). Small signal model used in the computation of the
driving point output resistance, Route, of the common
emitter amplifier in Figure (7.3a). (b). The small signal
equivalent circuit pertinent to computing the Norton, or
short circuit, signal current conducted by the collector
load branch in the amplifier of Figure (7.3a).
0 =
V
x
( Rs + rb + rπ ) I + Ree ( I x + I )
= r (I − β I ) + R (I + I )
o x
ac
ee x
.
(7-18)
The elimination of current I in these two relationships leads forthwith to an emitter follower output resistance, Route, of
⎛
⎞
V
β ac Ree
⎟r + R
(7-19)
= x = ⎜1 +
R
R +r +r .
π
oute
ee
s
b
⎜
I
R +R +r +r ⎟ o
π ⎠
x
ee
s
b
⎝
If Ree = 0, I in Figure (7.6a) is constrained to zero since the bottom node of resistance rπ is returned to ground, thereby forcing 0 = (Rs + rb + rπ)I. With I = 0, βacI is clearly zero, which
means that the only electrical entity seen looking into the amplifier output port is Early resistance
ro. Equation (7-19) correctly reflects this observation in that Ree = 0 produces Route = ro. The
result at hand shows that for nonzero emitter degeneration resistance, the common emitter output
resistance is larger than the already reasonably large Early resistance, ro. Depending on the
value of gain parameter βac and the relationship between resistance Ree and the resistance sum,
(Rs + rb + rπ), Route can actually be significantly larger than ro. For ro large, (7-19) collapses to
(
Ming Hsieh Department of Electrical Engineering
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)
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=
R
oute
Canonic Analog MOS Cells
V
β R
⎛
J. Choma
⎞
x ≈ ⎜1 +
ac ee
⎟r .
⎜
I
R +R +r +r ⎟ o
π ⎠
x
ee
s
b
⎝
(7-20)
Because the common emitter output resistance is large, a Norton equivalent macromodel for the amplifier output port is a reasonable architectural choice. To this end, the Norton
load current, IN, which is the current flowing through the collector load branch when the collector load resistance is supplanted by a short circuit, can be calculated with the model depicted in
Figure (7.6b). Observe in this model that load resistance Rl is indeed short circuited, while the
signal source comprised of voltage Vs and resistance Rs is maintained. In terms of the indicated
branch currents, the subject model delivers
0 = r
( I N − β ac I ) + Ree ( I N + I )
( Rs + rb + rπ + Ree ) I + Ree I N
o
V
s
=
.
(7-21)
These two equations can be solved straightforwardly for the Norton current, IN, whence the
effective transconductance, say gme, of the common emitter amplifier evolves as
⎛ r
⎞⎛
R ⎞
o
⎟⎜ 1 − ee ⎟
β ac ⎜
⎜ r + R ⎟⎜
β ac ro ⎟
β ac
I
ee ⎠⎝
⎝ o
⎠
N =
g
,
≈
(7-22)
me
V
β
r
1
R
+
+
R +r +r + β +1 R r
s
π
ac
ee
π
s
b
ac
ee o
where the approximation reflects the presumption of a large Early resistance. Recalling (7-10)
and introducing the common base small signal current gain parameter, αac, as
(
α ac =
β ac
β ac + 1
)(
)
(
)
(7-23)
,
the approximate form of the effective transconductance in (7-22) is expressible as
I
β ac
g
N ≈
m
(7-24)
=
g
.
me
V
⎛
⎞
R
β
r
1
R
+
+
s
ac
ee
π
1 + g ⎜ ee ⎟
m ⎜α ⎟
⎝ ac ⎠
Equation (7-24) underscores the immediate effect of emitter degeneration resistance on amplifier
I/O performance. In particular, we see that Ree reduces the forward transconductance, gm, of the
utilized transistor by the potentially substantial factor of [1 + (gmRee/αac)]. This reduction, or
“degeneration,” can be viewed as disadvantageous from the viewpoint that the effective
transconductance of a circuit is a measure of the gain that can be achieved by that circuit. But a
potential advantage of degeneration is the reduced sensitivity of the forward transconductance,
gme, on the transistor transconductance, gm, which (7-12) portrays as dependent on temperature
and quiescent collector current. For example, if gmRee/αac >> 1 in (7-24), the circuit I/O
transconductance, gme, approximates as
I
g
α
N ≈
m
(7-25)
≈ ac ,
g
me
V
R
⎛
⎞
R
s
ee
1 + g ⎜ ee ⎟
m ⎜α ⎟
⎝ ac ⎠
which, to the extent that αac in (7-23) approaches one by virtue of the fact that βac >> 1, is all but
completely independent of transistor parameters. Of course, this approximate parametric
(
Ming Hsieh Department of Electrical Engineering
)
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independence is true if and only if the transistor provides sufficient transconductance to validate
the constraint, gmRee /αac >> 1.
7.3.1.3. Common Emitter Output Port Macromodel
Armed with (7-15), (7-19), and (7-24), the small signal Norton macromodel of either of
the two common emitter stages depicted in Figure (7.3) is the network shown in Figure (7.7a).
In this representation, it must be understood that parameter gme is the effective common emitter
Norton transconductance from the applied signal source voltage, Vs, to the signal current that
flows in the short circuited collector load branch at the output port. A slight modification to this
structure is the alternative macromodel depicted in Figure (7.7b). In the latter structure, gmie
signifies the transconductance from the input port voltage, Vis, to the short circuited collector
load branch. We observe in Figure (7.7a) that
Rs
Vis
IN
+
gmeVs
Rine
Vs
Ios
Route
Vos
Rl
−
(a).
Rs
Vis
IN
+
gmieVis
Rine
Vs
Ios
Route
Vos
Rl
−
(b).
Figure (7.7). (a). Small signal macromodel of the common emitter amplifier
in Figure (7.3a). Observe that the VCCS, gmeVs, is couched as a
linear function of the applied input signal voltage, Vs. (b).
Alternative form of the common emitter macromodel. The
VCCS, gmieVs, incident with the amplifier output port is depicted
as proportional to the input port voltage, Vis.
V
R
is =
ine
,
V
R +R
s
ine
s
(7-26)
whence
⎛
R ⎞
⎜ 1 + s ⎟V .
(7-27)
me s
me ⎜
R ⎟ is
ine ⎠
⎝
If we study this disclosure in light of Figure (7.7b), we conclude that the so-called port
transconductance, gmie, of the common emitter amplifier is
g
V
= g
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Canonic Analog MOS Cells
J. Choma
⎛
R ⎞
⎜1 + s ⎟ .
(7-28)
mie
me ⎜
R ⎟
ine ⎠
⎝
Obviously, the port transconductance, gmie, is larger than the effective common emitter
g
= g
transconductance, gme, but if Rine >> Rs, gmie ≈ gme.
Returning to Figure (7.7a), we see that the small signal I/O voltage gain, Ave, of the
common emitter cell undergoing scrutiny is
V
α R
(7-29)
A os = − g
R
R ≈ − g R ≈ − ac l ,
ve
me oute l
me l
V
R
s
(
)
ee
where the first approximation exploits the commonly valid assumption, Route >> Rl, and the second approximation exploits (7-25). The same gain result ensues through use of Figure (7.7b);
recalling (7-26),
⎛ R
⎞
V
V
V
ine ⎟ ,
(7-30)
A os = os × is = ⎡ − g
R
R ⎤×⎜
ve
⎢⎣ mie oute l ⎥⎦ ⎜ R + R ⎟
V
V
V
s
is
s
s⎠
⎝ ine
which, by (7-28), is identical to (7-29).
)
(
Either of the preceding two analytical disclosures highlights the virtual direct dependence of common emitter gain on the load resistance, Rl. This gain dependence on load termination is a direct consequence of the high resistance presented by a common emitter amplifier at its
output port. Ordinarily, such a gain dependence on load resistance is a dubious characteristic
because, as has already been mentioned, it implies limited amplifier versatility; that is, a particular value of I/O voltage gain is achieved for only a single specified load resistance. But (7-29)
foretells an attribute if the amplifier is used to drive high impedance external loads connected
between circuit ground and the collector terminal of the transistor. In this case, resistance Rl
functions exclusively as a biasing element and like resistance Ree, it is therefore implemented as
an on chip diffused or implanted element. In a typical integrated circuit, resistance values suffer
from tolerances of up to about ±20%. But the resistance ratios of two resistors having comparable layout geometries (both wide and long, both narrow and long, etc) can be controlled to tolerances that are typically no worse than 2% -to- 5%. In this case, the common emitter voltage gain
in (7-29), which features the resistance ratio, Rl/Ree, is, with but modest layout care, predictable,
repeatable, and accurately controllable, especially since the gain parameter, αac, is very nearly
one.
It is vital to appreciate the fact that the negative sign in the gain relationships of (7-29)
and (7-30) indicate I/O phase inversion and are not merely the ramifications of algebraic convention. To understand better this phase inversion property, return to the amplifier in Figure (7.3a)
and assume that signal voltage Vs increases with time. As Vs rises, the voltage observed across
the base-emitter terminals can be expected to rise proportionately, which in turn incurs an increase in the collector current flowing into the NPN unit, thanks to Ebers and Moll[5]. This increased collector current manifests an increased voltage drop across the collector load resistance,
Rl. In turn, the enhanced Rl voltage drop diminishes the voltage that remains for the collector
node of the amplifier because of the fixed supply voltage, Vcc. Hence, an increase in Vs is met
with a proportionate decrease in the net output voltage, Vo, which defines classic phase inversion.
Of course, it can also be demonstrated that a decrease in Vs is met with increased Vo.
Ming Hsieh Department of Electrical Engineering
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Canonic Analog MOS Cells
J. Choma
Finally, it is worthwhile pointing out that the circuit transconductance, Gme, which is
the ratio of the load current, Ios indicated in Figure (7.6) -to- the applied signal voltage, Vs, is
⎛ R
⎞
I
α
os = − g ⎜
oute ⎟ ≈ − g
(7-31)
≈ − ac .
G
me
me ⎜ R
me
R
+R ⎟
V
s
l⎠
ee
⎝ oute
Equation (7-31) confirms previous speculations that the common emitter amplifier is a natural
transconductor cell in that for Route >> Rl, the circuit transconductance is essentially independent
of the collector load resistance. In fact, if the approximation that precipitates (7-25) is valid, the
circuit transconductance is all but completely independent of signal source resistance Rs and
transistor parameters.
7.3.2. PASSIVE INPUT PORT BIAS
The common emitter amplifiers depicted in Figure (7.3) are best deployed as interstage
units, wherein voltage Vbb, which forward biases the base-emitter junction of the transistor, derives as the quiescent output voltage of the preceding stage. But when a common emitter amplifier is the first stage of a system, Vbb is rarely available as an independent biasing supply. In this
case, Vbb, which must be smaller than Vcc to reverse bias the base-collector junction, can be extracted as a voltage divider off of the Vcc line, as is shown in the NPN common emitter amplifier
in Figure (7.8). To underscore this contention, the divider formed of the Vcc–R1–R2 subcircuit
can be replaced by the Thévenin equivalent network embedded in the alternative diagram of Figure (7.8b). In this circuit, Vbb is not an independently applied voltage source but rather, it is the
Thévenin, or open circuit, voltage of the divider. In particular,
+Vcc
+Vcc
R1
Rs
Cc
Rl
Rl
Vo
Roueb
Rine
Cc
Rs
Vi
+
Rine
Vi
Rp
+
Vs
Rineb
−
R2
Ree
Vs
−
Vo
Roueb
Rineb
Ree
+
Vbb
−
(a).
(b).
Figure (7.8). (a). Common emitter stage with base circuit biasing supplied by a voltage divider off of
the supply line voltage, Vcc. (b). The circuit of (a) with the biasing divider formed by resistances R1 and R2 replaced by a Thévenin equivalent circuit.
⎛ R
⎞
2 ⎟V ,
= ⎜
bb
⎜ R + R ⎟ cc
⎝ 2
1⎠
while the Thévenin resistance of the biasing divider is
V
R
p
= R R .
1
(7-33)
2
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Thus, a voltage, Vbb, complete with its internal resistance, Rp, is established via voltage division
of the Vcc supply line to bias the base of the transistor in the common emitter network. Since the
circuit in Figure (7.8b) is little more than the circuit of Figure (7.8a) with the Vcc–R1–R2 divider
chain replaced by its Thévenin equivalent, the electrical behavior of the two networks in Figure
(7.8) is identical.
The coupling capacitor, Cc, in either of the two schematic diagrams of Figure (7.8)
serves to isolate the signal source from the static voltage established to bias the transistor base
node. The isolation of the signal source is self-evident in the quiescent, or standby, state of the
circuit since all capacitors emulate open circuits for the zero frequencies that are implicit to
quiescent environments. But while a capacitor of any size satisfies the DC isolation requirement,
capacitance Cc must be large enough so that it behaves as an electrical short circuit for all nonzero signal frequencies of interest. The reason underlying this desired short circuit behavior is
that we do not wish capacitance Cc, which is connected in series between the signal source and
the amplifier input port, to cause significant attenuation of the applied input signal. If capacitance Cc emulates a short circuit for frequencies above some lowest frequency, say ωl, we can be
assured that most of the applied signal voltage is transferred to the transistor base node, which
forms the amplifier input port. On the other hand, if capacitance Cc does not behave as a signal
short circuit, a potentially appreciable percentage of the applied input signal amplitude is needlessly lost in the process of connecting this signal to the amplifier input port. In a word, too
small of a capacitance value incurs gain loss even before the applied input signal has a chance of
being processed by the amplifier.
In order to formulate the coupling capacitance requirements, consider the diagram In
Figure (7.9), which displays the small signal model of the input port to the amplifier in Figure
(7.8). Since the incorporation of the biasing resistances, R1 and R2, changes nothing to the right
of the base node in Figure (7.8), the resistance, Rine, presented to this node by the amplifier remains given by the expression in (7-15). It follows from a consideration of the structure in Figure (7.9a) that
Rs
Cc
Kps Rs
Vis
+
Vis
+
Vs
Rp
Rineb
−
Kps Vs
Rine
Rine
−
(a).
(b).
Figure (7.9). (a). Small signal equivalent circuit of the input port of the common emitter
amplifier in Figure (7.8b). (b). The circuit of (a) with the network driving the
amplifier input port replaced by its Thévenin equivalent representation for
frequencies at which capacitance Cc behaves as a short circuit.
V
is =
V
R
s
R
p
R
ine
1
R +R +
p ine
s
jωC
=
c
(
jω R
(
1 + jω R
p
p
R
ine
R
ine
)C
c
)
+R C
s
,
(7-34)
c
for which the magnitude response is
Ming Hsieh Department of Electrical Engineering
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V
is
(
J. Choma
.
(7-35)
)
ω R p Rine Cc
=
V
Canonic Analog MOS Cells
(
)
2
1 + ⎡ω R R + R C ⎤
p ine
s c ⎥⎦
⎢⎣
Clearly, |Vis/Vs| = 0 for ω = 0, which affirms the decoupling of the signal source from the amplifier port in the standby circuit condition. In a word, the signal source is isolated from the quiescent circuit because it is effectively disconnected from the amplifier for DC conditions. For any
nonzero frequency, (7-35) shows that the input port transfer magnitude function, |Vis/Vs|, is frequency dependent, a circumstance that arises from a progressive decrease in capacitive impedance as the signal frequency increases. It is therefore reasonable to project that at a sufficiently
high signal frequency, the capacitive impedance diminishes to virtually zero; that is, an approximate short circuit. If the amplifier at hand is earmarked to provide common emitter signal
processing at all frequencies above a lowest frequency, say ωl, (7-35) promotes the design
requirement,
s
(
)
⎡ω R R + R C ⎤
s c ⎥⎦
⎢⎣ l p ine
which is satisfied if
(
2
>> 1 ,
(7-36)
10 ;
(7-37)
)
ωl R p Rine + Rs Cc ≥
that is, the time constant associated with coupling capacitance Cc must be at least as large as
about 3.2-times the inverse of the lowest radial frequency of interest. If (7-37) is satisfied, Cc in
Figure (7.9a) approximates a short circuit for all radial frequencies above ωl. This observation
therefore allows the input port to be represented by the topology offered in Figure (7.9b). In the
later circuit diagram, the network to the left of the amplifier input port in Figure (7.9a) is replaced by its Thévenin form. In this electrically equivalent format, the open circuit voltage driving the input port is
⎛ R
⎞
p
⎜
⎟V K V ,
(7-37)
ps s
⎜R + R ⎟ s
s⎠
⎝ p
and the Thévenin resistance “seen” by the amplifier input port is
R
p
R
s
= K
R ,
(7-38)
ps s
where
K
ps
=
R
p
R +R
p
=
s
R R
1
2
R R +R
1
2
(7-39)
,
s
and we have appealed to (7-33).
There are several design-oriented implications to the two macromodels postured in Figure (7.9). The first of these is that for frequencies larger than ωl, as introduced in (7-36), the input resistance, Rineb, that the signal source is compelled to drive is
R
= R R
= R R R
≈ R R ⎡r + r + β + 1 R ⎤ .
(7-40)
ineb
p ine
1 2 ine
1 2 ⎣b
π
ac
ee ⎦
where we have used (7-33) and (7-16). Clearly, this input resistance is smaller than the input
resistance, Rine, observed prior to the incorporation of the resistive biasing divider. Since the
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Canonic Analog MOS Cells
J. Choma
input resistance of a common emitter stage, which is fundamentally a transconductor, must be
maintained large, we conclude that the biasing resistances, R1 and R2, must be large. Fortunately,
this constraint synergizes with prudent, low power biasing network design in that large R1 and R2
ensures that the static current drained from the Vcc supply by the R1–R2 divider in Figure (7.8a) is
small.
A second implication of resistive biasing and capacitive input coupling is that for ω ≥
ωl, the macromodel of Figure (7.7a) becomes the redefined network structure submitted in Figure
(7.10). The input port section of this amplifier macromodel mirrors the structure in Figure
(7.9b). Remember that in Figure (7.7a), the VCCS at the output port is proportional to the
Thévenin signal voltage, Vs, which drives the amplifier input port. Accordingly, the VCCS at the
output port in Figure (7.10) is necessarily proportional to KpsVs, which we witness as the effective Thévenin signal voltage that drives the self-biased input port of the common emitter
configuration. Moreover, we recall from (7-22) that the I/O transconductance, gme, is
functionally dependent on the resistance of the signal source applied to the amplifier. Since the
effective signal source resistance has changed from its original Rs to its modified value, KpsRs,
gme modifies to its revised value, gmeb, where by (7-22),
KpsRs
Vis
IN
Ios
Vos
+
KpsVs
Kps gmebVs
Rine
Roueb
Rl
−
Figure (7.10). Small signal macromodel of the resistively biased common emitter
amplifier in Figure (7.8a) for signal frequencies at which coupling
capacitor Cc approximates a signal short circuit.
⎛
⎞⎛
R ⎞
⎟⎜ 1 − ee ⎟
⎜ r + R ⎟⎜
β ac ro ⎟⎠
ee ⎠⎝
⎝ o
β ac ⎜
g
=
r
o
.
(7-41)
R +r +r + β +1 R r
ps s
b
π
ac
ee o
Interestingly, the effect of the self-biasing resistances is to increase (very slightly) the forward
transconductance of the amplifier in that the effective source resistance, to which transconductance is inversely related is reduced by a factor of Kps. However, it should be noted that Kps in
(7-39) tends toward unity if the biasing resistances, R1 and R2, are reasonably large. However,
this modest increase is moot since the transconductance in the VCCS output generator in Figure
(7.10b) is multiplied by the less than unity constant, Kps.
meb
K
(
)(
)
Reasoning that is similar to that adopted in conjunction with circuit transconductance
issues serves to convince that the original shunt output port resistance, Route, transforms to its revised value, Roueb, where by (7-19)
⎛
⎞
β ac Ree
⎜
⎟r + R
R
K R +r +r .
(7-42)
= 1+
oueb
ee
ps s
b
π
⎜
R +K R +r +r ⎟ o
ee
ps
s
b
π
⎝
⎠
(
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Obviously, the model in Figure (7.7b) can be similarly adjusted to account for the incorporated
biasing network, and the standard approximations invoked earlier can be applied herewith. In
view of the model developed in Figure (7.10), the updated I/O voltage gain, say Aveb, of the selfbiased common emitter amplifier becomes, with due diligence applied to (7-29),
α ac K ps Rl
V
os
A
= −K g
R
R ≈ −K g
R ≈ −
.
(7-43)
veb
ps meb oueb l
ps meb l
V
R
s
(
)
ee
Observe that an immediate impact of the resistive bias structure is I/O voltage gain attenuation.
The subliminal message in need of digestion here is that despite being given a new, albeit only slightly modified, common emitter amplifier to assess, we did not need to repeat the
analytical detail developed and discussed in the process of investigating the original common
emitter architectures of Figure (7.3). Instead, we relied on the experience and insights we garnered from the first analysis to assess the second structure. Aside from streamlining requisite
algebraic manipulations, this design-oriented analysis procedure helped us to develop a conceptual understanding of the impact exerted by the circuit modifications on the observable performance of the amplifier; e.g. input biasing resistances degrade I/O gain. Our analysis of the new
structure entailed little more than simply modifying appropriate circuit parameters encountered
in the first investigation and then applying the performance metric equations that we had already
developed. To be sure, not every new circuit topology is amenable to this simple “parameter
adjustment” analytical approach, but we shall ultimately learn that as we continue to construct
our electronic circuits base of experience, progressively more and more circuits will become
commensurately less foreign to us.
A key to the success of the foregoing analytical adaptation philosophy is the work ethic
we embraced in the first common emitter amplifier analysis. In particular, we elected not to simply write the Kirchhoff equilibrium equations to formulate the I/O characteristics of the amplifier. As the mathematical intricacy of the equations we ultimately compiled suggest, this “write
equation and solve equation” methodology would have engendered an algebraic mess that inhibits meaningful and insightful engineering interpretation. The conventional analytical method is
therefore counterproductive to the engineering goals of design creativity and design innovation.
Instead, we partitioned the first analysis into various components in an attempt to paint vivid images of the amplifier input resistance, output resistance, and I/O gain properties. Once these metrics were thoroughly understood in terms of the transistor parameters and the designable variables of the network topology, we were able to proceed to an alternative architectural form of the
considered circuit.
7.3.3. DIODE COMPENSATED INPUT PORT BIAS
The collector current of a BJT has a positive temperature coefficient, which is to say
that in the absence of any thermal compensation deployed at the circuit level, the collector current rises with increasing junction temperature. It should be noted that this increased temperature is not necessarily due to the ambient environment. Instead, and generally most predominantly, junction temperature increases occur because of the heat generated by internal losses
motivated by the large current densities that prevail in minimal geometry devices. In order to
stabilize the quiescent collector current of the BJT embedded in a common emitter amplifier, a
diode is often used to mitigate, albeit partially, the temperature rises observed in the base-emitter
junction.
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The traditional circuit diagram of a diode-compensated common emitter amplifier is
provided in Figure (7.11). The diode in this case is formed of transistor Q2, whose base and
collector terminals are connected together. Transistor Q1 is the transistor that provides
transconductor signal processing and is, in fact, the transistor addressed in our two preceding
common emitter topologies. In the present case, adequate thermal compensation requires that
transistors Q1 and diode-connected transistor Q2 be identical transistors conducting identical
collector current densities. Thus, for example, if the base-emitter junction area of transistor Q1
is k-times larger than that of Q2, it is necessary to choose resistances R2 and Ree such that Q1
conducts a quiescent collector current that is k-times the collector current flowing in transistor
Q2.
+Vcc
R1
Cc
+
Vo
Roueb
Rine
Vi
Q1
Q2
Rs
Vs
Rl
Rineb
R2
Ree
−
Figure (7.11). Common emitter amplifier
compensated biasing.
with
diode-
A comparison of the schematic diagram in Figure (7.11) with that of Figure (7.8a) portrays the two circuits as topologically identical, save for the fact that resistance R2 in Figure
(7.8a) is now replaced by the series combination of resistance R2 and the small signal resistance,
say Rd, presented to the circuit by the diode-connected device, Q2. In short, once we figure out
the mathematical nature of diode resistance Rd, we need only return to our analytical results for
input resistance, output resistance, transconductance, voltage gain, and other figures of merit for
the amplifier in Figure (7.8a) and simply replace R2 in those disclosures by the resistance sum
(R2 + Rd). This analytical tack is an elegantly straightforward example of how we build on our
base of circuit analysis experience to formulate performance metric equations for modified versions of topologies already addressed. In effect, we are obviating the need for additional, and
often tediously boring, algebra in favor of a streamlined analytical approach that is computationally efficient and supportive of forging design insights.
Figure (7.12) displays the low frequency, small signal equivalent circuit of diode-connected transistor Q2. A mathematical ohmmeter in the form of current source Ix is appended
across the terminals of the device to compute the diode resistance as Rd = Vx/Ix. Even though Q2
is physically identical to Q1, and Q1 and Q2 are likely to conduct equal densities of collector
currents, we allow for different values of corresponding small signal model parameters because
the two transistors may conduct different corresponding currents. In other words, the base-emitter junction areas of the two devices may be different. The model in question delivers
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I
rb2
Ix
+
Q2
+ I
Vx
V
−
+
rπ2
βac2 I
−
ro2 Vx
−
Ix−(βac2+1)I
Ix
Figure (7.12). Small signal equivalent circuit used in the evaluation of the resistance presented to
the circuit by the diode connected transistor, Q2, in the common emitter stage of Figure (7.11).
V
V
( b2 + rπ2 ) I
r ⎡I − ( β
+ 1) I ⎤
o2 ⎣ x
ac2
⎦
x
= r
x
=
(7-44)
.
If the first of these two equations is solved for current I and the solution is substituted into the
second relationship, we readily find that the resistance across the terminals of diode-connected
transistor Q2 is
⎛r +r ⎞
V
R = x = r ⎜ b2 π 2 ⎟ .
(7-45)
d
o2 ⎜ β
I
+1⎟
x
⎝ ac2
⎠
Since the Early resistance, ro2, is large and the gain parameter, βac2 is large, (7-45) approximates
as
⎛r +r ⎞
r +r
R = r ⎜ b2 π 2 ⎟ ≈ b2 π 2 ,
(7-46)
d
o2 ⎜ β
+1⎟
β
+1
ac2
⎝ ac2
⎠
and in turn, (7-10) enables expressing this relationship as
⎛r +r ⎞
r +r
α
R = r ⎜ b2 π 2 ⎟ ≈ b2 π 2 ≈ ac2 ,
(7-47)
d
o2 ⎜ β
β
g
+1⎟
+1
ac2
m2
⎝ ac2
⎠
where we presume βac2 >> gm2rb2. Our analysis of the amplifier in Figure (7.11) is now all but
completed for all that remains to be done is to replace resistance R2 by resistance sum (R2 + Rd)
in the pertinent performance metric equations we gleaned for the network in Figure (7.8a). For
example, Kps in (7-39) becomes
K
ps
=
R
p
R +R
p
s
=
( R2 + Rd )
R (R + R ) + R
1
2
d
s
R
1
,
(7-48)
Before proceeding to the next circuit of interest, it may be instructive to examine the diode resistance result in (7-45) in light of the engineering dynamics of the model provided in Figure (7.12). Specifically, since resistance ro2 in this model is in shunt with the terminals to which
the mathematical ohmmeter is incident, we know that the result for Rd must be of the form of ro2
in parallel with some other resistance. We might therefore wish to evaluate Rd by removing ro2
to simplify the circuit, calculating the resistance that remains in the simplified network, and ultimately remembering that this remaining resistance appears in parallel with ro2. With ro2 removed
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in Figure (7.12), the only resistance that remains is the sum, (rb2 + rπ2). But while this resistance
sum conducts a signal base current, I, the ohmmeter conducts a signal emitter current that is (βac2
+ 1)-times larger than the base current. Since larger current levels infer smaller resistances, the
resistance sum referred to the emitter, or “seen” by the ohmmeter, is necessarily (rb2 + rπ2)/(βac2
+1), whence the final form resistance deduced mathematically as the expression in (7-45).
7.3.4. TRANSISTOR COMPENSATED INPUT PORT BIAS
An improved version of the temperature compensation scheme afforded by the diodeconnected transistor in the common emitter unit of Figure (7.11), is the topology shown in Figure
(7.13). The latter diagram replaces transistor Q2 in Figure (7.11) by the Vbe multiplier subcircuit
comprised of transistor Q2 and resistances Rx and Ry. As in the amplifier of Figure (7.11),
transistors Q1 and Q2 are physically matched, but they be implemented on chip with different
base-emitter junction areas. Deviations in layout geometries are made to ensure identical current
densities in both devices (which helps to sustain identical temperature characteristics in both
transistors, despite the potential need for different absolute quiescent current levels. We note in
this figure that the Q2–Rx–Ry subcircuit functions as a two terminal structure connected in series
with resistance R2. Since transistor Q2 is biased in its active regime and is to be modeled by a
small signal equivalent circuit that is inherently linear, the Vbe multiplier cell behaves as a resistance, whose value we symbolize as Rv. Thus, the R2 branch of the amplifier in Figure (7.13)
houses a net resistance of (R2 + Rv). As in the preceding section of material, we may therefore
expedite the analysis of the present amplifier simply by replacing resistance R2 by the net resistance, (R2 + Rv) in the relevant equations that define the performance traits of the amplifier in
Figure (7.8a).
+Vcc
R1
Cc
Vs
Vo
Roueb
Rine
Vi
Q1
Ry
Rs
+
Rl
Rineb
Q2
Rx
−
R2
Ree
Figure (7.13). Common emitter amplifier using a Vbe multiplier
(subcircuit consisting of Q2–Rx–Ry) for thermal
compensation of the quiescent operating point.
Figure (7.14) displays the equivalent circuit for calculating the aforementioned small
signal resistance, Rv, of the Vbe multiplier. The model of Figure (7.2a) is selected to represent the
small signal characteristics of the transistor, and the mathematical ohmmeter (current source Ix
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with disassociated polarity voltage Vx developed across Ix) excites the collector and emitter nodes
of the Vbe multiplier. The branch currents are identified to facilitate the application of KVL,
which establishes the equilibrium conditions,
Ry
Ir
rb2
Ry
+ I
+
Q2
Rx
Ix
rπ2
Rx V
Vx
+
βac2 I
ro2 Vx
−
−
−
Ix−Ir+I
Ix−βac2I−Ir
Ir−I
Ix
Figure (7.14). Small signal equivalent circuit used in the evaluation of the resistance presented to
the circuit by the Vbe multiplier in the common emitter stage of Figure (7.13).
( rb2 + rπ 2 ) I = Rx ( I r − I )
r (I − β
− I ) = R I + (r + r ) I
o2 x
ac2
r
y r
b2
π2
V = R I + (r + r ) I
x
y r
b2
π2
(7-49)
.
The elimination of current variables I and Ir from these three relationships leads to
r ⎡R + R r + r ⎤
V
o2 ⎢⎣ y
x b2
π2 ⎥⎦
R = x =
.
v
I
⎡
⎤
⎛
⎞⎢
x
R
r
⎥
x
o2
⎜
⎟
1+ β
⎥
ac2 ⎜ R + r + r ⎟ ⎢
⎝ x b2 π2 ⎠ ⎢⎣ ro2 + R y + Rx rb2 + rπ2 ⎥⎦
(
)
(
(7-50)
)
The propriety of this admittedly cumbersome expression can be tested by considering the special
case, Rx = ∞ and Ry = 0, which reduces the Vbe multiplier cell in either Figure (7.13) or Figure
(7.14) to the classic diode-connected transistor configuration studied in the preceding section of
material. From (7-50),
R R =∞ =
v x
r
o2
( rb2 + rπ 2 )
⎛r +r ⎞
⎜ b2 π 2 ⎟ = R ,
o2 ⎜ β
d
+1⎟
⎝ ac2
⎠
≡ r
(7-51)
⎡
⎤
r
o2
R =o
⎢
⎥
1+ β
y
ac2 ⎢ r + r + r ⎥
b2
π2 ⎦
⎣ o2
which, as anticipated, is identical to the resistance expression found as (7-45). This successful
test does not guarantee the correctness of (7-50). But a test that does not confirm Rv = Rd for Rx
= ∞ and Ry = 0 absolutely assures the incorrectness of (7-50).
7.3.5. COMMON EMITTER WITH ACTIVE LOAD
Figure (7.15a) is a simplified schematic diagram of an NPN common emitter (QN)
amplifier whose collector load circuit is an active network comprised of PNP transistor QP,
resistances Re1 and Rb1, and a biasing voltage, Vbb2. Along with supply voltage Vcc, Vbb2 is chosen
and appropriately implemented (perhaps as a divider from the Vcc line) to ensure the active
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regime biasing of QP. Simple base circuit biasing of transistor QN via the voltage source, Vbb1,
similarly supports the active regime biasing of transistor QN. Transistor QP is necessarily a PNP
transistor because its collector current feeds NPN transistor QN, whose net collector current
flows into the device.
+Vcc
Re1
rbp
Rb1
Vbb2
Rout
QP
+
Rouep
Vo
Rouen
−
Rs
Vi
+
+ I
Rb1
V
rπp
βacp I
I
Ix−βacpI
rop
−
I
Re1
QN
+
Vx
Ix
−
Vs
−
Vbb
+
Rine
Ix
I
Ree
−
(a).
(b).
Figure (7.15). (a). Common emitter amplifier with active collector load realized by PNP transistor QP
and requisite biasing elements. (b). Small signal model used to evaluate the effective
value, Rouep, of the collector load resistance that terminates the output port of the NPN
common emitter device, QN.
It is interesting to observe that since the emitter and base leads of QP are returned to
signal ground through resistances Re1 and Rb1, respectively, the QP active load effectively acts as
a two terminal circuit branch element. These two terminals are the collector node of QP and signal ground (constant voltages are modeled as null voltages in small signal equivalent circuits).
Moreover, if QP is replaced by one of the small signal BJT models presented in Figure (7.2), the
QP–Re1–Rb1 subcircuit is not only a two terminal branch element, it is effectively modeled as a
two terminal linear branch element. In view of the fact that the models used to study transistor
performance in linear regimes are presently restricted to relatively low signal frequencies, the
aforementioned two terminal subcircuit therefore behaves as a linear resistance. This resistance,
which is highlighted in Figure (7.15a) as Rouep, can be found through use of the QP–Re1–Rb1
subcircuit model that appears as Figure (7.15b). But a bit of diligence reveals that this equivalent
circuit is topologically identical to the structure shown in Figure (7.6a), which we used to evaluate the output resistance, Route, of the common emitter amplifier in Figure (7.3a). Even the
branch currents shown in Figure (7.15b) are identical in form to the branch currents shown in
Figure (7.3a). Thus, the good news is that it is pointless to endure the algebra that surfaces from
the analysis of Figure (7.15b). Instead, we can craft an expression for Rouep directly from (7-19),
provided we make the appropriate parametric substitutions. For example, Ree in the former network is now Re1, Rs in the former circuit is now Rb1, and so forth. Accordingly, the effective load
resistance result is easily confirmed to be
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V
β
⎛
R
acp e1
= x = ⎜1 +
R
ouep
⎜
I
R +R +r +r
x
e1
b1 bp
πp
⎝
J. Choma
⎞
⎟r + R
R +r +r
e1
b1 bp
πp
⎟ op
⎠
(
)
(7-52)
⎛
⎞
β acp Re1
⎟r ,
≈ ⎜1 +
⎜
R + R + r + r ⎟ op
e1
b1 bp
πp ⎠
⎝
where, as usual, we have exercised the reasonable option of a large Early resistance. Note that in
the absence of emitter degeneration in transistor QP, Re1 = 0, and Rouep collapses to Rouep = rop.
As our earlier common emitter analyses suggest, the use of emitter degeneration in the present
load branch can substantively enhance the effective load resistance.
Several noteworthy points surround the active load initiative in the common emitter
amplifier of Figure (7.15a). The first of these is that the load resistance is very large. It is typically upwards of tens to even hundreds of thousands of ohms. It is impossible to implement such
a large load resistance as a passive resistance alone for to do so would require an enormous supply line voltage. For example a load resistance of 200 KΩ inserted into a collector that is to conduct 1 mA of quiescent current requires Vcc larger than 200 volts, which hardly synergizes with
the present day electronics portability culture. Yet, an effective 200 KΩ load resistance can be
synthesized actively with a single PNP transistor whose emitter -to- collector bias voltage can be
as small as a mere few tens of millivolts above the base-emitter turn on potential of nominally
700 mV -to- 800 mV.
A second important point is than an effective large load resistance befits a need to
achieve very large voltage gain, such as is required in the open loops of operational amplifiers.
For example, the voltage gain of the amplifier in Figure (7.15a) derives from (7-29); that is,
α acn ⎛⎜ Rouen Rouep ⎞⎟
V
⎠ ,
⎝
⎛R
⎞
(7-53)
A os = − g
⎜ ouen Rouep ⎟ ≈ −
ve
men
⎝
⎠
V
R
s
ee
where gmen is identical in form to gme in (7-22), and Rouen is identical in form to Route in (7-19). In
an attempt to derail possible confusion, (7-22) applied in the context of Figure (7.15a) delivers a
forward transconductance, gmen, of
⎛ r
⎞⎛
⎞
R
on
ee ⎟
⎟⎜ 1 −
β acn ⎜
⎜ r + R ⎟⎜
β acn ron ⎟⎠
β acn
on
ee ⎠⎝
⎝
g
,
=
≈
(7-54)
men
r + β
+1 R
R +r +r + β
+1 R r
acn
ee
πn
s
bn
acn
ee on
πn
while (7-19) produces
⎛
⎞
β acn Ree
⎟r + R
(7-55)
R
= ⎜1 +
R +r +r
.
ouen
ee
s
bn
πn
⎜
R + R + r + r ⎟ on
ee
s
bn
πn ⎠
⎝
The resistance ratio, (Rouen||Rouep)/Ree, can be very large, thereby effecting a large I/O voltage
gain. Even larger gains can be generated if no degeneration (Ree = 0) is used in conjunction with
transistor QN. This contention follows from (7-25), which confirms that in the absence of emitter degeneration, gmen rises to the transistor forward transconductance, gm, which can be many
times larger than gmen.
(
)
)(
(
(
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A third and unfortunate point to be made is that setting the quiescent output voltage
reliably, accurately, and predictably to a desired value that satisfies I/O gain and resistance
requirements is a daunting undertaking. The problem is that the Early voltage and both static
and small signal transistor current gains are plagued with large processing tolerances. These
manufacturing vagaries impart considerable uncertainty to the problem of establishing numerical
values of those transistor gain and resistance parameters on which the quiescent operating point
is dependent. The problem is exacerbated when the Early effects in both the PNP and NPN units
are deemed negligible; that is, the Early voltages are infinitely large, and the corresponding Early
resistances are also infinitely large. In this case, the PNP BJT acts as an ideal emitter -to- collector current source that is placed in series with an ideal collector -to- emitter current sink that the
NPN transistor emulates. The problem at hand is akin to the classic insoluble problem that is
abstracted in Figure (7.16). In this problem, the neophyte circuits student is asked to attempt
finding the voltage, VoQ, across an ideal current source (IcQ) that is placed in series with a second
current source that necessarily has the same current value of IcQ. The series interconnection of
the current source and the current sink are driven by a known voltage source, Vcc. Before the
frustrated student intent on solving the problem contemplates doing something rash, we remind
him/her that since the current conducted by an ideal current source (or sink) is independent of the
voltage developed across the terminals of the source or sink, the problem assigned cannot be
solved. This is a mathematically elegant way of asserting that voltage VoQ cannot be determined
analytically.
+Vcc
IcQ
VoQ
IcQ
Figure (7.16). Illustration of the output port voltage biasing problem in the
complementary NPN-PNP common
emitter amplifier of Figure (7.15a).
It is one thing to pull a nasty trick on an unsuspecting circuits student. It is quite another thing to circumvent the problem pragmatically with circuit hardware. To this end, a strategy involving the use of common mode feedback is typically exploited. In this design approach,
a replica of the complementary NPN-PNP stage is incorporated as a means of monitoring a prescribed voltage that is linearly proportional to the desired quiescent output voltage. This monitored voltage is compared to a reference voltage, whose value is usually the desired quiescent
output. The response to the difference between monitored and reference voltages is suitably fed
back to the NPN-PNP stage to achieve the desired static output. We shall delay a detailed
discussion of common mode feedback to another time.
The final issue worthy of mention relates to the small signal analysis of the active PNP
load in the amplifier of Figure (7.15a). The critically important point here is that the model in
Figure (7.15b) is topologically identical to the models we have invoked for NPN transistors. In
particular and despite the fact that the net collector current rolls out of the PNP device, the CCCS
whose value is βacpI remains directed from the collector -to- the emitter terminals of the subject
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transistor. Moreover, the small signal base current, I, continues to flow into the base terminal of
the PNP model, despite the fact that the net PNP base current flows out of the base lead.
7.4.0. COMMON COLLECTOR AMPLIFIER
The second canonic cell of analog bipolar junction transistor technology that we shall
investigate is the common collector amplifier, which is otherwise known as the emitter follower.
The common collector stage is routinely enlisted as a voltage buffer between a preceding gain
stage (such as a common emitter amplifier) and a low impedance load (perhaps a small resistance or a large capacitance) that the gain stage is compelled to drive and deliver reasonable I/O
gain. Figure (7.17) diagrams the NPN and PNP bipolar transistor versions of this cell. In these
diagrams, it is understood that the transistors operate in their active regimes for all values of the
applied signal source voltage, Vs. Moreover, we see that the input signal is applied to the base
terminal of the utilized transistor, as is indeed the case in the common emitter cell. We shall
learn that the input resistance, Rinc, of an emitter follower is reasonably large, which is why its
applied input signal is generally couched as a voltage. Unlike the common emitter stage, whose
output is taken at the collector port, the output response of the follower is extracted at the emitter. In the case of a diode-connected transistor, we have already witnessed a small resistance
seen looking into the emitter terminal. A similar fate awaits the output resistance, Routc, of an
emitter follower, which is why the output response of a common collector amplifier is invariably
taken as a signal voltage.
+Vcc
Rl
+Vcc
Routc
Rs
Rs
Vi
+
−
Vbb
+
Vi
+
Vs
Routc
Rinc
Vo
Vs
−
Vo
−
Rl
Rinc
Vbb
−
+
(a).
(b).
Figure (7.17). (a). Basic schematic diagram of a common collector amplifier utilizing an NPN bipolar junction transistor. (b). Basic schematic diagram of a common collector amplifier
utilizing a PNP BJT. In both diagrams, Rinc and Routc respectively symbolize the common collector (emitter follower), driving point input and output resistances.
It is important to underscore the fact that the collectors of the two followers in Figure
(7.17) are returned to signal ground. Electronic circuit designers appear to be commonly
tempted to introduce a resistance in series with the collector terminal, primarily to preclude
excessive quiescent voltage drop across the collector-emitter terminals of the utilized transistor.
Such a design tack is poor design practice. Aside from increasing the circuit power dissipation,
resistances in the collector lead of an emitter follower give rise to an inductive output impedance
that can interact with external load capacitances. This interaction can manifest ringing
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(underdamped) and/or long settling time output responses to input step or otherwise abrupt input
excitations.
7.4.1. LOW FREQUENCY FOLLOWER I/O CHARACTERISTICS
Because we anticipate that the emitter follower presents a low output resistance to a
load incident with its emitter output port, we elect a macromodel premised on a Thévenin
architecture at the output port. In the model of Figure (7.18a), Act symbolizes the Thévenin voltage gain of the common collector stage; that is, it is the I/O signal voltage gain, Vos/Vs, with the
load resistance, Rl, removed or equivalently, Rl open circuited. In the model depicted in Figure
(7.18a), Routc is the driving point output resistance of the follower, while Rinc is, of course, the
driving point input resistance of the network.
Rinc
Rs
Routc
Vis
+
Vs
Routc
Vos
+
ActVs
Rinc
−
Rl
−
(a).
Rs
+
Vs
−
Vis
rb
+ I
rπ
V
−
Routc
βac I
0
ro
(βac+1)I
Vot
(b).
Figure (7.18). (a). Thévenin output port form of emitter follower macromodel.
(b). Small signal model used in the computation of the
Thévenin voltage gain, Aot = Vot/Vs, of the emitter follower.
Using the low frequency transistor model provided in Figure (7.2a), the model
appropriate for the calculation of the Thévenin voltage gain is the construction in Figure (7.18b).
In this diagram, the load resistance, Rl, which formerly returned the emitter terminal to ground, is
removed to enable the computation of the Thévenin (or open circuit) output port voltage, Vot.
The equations of equilibrium, cast in terms of the branch currents delineated in the subject model
are
V
ot
V
s
=
=
( β ac + 1) ro I
( Rs + rb + rπ ) I + ( β ac + 1) ro I
(7-56)
,
which lead immediately to an emitter follower Thévenin voltage gain, Act, of
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ct
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V
1
ot =
.
R +r +r
V
s
1+ s b π
=
A
Canonic Analog MOS Cells
(7-57)
( β ac + 1) ro
The interesting aspects to this expression is that the Thévenin gain is a positive number that is
less than one and indeed very close to one, since (βac + 1)ro is likely to be much larger than the
resistance sum, (Rs + rb + rπ ). Because the Thévenin voltage gain is the maximum possible voltage gain that can be realized for any load termination, the actual voltage gain, say Avc, of the
common collector stage, is necessarily constrained to be less than one. While the actual voltage
gain is less than one, Figure (7.18a) shows that this voltage gain closely approaches Act if Rl is
substantially larger than the output resistance, Routc, of the emitter follower. The fact that the actual voltage gain, Avc, can approach the Thévenin gain, Act, motivates the amplifier terminology,
“emitter follower”; that is, the voltage signal response at the emitter (output) port of a common
collector amplifier “follows” the input signal applied to the amplifier.
The emitter follower macromodel is completed by evaluating the driving point input
and output resistances, Rinc and Routc, respectively. To this end, the previously used mathematical
ohmmeter method applied to the models offered in Figure (7.19) applies. In Figure (7.19a),
rb
rb
Vx
Ix
−
I
Ix
rπ
+
Rinc
Ix−I
I+βacIx
rπ
Rs
ro
βac Ix
I
βac I
Ix
Routc
Rl
ro
Ix+(βac+1)I
Ix+I
+
Vx
Ix
−
(a).
(b).
Figure (7.19). (a). Small signal model for computing the input resistance, Rinc, of a common collector amplifier.
(b). Small signal model used to compute the output resistance, Routc, of an emitter follower.
V
x
0 =
(
)
( )
R (I − I ) + r (I + β I )
l
x
o
ac x
= r +r I +R I −I
b
π x
l x
.
(7-58)
Upon eliminating current I from the two foregoing equations, we arrive at
V
R
= x = r +r + β +1 r R ≈ β +1 R ,
inc
b
ac
o l
ac
l
π
I
x
(
)(
) (
)
(7-59)
where the approximation exploits the presumptions of large βac and large ro. We note that while
the common collector input resistance is not accurately predictable owing to its direct dependence on parameter βac, the input resistance can be very large for large βac and reasonable load
resistance (Rl) values. Of course, a major reason underlying this large input resistance is that the
input port of a common collector configuration is formed by the base terminal of the utilized
transistor. This base lead conducts very small signal current and indeed, its signal current is (βac
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+ 1)-times smaller than the current conducted by the emitter lead, where the load resistance is
incident.
In Figure (7.19b),
V
x
0 =
(
)
= − R +r +r I
s
b
π
(7-60)
,
( Rs + rb + rπ ) I + ro ( I x + ( β ac + 1) I )
which, upon elimination of current variable I, readily a common collector output resistance, Routc,
of
⎛R +r +r ⎞
V
R +r +r
R
= x = r ⎜ s b π ⎟ ≈ s b π .
(7-61)
outc
o ⎜ β +1 ⎟
I
β
+1
x
ac
ac
⎝
⎠
As in the case of the emitter follower input resistance, the accurate numerical prediction of the
emitter follower output resistance is a challenge owing to the nominally inverse sensitivity of this
resistance to gain parameter βac. But because of this inverse relationship to βac, which is invariably a large number, the output resistance, Routc, is small.
In view of (7-61), the voltage gain of the emitter follower can now be expressed as an
explicit function of source resistance, load resistance, and transistor small signal parameters. In
particular, from Figure (7.18a) and (7-57),
A
vc
=
V
⎛
R
⎞
os = A ⎜
l
⎟ =
ct ⎜ R + R
⎟
V
s
outc ⎠
⎝ l
r R
o
(
l
R +r +r
r R + s b π
o l
β +1
)
.
(7-62)
ac
The result at hand naturally confirms a voltage gain that is positive (no phase inversion) and less
than unity. Moreover, the expression shows that the I/O voltage gain approaches unity for
( β ac + 1) ( ro Rl )
>> R + r + r .
(7-63)
s
b
π
Although (7-63) is routinely satisfied, it is appropriate to interject that in certain, somewhat extreme cases, the assumption implicit to this constraint may be invalid. In particular, emitter
followers are most likely used whenever the signal source resistance is very large and/or the load
resistance is very low. In particular, a prime reason for deploying an emitter follower in an
electronic system is mitigation of the gain degradation incurred when small load resistances are
driven by very high signal source resistances. We should note that with source resistance Rs
large and/or load resistance Rl small, doubts pervade the ability to satisfy (7-63) easily.
7.4.2. EMITTER FOLLOWER WITH ACTIVE LOAD
In an attempt to encourage an emitter follower voltage gain that closely tends toward
one, the passive load resistance, Rl, in the schematic diagram of Figure (7.17a) can be supplanted
by an active load, as is displayed in Figure (7.20a). In the subject figure, the active load is
formed of transistor Ql and emitter degeneration resistance Ree, although in low voltage applications, Ree can be replaced by a short circuit. Of course, Ql is biased, with the help of voltage
source, Vbias, in its active regime. And since no signal is inserted into the base port of the Ql
subcircuit, said subcircuit behaves as a constant, time-invariant current sink whose shunt resistance is the resistance, Rol, seen looking into the collector of Ql. This observation is crystallized
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by the diagram in Figure (7.20b), which models the Ql subcircuit as a simple constant current
element, Ik, in shunt with a resistance of value Rol.
+Vcc
+Vcc
Rs
Vi
+
Rs
Vs
−
+
Routc
Rinc
Ik
Vbb
−
Vbias
Vi
+
Q
Rol
Vs
Routc
−
Vo
Q
Rinc
+
Vo
Vbb
−
Ql
Ik
Rol
Ree
(a).
(b).
Figure (7.20). (a). Circuit schematic diagram of a common collector amplifier with active load. (b).
Circuit of (a) with the active load represented by a Norton type model consisting of the
quiescent current, Ik, conducted by Ql and the shunting resistance, Rol, seen looking
into the collector of Ql.
The foregoing active load observations are critically important to circuit design issues
for three reasons. First, because Ik is a constant, Norton equivalent current, the small signal
model of the Ql subcircuit in the network of Figure (7.20b) collapses to a simple two terminal
resistance of value Rol. Second, because Rol is likely to be large in that it is the resistance viewed
looking into the collector port of the Ql subcircuit, the emitter follower device, transistor Q, is
effectively biased to a quiescent emitter current of Ik. To the extent that current Ik conducted by
Ql has been thermally stabilized and desensitized with respect to uncertainties in vagarious
transistor parameters, this means that the quiescent current conducted by Q (recall that the
collector and emitter currents are nearly identical in the active regime) is also predictable and
stable. In other words, it is unnecessary to exercise extreme care in the biasing of transistor Q if
the biasing of the active load transistor has already been executed with appropriate design care.
Third, since resistance Rol is likely to be far larger than any practical passive resistance that can
be inserted into the emitter lead, the I/O voltage gain, Avc = Vos/Vs, is invariably closer to one
than is the gain achieved with a simple passive load resistance.
Because the base and the emitter of Ql are returned to ground, the active load in question emulates a two terminal subcircuit, as Figure (7.20b) depicts. No mystery surrounds an
analytical expression for the resistance, Rol, associated with this load subcircuit, for its calculation derives from a mathematical ohmmeter excitation of a model that is topologically identical
to the common emitter configuration investigated in Figure (7.6a). In particular, Rol derives directly from (7-19), provided the parameters associated with transistor Ql are factored into this
resistance expression. In particular,
⎛
⎛
β acl Ree ⎞
β acl Ree ⎞
⎟r + R
⎟ r , (7-64)
R = ⎜1 +
r +r
≈ ⎜1 +
ol
ee bl
πl
⎜
⎜
R + r + r ⎟ ol
R + r + r ⎟ ol
ee bl
ee bl
πl ⎠
πl ⎠
⎝
⎝
(
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where no source resistance term appears because the Vbias source is introduced in Figure (7.20a)
without a Thévenin source resistance. Observe that if Ree = 0, Rol = rol, which is still a large
resistance, but not nearly as large as that evidenced with emitter degeneration in transistor Ql.
In the interest of completeness, the input resistance, Rinc, in Figure (7.20a) derives from
(7-59) with load resistance Rl in that relationship replaced by the resistance, Rol, in (7-64).
Specifically,
(
)(
) (
)(
)
= r +r + β +1 r R
≈ β +1 r R .
(7-65)
b
π
ac
o ol
ac
o ol
Since Rol is invariably much larger than the original passive load termination, Rl, the active load
enhances the observable input resistance, in addition to rendering an I/O voltage gain that more
closely approaches unity.
R
inc
7.4.3. BUFFERED COMMON EMITTER AMPLIFIER
The stereotypical application of a common collector amplifier is that of a voltage buffer
inserted between a high impedance circuit node and a low impedance load. But when the low
impedance load happens to be a significant capacitance, the inserted common collector stage becomes an effective broadbanding vehicle, which is to say that it can extend the bandwidth of the
circuit realized without benefit of common collector buffering. The bandwidth of the circuit, as
we shall discuss forthwith, is the signal frequency range over which the I/O gain of a circuit is
maintained nominally constant. Since constant gain, independent of signal frequency, enables
the amplifier to process the applied input signal faithfully to within only a factor of a predictable
constant, the circuit bandwidth is a measure of the amount of information that can be processed
reliably and predictably by the circuit. The higher the bandwidth, the higher is the amount of
such information that can be processed, transmitted or otherwise utilized in an electronic system.
A case in point is the complementary NPN-PNP common emitter stage in Figure
(7.21a) in which the load that the amplifier drives is the capacitance, Cl. The biasing difficulties
discussed earlier in conjunction with this stage remain, but these will be tacitly ignored with the
understanding that some sort of voltage control network needs to be implemented to render the
biasing of the subject network reliable and practical. We shall assume that capacitance Cl establishes the dominant pole of the network. The dominant pole descriptive attached to Cl means
that all other device and circuit capacitances give rise to time constants that are substantially
smaller than the time constant forged by Cl. Consequently, these secondary capacitances can be
ignored in the course of studying the high frequency response of the circuit.
The Thévenin output voltage of the first stage is determined by removing capacitance
Cl; that is, we open circuit the load by setting Cl to zero. This Thévenin output voltage response
has effectively been determined in (7-53) as the voltage, AveVs, since Ave addresses the stage gain
without an extrinsic load. From (7-53) and Figure (7.21a),
α acn ⎛⎜ Rouen Rouep ⎞⎟
⎝
⎠ ,
⎛R
⎞ ≈ −
(7-66)
A = −g
R
ve
men ⎜⎝ ouen ouep ⎟⎠
R
e2
transconductance gmen derives from (7-54) as
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+Vcc
Re1
Rb1
Rout
QP
+
Vbb2
Rouep
−
Vo
Rouen
Rs
Vi
+
Cl
QN
Vs
−
Rine
+
Vbb
Re2
−
(a).
+Vcc
Re1
Rout
Rb1
QP
+
Vbb2
Rouep
−
Vi2
Rinc
Rouen
Rs
Vi1
+
Routc
Ik
Vbias
QN
Q
Rol
Ql
Vs
−
+
Vo
Cl
Rine
Re2
Ree
Vbb
−
(b).
Figure (7.21). (a). Circuit schematic diagram of a common emitter amplifier
driving a load capacitance, Cl, which is incident with its output
port. (b). Common emitter amplifier with an actively loaded
emitter follower buffer interposed between the output port of the
common emitter unit and the load capacitance.
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⎛
⎞⎛
⎞
R
e2 ⎟
⎟⎜ 1 −
⎜ r + R ⎟⎜
β acn ron ⎟⎠
ee ⎠⎝
⎝ on
β acn ⎜
g
=
J. Choma
r
on
≈
β acn
,
(7-67)
r + β
+1 R
+r + β
+1 R r
πn
acn
e2
πn
s
bn
acn
e2 on
resistance Rouep remains given by (7-52), and resistance Rouen is, from (7-55),
⎛
⎞
β acn Re2
⎟r + R
(7-68)
.
= ⎜1 +
R
R +r +r
ouen
e2
s
bn
πn
⎜
R + R + r + r ⎟ on
πn ⎠
e2
s
bn
⎝
The construction of the Thévenin equivalent circuit for the output port of the first stage is completed by noting a Thévenin resistance seen by capacitance Cl of (Rouen||Rouep).
men
)(
(
R +r
)
(
(
)
)
Figure (7.22) displays the Thévenin macromodel –complete with capacitive load attached– of the output port for the common emitter stage of Figure (7.21a). A casual inspection
of this simple equivalent circuit confirms a steady state common emitter voltage gain, Avu(jω) of
Rouen||Rouep
Vos
+
AveVs
Cl
−
Figure (7.22). Macromodel of the output port of the common emitter stage in Figure (7.21a).
1
⎡
⎤
⎛R
⎞
⎢
⎥
g
⎜ ouen Rouep ⎟
V
jωC
men
⎝
⎠ . (7-69)
l
⎥ = −
A (jω) = os = A ⎢
vu
ve
⎢ 1
V
⎞C
⎛
⎞⎥
1 + jω ⎛⎜ R
R
s
⎟ l
⎢ jωC + ⎜⎝ Rouen Rouep ⎟⎠ ⎥
ouen
ouep
⎝
⎠
⎢⎣
⎥
l
⎦
We have appended subscript “u” to the gain symbol in the above relationship to denote an
uncompensated voltage gain in the sense that compensation in the form of an inserted emitter
follower has yet to be implemented.
Equation (7-69) can be cast into the classic, single pole, lowpass form,
A (j0)
A (jω) = vu
,
vu
jω
1+
B
(7-70)
u
where
A (j0) = − g
vu
⎛R
men ⎜⎝ ouen
R
⎞ = A
ouep ⎟⎠
ve
(7-71)
is the voltage gain at zero frequency, wherein capacitance Cl functions as an open circuit (infinitely large branch impedance). By “lowpass,” is meant an ability of the electrical network to
operate with nonzero gain on signals whose frequency spectrum embraces all frequencies
extending down to or at least near to zero. The indicated circuit metric, Bu, is
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1
=
,
(7-72)
⎛R
⎞
R
C
⎜ ouen ouep ⎟ l
⎝
⎠
where (Rouen||Rouep)Cl is recognized as the time constant associated with Cl. We note by (7-70)
that
u
A (jB ) =
vu
u
A (j0)
vu
1 + j1
=
A (j0)
vu
2
(7-73)
;
|Avu(jω)| (dB)
|Avu(j0)|
3-dB
op
Sl
e
=
−
20
dB
ec
/d
Amplifier
Passband
e
ad
ω
0 dB
Bu
ωu
Figure (7.23). Approximate frequency response of the actively loaded common emitter
amplifier shown in Figure (7.21a).
that is, the gain magnitude at ω = Bu is a factor of root two smaller than the zero frequency value
of the circuit voltage gain. Since root two equates to approximately three decibels 1 , we say that
the gain at frequency Bu is 3-dB below the zero frequency gain. Parameter Bu is then termed the
3-dB bandwidth of the network, which is meant to impart that the gain magnitude is constant at
its zero frequency value to within an error, or a difference, of about 3-dB from zero frequency
through frequency Bu. Figure (7.23) exemplifies the so-called frequency response of the subject
lowpass network at hand. This graph plots the gain magnitude -versus- radial signal frequency ω
and in the process, the graph defines the zero frequency gain, Avu(j0), the passband, which extends from zero frequency through Bu, of the circuit where the gain remains nominally constant
at its zero frequency value, and the 3-dB bandwidth, Bu. Observe that nonzero gain prevails even
at zero frequencies, thereby confirming the lowpass nature of the considered network.
Since resistances Rouen and Rouep are large, the time constant associated with capacitance
Cl in (7-72) is large, whence an unfortunately limited 3-dB bandwidth. We observe that the zero
frequency gain in (7-71) is directly proportional to the shunt resistance combination,
(Rouen||Rouep), while the 3-dB bandwidth in (7-72) is inversely proportional to the same shunt
resistance. A figure of merit commonly adopted to stipulate the general quality of the frequency
response of an amplifier is the gain-bandwidth product. This metric is the product of the magnitude of the zero frequency gain and the 3-dB bandwidth and thus, it is independent of resistance
1
The decibel value of a positive, negative, or complex number, N, is 20 log
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(Rouen||Rouep). For the uncompensated structure of Figure (7.21a) the gain-bandwidth product,
say GBPu, is
⎛R
⎞
g
R
g
men ⎜⎝ ouen ouep ⎟⎠
GBP = A (j0) B =
= men .
(7-74)
u
vu
u
C
⎛R
⎞
l
⎜ ouen Rouep ⎟ Cl
⎝
⎠
Thus, the gain-bandwidth product is dependent on only the load capacitance and the
transconductance associated with the common emitter transistor. Because the gain-bandwidth
product is independent of the shunt resistance, (Rouen||Rouep), increasing this net resistance to enhance gain by a certain factor is automatically met by a 3-dB bandwidth that is reduced by the
same factor and vice versa.
+Vcc
Rouen||Rouep
Vi2
Q
+
Rinc
AveVs
Routc
−
Vi2Q
Ik
+
−
Rol
Vbias
Vo
Ql
Cl
Ree
(a).
Rouen||Rouep
+
AveVs
Routc||Rol
Vi2s
+
Rinc
Act AveVs
−
Vos
Cl
−
(b).
Figure (7.24). (a).Emitter follower used in the amplifier shown in Figure (7.21b). The
net input signal is fundamentally represented by the Thévenin equivalent circuit prevailing at the output port of the common emitter stage.
(b). Small signal macromodel of the emitter follower stage that couples
the load capacitance into the common emitter amplifier of Figure
(7.21b).
Figure (7.21b) is essentially the same amplifier structure as that shown in Figure
(7.21a), but with an actively loaded source follower introduced in the signal flow path before the
load capacitor. In view of our Thévenin output port analysis of the common emitter component
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of this amplifier, we can represent the source follower stage in the form shown in Figure (7.24a).
It is to be understood that in this representation, the gain term, Ave, is given by (7-66), the effective (and very large) source resistance of (Rouen||Rouep) derives from (7-52) and (7-68), and the
constant voltage, Vi2Q, is the quiescent value of the voltage developed at the output port of the
common emitter unit. This static voltage must be sufficiently large to ensure turn on of transistor
Q.
Recalling Figure (7.18a), we can now formulate the small signal macromodel of the entire source follower network as the architecture provided in Figure (7.24b). In this structure, we
note that the signal source incident with the emitter follower input port is not simply Vs but is,
instead, AveVs. Of course, the effective source resistance for this stage is the Thévenin resistance
witnessed at the output port of the predecessor common emitter unit. Accordingly, the VCVS in
the output port of the follower macromodel must be ActAveVs, where Act, the Thévenin voltage
gain of the common collector stage considered herewith is, by (7-57),
1
1
(7-75)
A =
,
≈
ct
⎛R
⎞
R
R
⎜ ouen Rouep ⎟ + rb + rπ
ouen ouep
⎠
1+
1+ ⎝
β +1 r
β +1 r
(
ac
(
)o
ac
)o
and we have made use of the likelihood that (Rouen||Rouep) is much greater than (rb + rπ ). We
note that while Act naturally remains a positive number less than one, it may be several percent
below one owing to the fact that (Rouen||Rouep) is, by most standards, a very large effective source
resistance. The macromodel is completed by observing that the Thévenin output port resistance
of the follower is little more than the shunt interconnection of the resistance, Routc, seen looking
into the emitter of common collector transistor Q and the resistance, Rol, presented to the network
by the collector port of the current sinking transistor, Ql. While Rol remains as per (7-64), Routc
in (7-61) modifies to
⎡⎛
⎤
⎞
⎛R
⎞
⎢ ⎜⎝ Rouen Rouep ⎟⎠ + rb + rπ ⎥
⎜ ouen Rouep ⎟
R
= r ⎢
(7-76)
⎥ ≈ ro ⎜
⎟.
outc
o
β ac + 1
⎢
⎥
⎜ β ac + 1 ⎟
⎝
⎠
⎣⎢
⎦⎥
Because (Rouen||Rouep) is an invariably large resistance, the output resistance of the present follower is likely not to be as small as the output resistance of more traditional followers whose signal source resistances are only moderately large.
With reference to the macromodel in Figure (7.24b), we determine the compensated
voltage transfer function, Avco(jω), to be
A A
ct ve
A (jω) =
.
(7-77)
vco
1 + jω R
R C
(
outc
ol
)
l
Since Act is in the neighborhood of unity (to be sure, it is slightly less than one), the zero frequency I/O voltage gain is almost Ave, which is essentially unchanged from the gain evidenced in
the uncompensated structure. On the other hand, the compensated 3-dB bandwidth, say Bco is
now
1
B
,
=
(7-78)
co
R
R C
(
outc
ol
)
l
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which is certainly larger than 1/RoutcCl. Recalling (7-76),
β ac + 1
1
B
>
>
= β +1 B .
(7-79)
co
ac
u
R
C
⎛
⎞
outc l
⎜ Rouen Rouep ⎟ Cl
⎝
⎠
We thus see that the passband effect of the incorporated emitter follower is to increase the 3-dB
bandwidth of the original, uncompensated emitter follower by a very large factor that is roughly
equal to (βac + 1). And because the zero frequency voltage gain is essentially unchanged by the
appended follower, the gain-bandwidth product of the compensated network correspondingly
increases by the factor of (βac + 1). It should be noted that because of the biasing controls compelled by the actively loaded common emitter amplifier, the actual factor by which emitter follower compensation increases the 3-dB bandwidth and gain-bandwidth product is somewhat less
than the predicted factor of (βac + 1). Nonetheless, the bandwidth improvement is substantial
and is worthwhile writing home about.
(
)
It is important to reflect on our analysis of the buffered common emitter amplifier. Despite the fact that the initially encountered buffered configuration is a new electronic circuit that
seemingly begets a need for extensive analyses to understand its dynamics, we actually did next
to no new circuit analysis. We relied instead on our engineering awareness of, and analytical
experience with, both the common emitter amplifier and the common collector amplifier and
simply re-parameterized our relevant analytical results to fit the requirements of the new topology. In doing so, we not only obviated the grief and misery that accompanies the solution to
intricate algebraic relationships, we garnered several insights –insights that might have been lost
in the quagmire of algebraic manipulations– about the attributes and limitations of the buffered
amplifier. First and foremost, we learned that with a bit of care, the emitter follower can induce
appreciable broadbanding of a common emitter amplifier that is called upon to drive a significant
load capacitance, which is a commonly encountered design circumstance. We learned that when
an emitter follower is driven from a high resistance output port, as is the case in the actively
loaded common emitter cell, the voltage gain of the emitter follower is not assured to be very
near unity, nor is the output resistance of the follower assured to be very small. Moreover, we
came to understand that the interaction of this large output resistance with a dominant load
capacitance results in anemic bandwidth. We leaned further that the gain-bandwidth product of a
dominant pole amplifier is independent of the resistance associated with the time constant resulting from the capacitor that establishes the dominant circuit pole. In plain engineering street talk,
the more gain we design for, the smaller is the bandwidth we achieve. And our study certainly
allows us to surmise that a large gain-bandwidth product is desirable in that it gives the electronic circuit designer headroom with respect to realizing a desired gain and a targeted bandwidth.
7.5.0. COMMON BASE AMPLIFIER
The third canonic cell of analog bipolar junction transistor technology is the common
base amplifier. Like its common collector cousin, the common base circuit is seldom used as a
standalone circuit. Typically, it is used in conjunction with a common emitter stage, either to
boost the output resistance of the common emitter unit or to mitigate the deleterious effects exerted on circuit bandwidth by the base-collector depletion capacitance of the common emitter
stage. Figure (7.25) depicts a simplified schematic diagram of a common base amplifier. When
used in concert with an NPN common emitter amplifier, current IQ in this diagram is the
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quiescent collector current conducted by the common emitter device, while Is is the signal
component of this net collector current. For the case in which IQ and Is derive as output currents
from a common emitter cell, Rs, the effective resistance associated with the signal current applied
to the common base unit, is large. Indeed, it is at least of the order of an Early resistance and if
the common emitter unit boasts emitter degeneration, Rs is considerably larger than the Early
resistance.
+Vcc
Rl
Io
Routb
Vbias
Rinb
IQ
Is
Rs
Figure (7.25). Basic schematic diagram of a
common base amplifier.
The input port of a common base amplifier is formed between ground and the emitter
node. Our experiences with the diode-connected transistor and with the output port of a common
collector amplifier leads us to believe that the driving point input resistance, Rinb, of a common
base stage is small. Accordingly, the input port of a common base network is better suited to receive input signal current than it is input signal voltage. Our common emitter experience also
leads us to project that the indicated common base output resistance, Routb, is large. In fact, Routb
is potentially very large for in effect, the emitter of the common base stage is degenerated in
resistance Rs that, as we have already suggested, is typically at least as large as an Early resistance. It follows that the Norton (current source) architecture is optimally suited for the output
port of the common base macromodel.
7.5.1. LOW FREQUENCY COMMON BASE CHARACTERISTICS
The low frequency, small signal model of the subject common base amplifier is submitted in Figure (7.26), in which branch currents are delineated to facilitate the application of
Kirchhoff’s laws. Of particular immediate interest is the Norton common base current gain, say
Aibn, which, with reference to Figure (7.26), is the signal current ratio, Ios/Is, for a short circuited
load (Rl = 0). Upon writing the equations of equilibrium for the equivalent circuit at hand and
then eliminating current I from these equations, the reader should have little difficulty
demonstrating that the Norton current gain is
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Routb
rb
I
rπ
ro
βac I
Rl
Ios−βacI
Rinb
Ios+I
Is
Ios
Rs
Ios+I−Is
Figure (7.26). Small signal, low frequency equivalent circuit of the
common base stage pictured in Figure (7.25).
⎛ β R
⎞
ac s
⎜
⎟r + R r + r
π
s b
⎜R +r +r ⎟ o
I
π
s
b
⎝
⎠
os
(7-80)
=
=
A
.
ibn
I
⎛
β ac Rs ⎞
s R =0
⎜1 +
⎟r + R r + r
l
π
s b
⎜
R +r +r ⎟ o
π ⎠
s
b
⎝
Obviously, the Norton current gain is smaller than one, which is hardly surprising since the signal source current is essentially transistor emitter current, while the signal current response flows
in the collector of the transistor. We recall from (7-4) that the collector current is always smaller
than is the emitter current since the latter current is actually the sum of collector and base currents. While the Norton current gain is always less than one, (7-80) confirms that it closely approaches one if resistances Rs and ro are large. In particular,
I
β ac
= os
≈
= α .
(7-81)
A
ibn
ac
I Rl =0
β +1
(
)
(
s
Large R , r
s o
)
ac
where (7-23) is invoked. In concert with our observation of an emitter current that is always larger than its corresponding collector current, it is interesting to observe in Figure (7.26) that large
Rs renders the signal source current, Is, identical to the signal component of net emitter current,
while large ro, forces the output current response, Ios, to flow exclusively in the transistor collector.
The output resistance, Routb, of the common base amplifier can be determined via traditional mathematical ohmmeter measures. Alternatively, we can test the circuit insights we have
garnered to this juncture by adapting the expression for the common emitter output resistance,
Route, in (7-19). Equation (7-19) derives from an analytical consideration of the model in Figure
(7.6). A comparison of that model with the common base structure offered in Figure (7.26) highlights the following observations. First, current Is, which is an independent signal source, would
necessarily be set to zero in the course of determining Routb by conventional ohmmeter methods.
This action leaves resistance Rs in Figure (7.26) as the effective emitter degeneration element and
as a result, Ree, the degeneration element in the common emitter unit is now Rs. Second, the
common emitter amplifier shows a source resistance of Rs in its base terminal, whereas the
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common base structure returns the base of its utilized transistor to ground. Thus, Rs in the common emitter unit now remands to zero in the common base stage. In a word, the Route expression
in (7-19) adapts to become Routb if Ree in (7-19) is replaced by Rs and Rs in (7-19) is set to zero.
The result is
⎛
β ac Rs ⎞
⎟r + R r + r
(7-82)
R
= ⎜1 +
≈ β +1 r ,
outb
s b
ac
o
π
⎜
R +r +r ⎟ o
s
b
π ⎠
⎝
where the approximation reflects the assumptions of large Rs and large ro. We take note of the
fact that for large Rs and ro, the output resistance is potentially huge. This attribute is notable in
several electronic system applications. On such application entails the realization of high
performance active filters that exploit transconductors terminated in capacitive loads to achieve
an output response that integrates the applied input signal[6]-[7].
(
) (
)
The evaluation of the input resistance, Rinb, of the common base stage requires a bit
more diligence than does the foregoing output resistance computation. To be sure, the input
resistance of the common base amplifier is analogous to the output resistance of the previously
considered common collector stage in that both of these resistances present themselves at the
emitter terminal of the considered transistor. Unfortunately, the common collector stage, unlike
the present common base topology, does not have a resistance in series with the collector lead.
This slight complication mandates the use of the mathematical ohmmeter method, as diagrammed in Figure (7.27). An analysis of this network produces
rb
I
rπ
βac I
Ix
ro
Ix+(βac+1)I
Rinb
Rl
Ix+I
+
Ix
Vx
−
Figure (7.27). Equivalent circuit used in the evaluation of the driving point input resistance, Rinb, of the common base
amplifier in Figure (7.25).
(o
⎛r +r ⎞
⎜ b π ⎟
l ⎜ β + 1⎟
⎝ ac
⎠
α R
r +R
R
inb
=
1−
)
ac l
≈
r +r
π ,
b
β +1
(7-83)
ac
⎛r +r ⎞
r +R +⎜ b π ⎟
o
l ⎜ β + 1⎟
⎝ ac
⎠
where the indicated approximation reflects the impact of a large Early resistance, ro. As expected, the input resistance is small since it is nominally inversely proportional to (βac + 1). A
comparison of this relationship with the output resistance expression, (7-61), for the common
collector stage inspires confidence in the result at hand. In particular, if Rl in (7-83) is set to zero
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to mirror the return of the collector lead to ground in the emitter follower and if in addition, rb in
(7-83) is replaced by the resistance sum, (Rs + rb), to account for the signal source resistance in
the emitter follower, (7-83) mirrors the resistance expression in (7-61).
Is
Rs
Rinb
Aibn Is
Routb
Rl
Ios
Figure (7.28). Small signal I/O macromodel for the common base amplifier in
Figure (7.25). Input resistance, Rinb, output resistance Routb, and
Norton current gain, Aibn, are given respectively by (7-83), (7-82),
and (7-80).
The I/O macromodel of the common base stage can be drawn as the topological structure appearing in Figure (7.28). In the interest of engineering completeness, this macromodel
confers a common base I/O current gain, Aib, of
⎛ β R
⎞
ac s
⎜
⎟r + R r + r
π
s b
⎜R +r +r ⎟ o
⎛ R
⎞
I
⎝ s b π ⎠
outb ⎟ =
. (7-84)
A = os = A ⎜
ib
ibn ⎜ R
+R ⎟
I
⎛
⎞
β
R
s
l⎠
⎝ outb
ac s
⎜1 +
⎟r + R r + r + R
π
s b
l
⎜
R +r +r ⎟ o
π ⎠
s
b
⎝
We observe no phase inversion of this current gain and, as we had previously surmised, the current gain is smaller than one. However, Aib nears unity for large ro and/or large βac. We note that
for a large Early resistance, ro, and a large source resistance, Rs, witnessed by the common base
unit, Ios/Is ≈ βac/(βac+1) Δ αac, which is, of course, very close to one.
(
)
(
)
In light of the foregoing general performance metrics, the common base and common
collector amplifiers can be viewed as duals of one another. Recall that the common collector
stage boasts high input resistance, low output resistance, and a non-phase inverted voltage gain
that, while less than one, approaches one for large load resistance and large current gain βac. In
contrast, we have seen that the common base amplifier delivers low input resistance, high output
resistance, and a positive current gain that, while less than one, tends toward one for low load
resistance and large βac. Whereas we refer to the common collector configuration as a voltage
buffer, we might therefore be moved to reference its common base brethren as a current buffer.
7.5.2. COMMON EMITTER-COMMON BASE CASCODE
As we noted earlier, the common base stage is often used in conjunction with a common emitter amplifier to forge bandwidth improvements or to enhance driving point output resistances. To this end, a commonly encountered topology is the common emitter-common base
cascode amplifier, which is presented schematically in Figure (7.29a). In this diagram, Q1 and
Q2 are essentially connected in series with one another. These devices are matched monolithic
transistors, save for the fact that circuit bandwidth optimization may require that these two devices possess different base-emitter junction areas. Transistor Q1, which functions as the common emitter component of this cascode, utilizes emitter degeneration (Ree) although in actual
practice, this resistance might not be deployed. Of course, both transistors operate in their active
domains and conduct nominal collector currents of Io, for which the quiescent component is IoQ.
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The signal component of current Io, which arises in response to applied signal voltage Vs, is Ios.
In the paragraphs that follow, we shall rely largely on the electronic circuit insights we have
assimilated thus far to analyze the cascode configuration.
+Vcc
Rl
Io = IoQ+Ios
Vo = VoQ+Vos
Routb
Vbias
Rl
Q2
Ios
Vos
Routb
Rinb
Route
Rs
Vi
+
Q2
Q1
Rinb
Vs
−
+
Vbb
Rine
Ree
Route
gmeVs
−
(a).
(b).
Figure (7.29). (a). Schematic diagram of a common emitter-common base cascode amplifier.
(b). Macromodel of the amplifier in (a) under signal conditions. The constant
voltage supplies have been replaced by short circuits, while the common emitter
amplifier formed by transistor Q1 has been represented by its output port macromodel in accordance with Figure (7.7a).
The input resistance presented to the signal source by the input port of the common
emitter unit derives from (7-15). In that relationship, the transistor parameters, rb, rπ, ro, and βac,
refer to transistor Q1, while Rl, which here symbolizes the effective collector load resistance imposed on the output port of the common emitter stage, is Rinb, the input resistance of the common
base stage formed of transistor Q2. Accordingly and from (7-15),
⎛ β r
⎞
⎤
R
r +R
= r + r + ⎜ ac1 o1 + 1 ⎟ ⎡ R
ine
b1 π 1 ⎜ r + R
inb ⎦
⎟ ⎣ ee o1
(7-85)
inb
⎝ o1
⎠
(
≈ r
(
)
)
+r + β
+1 R ,
π1
ac1
ee
where the approximation makes use of the likelihood that ro1 >> Rinb and ro1 >> Ree. In turn,
Rinb, the input resistance seen looking into the emitter of the common base transistor, Q2, is,
from (7-83),
b1
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( o2
r
R
inb
⎛r + r ⎞
⎜ b2 π2 ⎟
l ⎜ β
+1⎟
⎝ ac2
⎠
α R
+R
=
)
r +r
≈ b2 π2 ,
+1
β
ac2 l
1−
J. Choma
(7-86)
ac2
⎛r + r ⎞
r + R + ⎜ b2 π2 ⎟
o2
l ⎜ β
+1⎟
⎝ ac2
⎠
Because Rinb is very small in comparison to the Early resistance of Q1, it exerts negligible effect
on the input resistance of the cascode configuration. We note further that while emitter
degeneration resistance Ree is strictly unnecessary, it does bolster the input resistance, thereby
encouraging the input port of the cascode network to receive signal excitation in the form of a
voltage. Moreover, we recall that Ree is also advantageous from the standpoint that it desensitizes the forward transconductance of the common emitter amplifier with respect to key transistor parameters.
The analysis of the cascode configuration at hand continues by examining the topology
of Figure (7.29a) under exclusively signal (to be sure, “small” signal for reasonable I/O linearity)
circumstances. To this end, Figure (7.29a) collapses to the structure in Figure (7.29b), where the
battery voltages in the former schematic diagram are replaced by their signal values of zero voltage; that is, voltages Vcc and Vbb become short circuits. Of critical importance is the fact that in
Figure (7.29b) we have elected to model the small signal dynamics of the common emitter output
port by the Norton equivalent network comprised of VCCS gmeVs in shunt with resistance Route.
Of course, Route represents the driving point output resistance of the common emitter stage. From
(7-19), this resistance is
⎛
⎞
β R
ac1 ee
⎟r + R
R
R +r +r
= ⎜1 +
oute
ee
s
b1
π1
⎜
R + R + r + r ⎟ o1
ee
s
b1
π1 ⎠
⎝
(7-87)
⎛
⎞
β R
ac1 ee
⎟r .
≈ ⎜1 +
⎜
R + R + r + r ⎟ o1
ee
s
b1
π1 ⎠
⎝
The transconductance parameter, gme, is given by (7-22), with the understanding that all transistor parameters therein refer to transistor Q1. In the interest of clarity, we write herewith
⎛ r
⎞⎛
⎞
R
o1
ee ⎟
⎟⎜1 −
β ⎜
ac1 ⎜ r + R ⎟ ⎜
β r ⎟
β
α
ee ⎠ ⎝
ac1 o1 ⎠
⎝ o1
ac1
g
=
≈
≈ ac1 . (7-88)
me
R
r + β
+1 R
R +r +r + β
+1 R r
ee
(
s
b1
π1
(
ac1
)(
ee o1
)
)
(
π1
)
ac1
ee
Recall that the small signal current gain of the generic common base stage shown in
Figure (7.25) is given by (7-84). When applied in the context of the cascode schematic in Figure
(7.29b), we see that
⎛
⎞
β R
ac2 oute
⎜
⎟r + R
r +r
oute b2
π2
⎜R
+ r + r ⎟ o2
I
⎝ oute b2 π2 ⎠
os
=
≈ α
A =
, (7-89)
ib
ac2
g V
⎛
⎞
β
R
me s
ac2 oute
⎜1 +
⎟r + R
+R
r +r
oute b2
π2
l
⎜
+ r + r ⎟ o2
R
oute
b2
π2 ⎠
⎝
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where the indicated approximation is valid because Route, the output resistance of the common
emitter cell that drives the common base amplifier, is large. It is conceptually important to
understand that this current gain is approximately independent of the terminating load resistance,
Rl, because the driving point output resistance, Routb of the common base stage is very large. In
particular, Figure (7.29b) and (7-82) deliver
⎛
⎞
β ac2 Route
⎟r + R
(7-90)
R
r +r
= ⎜1 +
≈ β
+1 r .
outb
oute b2
π2
ac2
o2
⎜
+ r + r ⎟ o2
R
oute
b2
π2 ⎠
⎝
(
) (
)
The voltage gain of the common emitter-common base cascode circuit follows directly
from the fact that the output signal voltage, Vos, is simply –IosRl. Using (7-89),
V
I R
α α R
os = − os l = − g R A ≈ − g R α
(7-91)
≈ − ac1 ac2 l ,
me l ib
me l ac2
V
V
R
s
s
ee
where we have invoked our previously delineated approximations surrounding transconductance
parameter gme and common base current gain Aib. The very large output resistance reason
underlying the nominal independence of the cascode current gain on load resistance is precisely
the same reason that the cascode voltage gain is virtually directly dependent on this terminating
load resistance. But to the extent that both resistances Rl and Ree are on chip elements, the voltage gain can be tightly controlled in a monolithic fabrication process because it is proportional to
a resistance ratio, which in this case is Rl/Ree.
7.5.2.1. Mitigation Of Miller Capacitance
Equation (7-91) confirms that the I/O voltage gain of a common emitter-common base
cascode is within a factor of αac2 (which is very nearly unity) of the voltage gain supplied by an
emitter-degenerated, common emitter cell whose collector is terminated in a simple load resistance of Rl. Clearly, the compound configuration offers no voltage gain benefits above those
provided by an amplifier implemented without a common base cascode insertion into the collector lead of the common emitter cell. But it does offer a transconductance gain advantage in that
the very high output resistance afforded by a common emitter-common base cascode renders the
output current response almost independent of the load resistance. High output resistance
notwithstanding, perhaps the most significant potential advantage of the cascode topology lies in
the arena of circuit broadbanding. The bandwidth of a circuit is fundamentally related to the inverse sum of the time constants associated with the energy storage elements implicit to the circuit topology and the models of the active devices embedded therein. While numerous design
challenges and issues accompany broadbanding tasks, it is generally true that progressively
smaller network time constants lead to correspondingly larger bandwidths. The common emitter-common base cascode attempts to reduce one of the time constants evidenced in a common
emitter amplifier; namely the time constant associated with the base-collector capacitance, Cμ, of
the common emitter, or driving, transistor.
In order to gain an appreciation of the effect that a cascode of the form shown in Figure
(7.29a) has on 3-dB bandwidth, we return to the basic amplifier schematic of Figure (7.3a) and
explicitly incorporate the base-collector capacitance, as depicted by the dashed external branch
capacitance in Figure (7.30a). In order to show this depletion capacitance explicitly in a basic
schematic format, we have taken the liberty of extracting the base resistance from the device
model and have lumped this resistance into the Thévenin source resistance. The corresponding
small signal model is offered in Figure (7.30b), where because of our present explicit focus on
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base-collector capacitance, the base-emitter and substrate capacitances of the transistor are not
included. It should be clearly understood that we are not implying that these latter two
capacitances insignificantly affect the observable circuit bandwidth. Instead, we are ignoring
these capacitances because we are focusing only on the base-collector depletion capacitance,
whose effects are ostensibly mitigated by the incorporation of a cascode stage in tandem with a
driving common emitter amplifier. The model is further approximated by our tacit neglect of the
Early resistance. Previous observations confirm that the Early resistance exerts no significant
impact on the small signal dynamics of a common base amplifier. Consequently, ignoring Early
phenomena, which is motivated more by analytical convenience than by engineering necessity, is
not likely to incur any significant errors in our bandwidth-related conclusions.
+Vcc
Cμ
Rl
Vo
Ibc
Rs+rb
+
Vb
Vs
−
Ree
+
Vbb
−
(a).
Rs+rb
+
Cμ
Vbs
Rs+rb
Vos
I
rπ
Vs
Ix
βac I
Rl
+ Vx −
I
rπ
βac I
Rl
−
Ree
Ree
(b).
(c).
Figure (7.30). (a). Basic schematic diagram of an emitter-degenerated, common emitter amplifier with a simple
resistive load termination. The base resistance, rb, is extracted to highlight the base-collector
junction capacitance, Cμ, whose effect on the circuit 3-dB bandwidth is investigated. (b). Small
signal, high frequency model of the amplifier in (a). The model is an approximate equivalent circuit in that the Early resistance is tacitly ignored and the only capacitance considered is the basecollector junction capacitance, Cμ. (c). Approximate model used to calculate the resistance
associated with the time constant established by the base-collector junction capacitance.
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Before diving into a sea of mathematics, we should note in Figure (7.30a) that the basecollector junction capacitance, Cμ, can be expected to conduct a high frequency signal current,
Ibc, which must be supplied by the source of signal excitation. This current is
I
bc
= C
(b
d V −V
μ
dt
which in the steady state is
= jω C
(
o
),
(7-92)
)
V −V
.
(7-93)
μ bs
os
As inferred by the model of Figure (7.30b), Vbs and Vos respectively symbolize the small signal
components of input voltage Vb and output voltage Vo. In addition to the direct proportionality of
capacitive current Ibc on radial frequency ω, we can postulate a potentially significant voltage
difference, (Vbs − Vos), which can further increase the magnitude of the current conducted by
capacitance Cμ. This postulate derives from the fact that a common emitter amplifier is typically
designed for significantly larger than unity voltage gain magnitude. Moreover, a common emitter amplifier exhibits 180° of I/O phase inversion, at least at low to even moderately high signal
frequencies. Consequently, and to crude first order, Vos is proportional to port voltage Vbs by
some negative, gain-related constant, say (−M), whence
(7-94)
I bc = jωC μ (Vbs − Vos ) = jωC μ (Vbs + MVbs ) = jωC μ ( 1 + M ) Vbs ,
I
bc
which is certainly sizeable for a large gain magnitude, M.
There are two interesting sidebars to the foregoing expression. The first of these is that
the current, Ibc, conducted by capacitance Cμ in Figure (7.30a) is identical to the current drawn
from the signal source by capacitance Cm in Figure (7.31), where it is understood that
C = (1 + M ) C .
(7-95)
m
μ
+Vcc
Rl
Vo
Rs+rb
+
Vs
−
Vbb
+
Vb
Ibc
Cm
Ree
−
Figure (7.31). Equivalent Miller representation of the
capacitance, Cμ, in Figure (7.30a). The
Miller capacitance, Cm, is given by (7-95).
This equation demonstrates that the effect of the capacitance, Cμ, in Figure (7.29a) is to establish
a grounded capacitance of value Cm at the node that supports voltage Vb (whose time-dependent
signal value is Vbs). Capacitance Cm, which is termed the Miller capacitance, can be several
times the value of Cμ if the magnitude of gain postured by the considered common emitter cell is
large. The factor, (1 + M), which multiplies Cμ is called the Miller multiplier. We might
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serendipitously opine that whenever the Miller capacitance multiplier is large enough to impact
the I/O dynamics of a common emitter stage, it must be “Miller time” (pun intended).
The second illuminating aspect of (7-94) is that the capacitive current, Ibc, predicted by
(7-92), (7-93), or (7-94) is necessarily supplied by the signal source. Since this current flows
through the internal signal source resistance, a fraction of the Thévenin signal voltage, Vs, is lost
as a high frequency voltage drop across Rs. This signal voltage loss spells a diminished input
signal, Vbs, which in turn proportionately decreases the magnitude of the output voltage response,
Vos. If the stage at hand exhibits voltage gain, as is commonly the case, the magnitude of Vos decreases at a faster rate than that of Vbs and hence, gain is degraded at the high signal frequencies
that spawn a measurable base-collector capacitive current. As we propounded earlier, a measure
of this gain degradation is the 3-dB bandwidth.
The foregoing observations and conclusions can be formalized by returning to Figure
(7.30b) to investigate the time constant established by the capacitance, Cμ, of interest. To this
end, Figure (7.30c) gives the equivalent circuit for evaluating the resistance, Rμ = Vx/Ix, seen by
capacitance Cμ with the independent signal source set to zero. Using the branch currents provided in this diagram, it can be shown that resistance Rμ is given by
⎡
⎤
V
g R
x
m
l
⎢
⎥ ,
⎡
⎤
(7-96)
R =
r + β +1 R
1+
= R + r +R
l
b
s ⎣π
ac
ee ⎦ ⎢
μ
⎥
I
α
1
g
R
+
x
⎢⎣
m ee ac ⎥⎦
where we have once again exploited the fact that βac = gm rπ. Careful scrutiny of this relationship
reveals that the indicated shunt combination of the resistance sum, (rb + Rs), and the sum, [rπ +
(βac + 1)Ree], is exactly the resistance presented with respect to ground at the node in Figure
(7.30b) where signal voltage Vbs is established. Since the Miller capacitance, Cm, is inserted between ground and the aforementioned node that supports Vbs, we conclude that the time constant,
say τμ, attributed to Cμ is
{(
)
{(
(
)
)
(
}
)
(
)
}
(7-97)
τ μ = Rμ C μ = Rl C μ + rb + Rs ⎡ rπ + β ac + 1 Ree ⎤ Cm ,
⎣
⎦
where Miller capacitance Cm is, by comparison of the last equation with (7-95),
⎡
⎤
g R
m
l
⎢
⎥
(7-98)
C = 1+
C .
m
⎢
⎥ μ
α
1
g
R
+
⎢⎣
m ee ac ⎥⎦
Evidently, the parameter, M, introduced in conjunction with the Miller multiplier in (7-94) is
g R
m l
(7-99)
M =
,
1+ g R α
m ee ac
(
(
)
)
which, provided resistance ro can indeed be ignored, is precisely the magnitude of the small signal voltage gain, Vos/Vbs. The reader is encouraged to confirm this voltage gain contention
through a straightforward reconsideration of the gain and I/O transconductance expressions
developed earlier for the common emitter amplifier.
In order to sustain a large circuit bandwidth, all circuit time constants, including τμ,
must be kept small. To this end, a large common emitter gain, as might be promoted by large
gmRl, manifests large M, and hence a large Miller capacitance, which controverts the large bandwidth goal. In a word, large gain begets proportionately small 3-dB bandwidth. On the other
hand, note that progressively larger Ree results in a decreased M factor, hence a smaller time
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constant, τμ, and presumably enhanced bandwidth. Of course too large a value of emitter
degeneration resistance Ree is counterproductive to achieving reasonable voltage gain levels, low
noise analog signal processing, and power efficient, low voltage biasing.
Insofar as forward gain investigations are concerned, (7-97) suggests that the effects in
Figure (7.30b) of capacitance Cμ, which appears as a feedback element that couples the collector
to the base at high signal frequencies can be modeled by a Miller capacitance and an appropriate
output port capacitance. Both of these capacitances have one of their terminals grounded. The
alternative high frequency equivalent circuit is postured in Figure (7.32). There is both good and
bad news associated with this alternate structure. On the good side, the time constants associated
with capacitances Cm and Cμ are easily computed due to the fact that collector -to- base feedback
has been eliminated, thereby decoupling the input and output ports of the amplifier. For example
and by inspection, the time constant associated with Cm in Figure (7.32) is {(rb + Rs)||[rπ + (βac
+ 1)Ree]}Cμ while the time constant associated with Cμ at the output port is simply RlCμ. If we
simply add these two time constants, we obtain τμ, as per (7-97), exactly. We are therefore
moved to assert that the model in Figure (7.32) is identical to that of Figure (7.30b) in at least
two respects. First, the low frequency I/O characteristics embraced by both models are identical,
for nothing has been done to change model dynamics at low frequencies where capacitances behave as open circuits. Second, the superposition of the individual time constants in Figure (7.32)
identically produces the time constant associated with capacitance Cμ in Figure (7.30b). But on
the bad side, capacitance Cμ in Figure (7.30b) can be shown to establish, in addition to the
aforementioned time constant, τμ, a right half plane zero, whereas neither capacitance Cm nor
capacitance Cμ in Figure (7.32b) gives rise to a zero (in either the left half or the right half complex frequency plane). Fortunately, the frequency of the right half plane zero established by Cμ
in Figure (7.30b) is so large that this zero generally exerts little, if any, measurable effect on the
circuit 3-dB bandwidth.
Rs+rb
+
Vbs
Vos
I
rπ
Vs
βac I
Rl
−
Cm
Ree
Cμ
Figure (7.32). Approximate high frequency model alternative to the
equivalent circuit in Figure (7.30b).
The preceding discussion establishes the somewhat curious fact that the base-collector
junction capacitance, Cμ, which is generally the smallest of the three primary bipolar transistor
capacitances (base-emitter, base-collector, and collector-substrate) may very well be the dominant capacitance with respect to determining the 3-dB bandwidth of a simple common emitter
amplifier. The problem is that while Cμ is small, its time constant, τμ, is potentially large,
primarily because of the gain-related Miller multiplier, M, as defined analytically by (7-99). We
note that this Miller multiplier is directly proportional to the load resistance, Rl, which is inserted
in the collector lead of the transistor in the common emitter amplifier. To wit, the larger is Rl,
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the larger is the I/O common emitter voltage gain and Miller multiplier M, and the larger is the
time constant, τμ, associated with capacitance Cμ. Of course, larger time constants portend
diminished circuit bandwidth. Obviously, the key to sustaining relatively small τμ and presumably acceptably large circuit bandwidth, while not compromising gain, is to reduce the Miller
multiplier. Recall that the common emitter-common base cascode in Figure (7.29a) sustains an
I/O low frequency voltage gain that is nearly the same as that afforded by a simple common
emitter amplifier; that is, a cascode does not alter the achievable I/O low frequency voltage gain.
But observe in this cascode configuration that the effective load resistance driven by the collector
of the common emitter transistor is not Rl (which now appears in the collector lead of the common base stage) but in fact, it is Rinb, the driving point input resistance of the common base cell
in Figure (7.29b). If Rl is larger than Rinb, which indeed is small in that it is approximately (rb2 +
rπ2)/(βac2 +1), the Miller multiplier associated with the base-collector capacitance of the common
emitter transistor in the cascode is substantively smaller than the corresponding Miller multiplier
of a simple common emitter amplifier.
There is no question that the common emitter-common base cascode amplifier mitigates Miller multiplication of the base-collector capacitance of the common emitter transistor.
Whether such mitigation nets increased bandwidth is problematical and needs to be investigated
carefully by the circuit designer. The issue at hand is the degree by which resistance Rl exceeds
the common base input port resistance, Rinb and thus, the amount by which time constant τμ is
reduced from its original common emitter value. The amount of time constant savings, as it
were, must be compared to an effective time constant penalty incurred by the addition of the
common base transistor, Q2, in Figure (7.29b). In particular, Q2 adds a base-emitter capacitance, a base-collector capacitance, and a collector-substrate capacitance that certainly were not
present in the original common emitter topology. All of these appended capacitances incur time
constants that superimpose with those of the common emitter transistor to define the observable
3-dB bandwidth of the amplifier. We can argue that since the base of Q2 is grounded under signal conditions, the base-emitter and base-collector capacitances of Q2 are not likely to establish
large time constants. And to the extent that resistance Rl is not a large load resistance, the collector-substrate capacitance of Q2 is similarly inconsequential. But these qualitative stipulations
must be tested and properly evaluated prior to formal adoption of a cascode scheme to effect circuit broadbanding.
7.5.2.2. Folded Bipolar Cascode
An alternative form of the classic common emitter-common base cascode is the folded
cascode circuit, whose basic schematic diagram appears in Figure (7.33a). In this diagram,
transistor Q1 and resistance Ree1 comprise an emitter degenerated common emitter amplifier.
The common base transistor, Q2, is not placed in series with the collector of Q1. Rather, it is
placed in a separate branch, parallel to the emitter degenerated cell, to allow the designer to
choose base bias voltage, Vbias1, so that the quiescent collector current, IoQ, of common base device Q2 need not necessarily equal the quiescent collector current conducted by the common
emitter transistor, Q1. This additional design degree of freedom, which is not afforded by the
conventional cascode topology, is advantageous from the perspective of optimizing circuit bandwidth. We further note that transistor Q3, which is driven at its base by a constant voltage, Vbias2,
supplies its correspondingly constant static current, to both transistors Q1 and Q2.
The signal schematic diagram pertinent to the subject folded cascode is offered in Figure (7.33b). In this depiction, all static supply voltages are reduced to zero, with the result that
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all node voltages and all branch currents assume their pertinent small signal values. Additionally, we have elected to represent the collector output port of the Q1–Ree1 amplifier by its Norton
equivalent macromodel. In this macromodel, forward transconductance gme1 derives from (7-22)
and is specifically given for the circuit investigation at hand by
+Vcc
Ree2
Vbias2
Q3
Roe2
Roe2
Roe1
Rs
Vi
+
Q1
Rib
Vbias1
Q2
Rib
Roe1
gme1Vs
Q2
Vs
−
Rine
+
Rob
Ree1
Vbb
−
Rl
Rob
Vo =
VoQ+Vos
Vos
Rl
Io = IoQ+Ios
Ios
(a).
(b).
Figure (7.33). (a). Schematic diagram of a bipolar technology folded cascode. (b). Equivalent circuit of
(a) under signal conditions. All static supply voltages are replaced by short circuits to
ground, and the output port of the common emitter cell is replaced by its Norton equivalent output port macromodel. The collector port macromodel of the Q3-Ree2 subcircuit
consists only of the output resistance, Roe2, seen looking in to the Q3 collector, since no
signal is applied to the base of Q3. The output voltage and current, Vo and Io, respectively, assume their respective signal values, Vos and Ios.
⎛
⎞⎛
⎞
R
ee1 ⎟
⎟⎜1 −
⎜ r + R ⎟⎜
β ac1ro1 ⎟
ee1 ⎠ ⎝
⎝ o1
⎠
r
o1
β ac1 ⎜
g
me1
=
R +r
s
b1
+r
π1
(
+ β
ac1
)(
+1 R
r
ee1 o1
≈
)
α ac1
R
.
(7-100)
ee1
Using (7-19), we see an output resistance of the Q1 subcircuit of
⎛
⎞
β ac1Ree1
⎟r + R
= ⎜1 +
R
R +r +r
oe1
ee1
s
b1 π 1
⎜
R + R + r + r ⎟ o1
ee1
s
b1 π 1 ⎠
⎝
⎛
⎞
β ac1Ree1
⎟r .
≈ ⎜1 +
⎜
R + R + r + r ⎟ o1
ee1
s
b1 π 1 ⎠
⎝
(
)
(7-101)
As in the conventional common emitter-common base cascode, the collector output
port of the emitter degenerated common emitter amplifier is terminated in low resistance. This
low resistance ensures minimal Miller multiplication of the base-collector depletion capacitance
of Q1 and the establishment of minimal time constant associated with any parasitic or circuit
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capacitance that may be incident at this collector node. In particular, the terminating resistance
in question is the shunt interconnection of resistance Roe2, which is seen looking into the collector of the Q3–Ree2 subcircuit and the input resistance, Rib, presented to the network by the emitter
of transistor Q2. To be sure, resistance Roe2 is large for appealing to (7-19) once again,
⎛
⎞
β ac3 Ree2
⎟r + R
= ⎜1 +
R
r +r
oe2
ee2 b3
π3
⎜
+ r + r ⎟ o3
R
ee2
b3
π3 ⎠
⎝
(7-102)
⎛
⎞
β ac3 Ree2
⎟r .
≈ ⎜1 +
⎜
+ r + r ⎟ o3
R
ee2
b3
π3 ⎠
⎝
which is potentially significantly larger than the Early resistance, ro3. On the other hand, resistance Rib is small in that (7-86) yields
⎛r + r ⎞
r + R ⎜ b2 π2 ⎟
o2
l ⎜ β
+1⎟
r +r
⎝ ac2
⎠
R =
≈ b2 π2 ,
(7-103)
ib
α R
+1
β
ac2
l
ac2
1−
⎛r + r ⎞
r + R + ⎜ b2 π2 ⎟
o2
l ⎜ β
+1⎟
⎝ ac2
⎠
which is roughly inversely proportional to the gain-related metric, (βac2 + 1).
(
(
)
)
We may now determine the input and output resistances, Rine, and Rob for the folded
cascode configuration In view of the Q1 collector termination in a resistance of Roe2||Rib, (7-15)
yields an input resistance of
⎛
⎞
β ac1ro1
⎤
R
r +R
R
= r +r +⎜
+ 1⎟ ⎡ R
ine
b1 π 1 ⎜
ee1 o1
oe2 inb ⎦⎥
⎢
⎟
⎣
⎜r +R
⎟
R
(7-104)
oe2 inb
⎝ o1
⎠
(
≈
( β ac1 + 1) Ree1 ,
while by (7-82), the output resistance is
⎡
⎤
β ac2 Roe1 Roe2
⎢
⎥r + R
R
R
= ⎢1 +
⎥ o2
ob
oe1 oe2
R
R
r
r
+
+
⎢⎣
oe1 oe2
b2
π 2 ⎥⎦
(
≈
)
(
( β ac2 + 1) ro2 ,
)
)
(
) ( rb2 + rπ 2 )
(7-105)
which is indeed huge by virtue of the fact that the effective signal source resistance driving the
common base stage is the parallel combination of the large resistances, Roe1 and Roe2, as per (7101) and (7-102).
The current gain, Aib, and the voltage gain, Av, of the folded cascode network can now
be evaluated. For the current gain, (7-89) establishes
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ib
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g
Canonic Analog MOS Cells
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os
V
me1 s
(
)
⎡ β
⎤
R
R
ac2 oe1 oe2
⎢
⎥r + R
R
r +r
(7-106)
oe1 oe2
b2
π2
⎢
⎥ o2
+
+
R
R
r
r
⎢⎣ oe1 oe2
b2
π2 ⎥⎦
= −
≈ α
.
ac2
⎡
⎤
β
R
R
ac2 oe1 oe2
⎢1 +
⎥r + R
+R
R
r +r
oe1 oe2
b2
π2
l
⎢
⎥ o2
+
+
R
R
r
r
⎢⎣
oe1 oe2
b2
π2 ⎥⎦
In this relationship, we have been careful to characterize the signal source resistance driving the
common base unit as (Roe1||Roe2), which is very large and indeed permits the indicated
approximation. Also, observe that in contrast to the current gain expression of (7-89), a minus
sign precedes the present current gain relationship in (7-106). This negative sign occurs because
while the signal output current and the signal input current are couched as flowing in the same
direction in the simple common base amplifier of Figure (7.25), which precipitates (7-89), these
two currents are delineated as opposing one another in Figure (7.33b). Once the current gain is
established, the corresponding voltage gain, Av, follows as,
V
I R
α α R
(7-107)
A = os = os l = − g
R A ≈ − ac1 ac2 l ,
v
me1 l ib
V
V
R
(
(
(
s
)
)
)
s
(
)(
)
(
)(
)
ee1
which is essentially identical to the I/O voltage gain provided by the conventional common emitter-common base cascode amplifier.
In the absence of approximations, the I/O resistance expressions for the folded cascode
network are clearly algebraically intricate. And if the analytical relationships for the forward
transconductance, gme1, in (7-100) and common base current gain, Aib, in (7-106) are substituted
into (7-107), the voltage gain expression, Av, is equally involved. But it is worthwhile emphasizing that as in the previously examined circuit cells, we forged the performance metrics of the
folded cascode amplifier divorced of any substantive analysis. Instead, we simply conflated relevant performance relationships with the topological structure of the circuit before us. It is painful even to imagine the algebraic mess in which we would have immersed ourselves had we
elected to study the folded cascode circuit simply by analyzing the network that derives from
substituting the small signal equivalent circuit for each of the three transistors in Figure (7.33a).
In addition to circumventing algebraic grief and inspiring computational efficiency, we deduced
the performance metrics for the folded cascode in a manner that conveys the design-oriented insights that are indispensable to the circuit designer. For example, we confirmed easily that the
I/O voltage gain of the folded cascode is essentially the same as that of the original cascode
configuration. In addition we are hardly surprised by the approximate direct proportionality of
the I/O voltage gain on load resistance, given that our disclosures reveal a very high amplifier
output resistance, Rob.
7.5.2.2. Regulated Bipolar Cascode
The regulated bipolar junction transistor cascode, whose basic schematic diagram is
illustrated in Figure (7.34) improves on the previously examined common emitter-common base
cascode configurations in two respects. First it diminishes the input resistance, Rir, presented to
the collector of the common emitter cell, Q1, by the common base transistor Q2. Accordingly,
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the regulated cascode all but completely neutralizes the effects of Miller multiplication of the
base-collector transition capacitance in transistor Q1, thereby promoting enhanced 3-db circuit
bandwidth. Second, it boosts the output resistance, Ror, rendering the amplifier in Figure (7.34)
an excellent transconductor for such applications as operational transconductor amplifier-capacitor (OTA-C) active filters. The regulated cascode accomplishes the aforementioned very low
input resistance and very high output resistance attributes by incorporating negative feedback
from the emitter -to- the base of common base transistor Q2 in the form of the additional common emitter transistor, Q3, as shown in the diagram.
+Vcc
R
Rl
Io = IoQ+Ios
Vo = VoQ+Vos
Ror
V3 = V3Q+V3s
Q2
V2 = V2Q+V2s
Q3
Rir
Rs
+
Route
Vi
Q1
Vs
−
+
Vbb
Rine
Ree
−
Figure (7.34). Basic schematic diagram of a regulated cascode
realized in bipolar junction transistor technology.
A qualitative understanding of the effects that the feedback manifested by the indicated
connection of transistor Q3 exerts on observable circuit performance can be gleaned by presuming that the signal component, say Ios, of the indicated Q2 collector current rises for any realistic
reason whose specifics need not presently concern us. The immediate effect of an enhanced Ios is
an increase in the signal component, say Ie2s, of the Q2 emitter current, Ie2. As Ie2s rises, so must
the signal voltage, V2s rise at the base of transistor Q3, if our friends, Ohm and Kirchhoff, are to
be kept happy. But as voltage V2s increases, the signal component, V3s, of the voltage, V3, developed at the base of Q2 diminishes because of the 180° low frequency phase shift evidenced between the base and the collector in the Q3 common emitter subcircuit. The two immediate
ramifications of this decreasing signal voltage, V3s, are a diminished V2s, and a decrease in signal
current Ios in the collector of Q2. It is to be understood that voltage V2s is compelled to fall when
voltage V3s diminishes because the signal voltage developed at the emitter of a BJT necessarily
follows the signal voltage established at the base of the transistor. Moreover, the Ebers-Moll
transistor model nicely explains the decrease in Ios when the voltage V3s, at the transistor base
decreases[2]. Thus, while the original perturbation in current Ios caused V2s to rise, the implemented feedback precipitates a proportionate fall in V2s. In a sense, therefore, we might say that
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the regulated cascode precludes rampant changes in signal voltage V2s. In other words the implemented feedback subcircuit “regulates” changes in V2s. If the precipitated fall in V2s matches the
original rise in V2s (to be sure, such matching can never be achieved exactly with practical feedback measures), there is, in effect, no change in V2s. But this resultant zero signal voltage implies a short circuited node under signal conditions, which means that the node at which the
collector of Q1 connects to the emitter of Q2 is an effective small signal short circuit, or a zero
resistance node. Analogously, the original increase in Ios is matched by a commensurate decrease in Ios. Current Ios is, therefore, like voltage V2s, “regulated” by the feedback structure and
if the resultant change in Ios is very small, an effective very high output resistance port is established.
rb2
Vos
I
rπ2
I+βac3 I
βac2 I
Rl
V2s
V3s
rb3
(βac2+1)I
βac2 I
I3
R
βac3 I3
rπ3
gme1Vs
Figure (7.35). Approximate small signal model of the regulated cascode
in Figure (7.34).
In an attempt to reinforce the foregoing qualitative observations with appropriate circuit
analysis, Figure (7.35) is submitted. This figure diagrams the small signal model of the regulated
cascode under the simplifying (and realistic) assumption of large Early resistances in all active
devices. Because of our tacit neglect of Early phenomena, the Norton equivalent macromodel of
the output port of the Q1 common emitter driver consists only of the indicated VCCS, gme1Vs,
where by (7-22) with ro = ∞,
=
β ac1
≈
α ac1
(7-108)
.
R
+r + β
+1 R
ee
s
b1 π 1
ac1
ee
No resistance appears in shunt with this VCCS because, as is confirmed by (7-19), this resistance, which is Route, the driving point output resistance of the common emitter amplifier, is infinitely large when the Early resistance is taken as infinitely large. The remaining model elements
are traditional to the small signal BJT equivalent circuit that we have used repeatedly throughout
this document.
g
me
R +r
(
)( )
The analysis of the equivalent circuit in Figure (7.35) is best accomplished by first
solving for ancillary current, I. This intermediate current is foundational for ascertaining the I/O
gain, Vos/Vs, and the voltage gain, V2s/Vs, from signal source to the Q3 base-Q2 emitter
interconnection. The analysis shows that
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g
I =
1+
me3
=
( β ac2 + 1)
R+r
b2
,
+r
(7-109)
π2
( β ac2 + 1)( rb3 + rπ3 )(1 + g me3 R )
where
g
V
me1 s
J. Choma
β ac3
r
b3
(7-110)
+r
π3
is recognized as the effective forward transconductance of the Q3 common emitter stage. Since
the output signal voltage, Vos, is Vos = –βac2RlI, we see, with the help of (7-109), that the I/O
voltage gain, Vos/Vs, is
V
α ac2 g me1Rl
α α R
os = −
(7-111)
≈ − ac2 ac1 l ,
R+r +r
V
R
b2
π2
s
ee
1+
β
1+ g
R
+1 r +r
(
)( b3
ac2
π3
)(
)
me3
where (7-108) has been used. This approximate gain result is essentially the same as that of (791). In other words, the regulated cascode offers no obvious advantages insofar as I/O voltage
gain is concerned. However, we should interject that because of the reasonably large numerical
value of the product, (βac2 + 1)(1 + gme3R), in the denominator on the right hand side of (7-111),
the approximation therein is likely more easily satisfied than is the corresponding approximation
leading to (7-91).
The signal voltage, V2s, in Figure (7.35) is
= r +r I = r +r ⎡ β
+1 I −g
V
V ⎤.
2s
b3
π3 3
b3
π3 ⎣⎢ ac2
me1 s ⎦⎥
The substitution of (7-109) into this relationship leads to the voltage transfer ratio,
⎡
⎛ R + r + r ⎞⎤
b2
π2 ⎟ ⎥
⎢ r +r
⎜
g
me1
b3
π3
⎜
β ac2 + 1 ⎟⎠ ⎥
⎢⎣
V
⎝
⎦
2s = −
g
R
V
me3
s
1+
R+r +r
b2
π2
1+
+1 r +r
β
(
)
(
(
)
(7-112)
)
(
α ac1 ⎡
)(
ac2
)( b3
π3
)
(7-113)
⎤
R+r +r
b2
π2
⎢
⎥ ,
≈ −
⎥
R ⎢ β
ee ⎢⎣ ac2 + 1 1 + g me3 R ⎥⎦
which is very small, once again because of the large denominator product, (βac2 + 1)(1 + gme3R).
This result seemingly reaffirms our qualitative expectation of a very well regulated signal voltage, V2s. We note that we can never clamp V2s to zero, but V2s can be made to approach zero for
large βac2 and/or large gme3R, the latter being related to the voltage gain magnitude of the Q3
common emitter feedback subcircuit. Indeed, gme3R is the voltage gain magnitude of the Q3
feedback stage if the signal current conducted by the base of transistor Q2 is small in comparison
to the signal collector current that flows in transistor Q3. Stated in yet another way, the input
resistance seen at the node at which signal voltage V2s is established, is necessarily very small.
This resistance, which in Figure (7-34) is Rir, is literally the resistance that is driven by the
(
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)
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VCCS, gme1Vs, of the output port macromodel for the Q1 common emitter driver. In a word, it is
identically equal to the coefficient of gme1 in the numerator on the right hand side of (7-113); that
is,
⎛R+r +r ⎞
b2
π2 ⎟
⎜
r +r
b3
π3 ⎜ β
+1 ⎟
R+r +r
ac2
⎝
⎠
b2
π2
(7-114)
≈
R =
,
ir
g
R
β ac2 + 1 1 + g me3 R
me3
1+
R+r +r
b2
π2
1+
β
+1 r +r
(
)
(
(
ac2
)( b3
π3
)(
)
)
which indeed is very small owing to the product, (βac2 +1) (1 + gme3R).
The driving point output resistance, Ror, of the regulated cascode is infinitely large if
we continue to enforce the assumption of infinitely large Early resistance in all transistors
embedded in the cascode topology. We may compromise here and still preserve mathematical
tractability by allowing transistor Q2 to have finite, but nonetheless large, Early resistance ro2.
The Early resistance of transistor Q1 plays a less dominant role than does ro2 because it is placed
in shunt with the base-emitter port of Q3 where the observable resistance is (rb3 + rπ3). Typically, this resistance can be expected to be considerably smaller than the Q1 Early resistance.
For Q3, we argue that Early resistance ro3 is not significant since it appears in shunt with the circuit resistance, R, for which practical biasing constraints alone preclude large values.
The resultant model pertinent to the computation of output resistance Ror via the
mathematical ohmmeter method is the topology that appears in Figure (7.36). An analysis of this
network reveals
rb2
I
+
rπ2
βac2 I
I+βac3 I3
ro2 Vx
Ix
−
Ix−βac2I
rb3
I+Ix=I3
I3
R
βac3 I3
rπ3
Figure (7.36). Approximate small signal model for evaluating the driving point output
resistance of the regulated cascode. The Early resistances in transistors
Q1 and Q3 are ignored. Ignoring the Early resistance in transistor Q1
is tantamount to representing the output port of the Q1 common emitter
amplifier as an ideal VCCS, which, of course, is set to zero for the
resistance computation at hand.
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⎧
⎪
⎪
V
β ac2
⎪
x
R
=
= ⎨
or
I
⎡
⎪
R+r +r
x
b2
π2
⎢
1
+
⎪
⎢
1+ g
R r +r
⎪
me3
b3
π3
⎣
⎩
(
)(
)
J. Choma
⎫
⎪
⎪
⎪
+ 1⎬ r
o2
⎤
⎪
⎥
⎪
⎥
⎪
⎦
⎭
(7-115)
⎛R+r +r ⎞
b2
π2 ⎟ ≈ β
⎜
+1 r .
o2
b3
π3 ⎜ 1 + g
ac2
R ⎟
me3
⎝
⎠
The indicated approximation exploits the tacit assumption that resistance ro2 is large and
additionally,
R+r +r
b2
π2 ,
(7-116)
1+ g
R >>
me3
r +r
(
+ r
+r
)
(
b3
)
π3
which is easily satisfied since the term, gme3R, which is intimately related to the voltage gain of
the Q3 feedback subcircuit, can be expected to large.
7.6.0. WILSON CURRENT AMPLIFIER
The common base amplifier, along with all of its variants discussed in this document,
are current amplifiers in that all of these structures present low input resistance to the applied signal source and high output resistance to the load termination. Unfortunately, all of the considered common base structures provide less than unity current gain. While the Wilson current
amplifier, whose schematic diagram appears in Figure (7.37), is characterized by low input
resistance and high output resistance, it, unlike traditional common base units, can deliver greater
than unity current gain. Moreover, the gain of the Wilson unit is both highly predictable and
reproducible in that it is determined by ratios of junction areas.
+Vcc
Io
Rl
Riw
V1
I1
IQ + Is
Rs
Q1
Io /hFE3
Row
Q3
I1 /hFE
ηI1
Io(hFE3+1)/hFE3
V2
ηI1 /hFE3
Q2
Figure (7.37). Basic schematic diagram of a Wilson current amplifier. All three
transistors are identical monolithic devices, but both transistors Q2
and Q3 have base-emitter junction areas that are larger than the
base-emitter junction area of transistor Q1 by a factor of η. Branch
currents are delineated for static or low frequency conditions.
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In the Wilson stage before us, IQ represents a quiescent source current that is largely
used to supply collector current to transistor Q1. On the other hand, Is, which superimposes with
static current component IQ, is the input signal current that is earmarked for amplification. Resistance Rs is the Thévenin resistance of the net signal source, while Rl is the load resistance inserted into the collector of transistor Q3. All three bipolar junction transistors operate in their
active regimes. All three are identical monolithic devices, save for the fact that both transistors
Q2 and Q3 have base-emitter junction areas that are larger than that of transistor Q1 by a factor
of η.
Like the regulated cascode, the Wilson current amplifier is a new topological structure
for which the development of an insightful understanding of I/O performance metrics is not
likely to evolve simply from a re-interpretation of preceding performance disclosures for common emitter, common base, and common collector stages. In other words, we shall need to derive the relationships for the I/O performance metrics of the Wilson circuit, just as we did for the
regulated cascode. While this necessity may spell proverbial bad news from the perspective of
requisite algebraic manipulations, the good news is that a definitive consideration of the Wilson
circuit adds to our electronic circuits experience base. And if we execute the requisite analysis
creatively, we may find that the fruits of our mathematical labors are generally applicable to
other circuit topologies that we may ultimately encounter.
Before plunging into the analysis task lying before us, we may be able to assimilate a
first order understanding of Wilson amplifier dynamics by formulating qualitatively an approximate gain relationship premised in terms of reasonable approximations. To this end, the applied
net input current, (IQ + Is), in Figure (7.37) feeds the shunting source resistance, Rs, the collector
of Q1, and the base of transistor Q3. Let us assume that Rs is large, as we might reasonably
anticipate if the net input signal is represented as a current. If the base current conducted by
transistor Q3 is small, which fundamentally requires Q3 to have a large static current gain, hFE3,
current I1 conducted by Q1 is nominally (IQ + Is). Since Q2 and Q1 share the same base-emitter
voltage (these two devices act as a simple current mirror) and the base-emitter junction area of
Q2 is η-times that of Q1, the collector current of Q2 is ηI1 = η(IQ + Is). Ignoring the base currents in transistors Q2 and Q1, it follows that the emitter current of Q3 is ηI1. Assuming a large
static current gain, hFE3, in transistor Q3, the collector current conducted by Q3 is also ηI1 = η(IQ
+ Is), which is to say that the signal component of the net output current flowing in the collector
of Q3 is ηIs. In other words, the I/O current gain of the Wilson stage is ηIs/Is = η, which is a
nicely controllable ratio of the base-emitter junction area of Q3 (and of Q2) -to- the base-emitter
junction area of Q1. Parenthetically we might interject that since transistors Q2 and Q3 are
identical and have matched base-emitter junction geometries, their static current gains are nominally the same; that is, hFE2 ≈ hFE3. The approximate disclaimer used herewith reflects the slight
dependency of hFE on collector-emitter voltage and the fact that the static collector-emitter voltages imposed on Q2 and Q3 may not be equivalent.
7.6.1. SMALL SIGNAL ANALYSIS OF THE WILSON AMPLIFIER
We shall commence our analysis of the Wilson amplifier by first concentrating our
engineering attention on the Q1-Q2 subcircuit, which forms a feedback loop from the emitter of
transistor Q3 -to- the base of Q3. The feedback nature of this subcircuit, which is embraced by
the dashed box in Figure (7.38a), can be confirmed by examining the effect of an increase in the
voltage, V2, at the emitter of Q3. If V2 rises, voltage V1 must fall because Q1 operates as a
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common emitter unit with its invariable 180° of low frequency phase inversion between its base
and collector port. But if V1 falls, so must V2 diminish owing to the fact that the signal evidenced
at a BJT emitter follows the signal established at the base of the same BJT. In other words voltage V2 is automatically regulated by the feedback subcircuit. Even more important is that the
feedback is stable feedback, or negative feedback, in that the original increase in V2 is met with a
responsive decrease. It would therefore appear that V2 is not permitted to grow without apparent
bound.
+Vcc
Io
Rl
Row
Riw
V1
IQ + Is
Rs
Io /hFE3
Q3
I1
Io(hFE3+1)/hFE3 = I2
Feedback Network
Q1
I1 /hFE
V2
ηI1 /hFE3
ηI1
Q2
(a).
V1s
rb1
I1s
ro1
gm1Vb rπ1
+
Vb
I2s
V2s
rd2
−
(b).
Figure (7.38). (a). Wilson current amplifier with feedback network comprised of
transistors Q2 and Q1 specifically highlighted. (b). Small signal
model of the feedback subcircuit highlighted in (a).
Using the VCCS form of the equivalent circuit in Figure (7.2b) for a bipolar junction
transistor, the small signal model of the feedback structure delineated in Figure (7.38a) is shown
in Figure (7.38b). Parameters rb1, rπ1, gm1, and ro1 in this model apply to transistor Q1, whose
quiescent current is I1Q, as suggested in Figure (7.38a). Resistance rd2 is the resistance of diodeconnected transistor Q2. From (7-45),
⎛r +r ⎞
r +r
r
= r ⎜ b2 π 2 ⎟ ≈ b2 π 2 .
(7-117)
d2
o2 ⎜ β
β
+1⎟
+1
ac2
⎝ ac2
⎠
We should digress momentarily and explain that the BJT base resistance, rb, scales inversely
with the base-emitter junction area, while resistances rπ and ro scale inversely with static collector current. Recall further that device transconductance gm is linearly proportional to static
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collector current. The small signal gain metric, βac, is nominally invulnerable to area and current
since it is equal to the product of gm and rπ. Thus, since transistors Q2 and Q3 conduct the same
collector current, which is a factor of η larger than the collector current of Q1,
r
= r
r
= π1
r
= r
r
= o1
g
=
π2
o2
m3
π3
η
o3
I
.
η
oQ
nV
=
T
η I1Q
nV
= ηg
T
m1
= g
(7-118)
m2
And because of the aforementioned base-emitter junction area factors and current gain
invulnerability to current and area,
r
= r = b1
r
b2
b3
η
(7-119)
.
β ac2 ≈ β ac3 ≈ β ac1 β ac
In light of these declarations, (7-117) becomes
⎤
r ⎡ r +r
r +r
1⎛
o1
b1
π
1
b1 π 1
⎢
⎥
=
= ⎜r
r
d2
o1
η ⎢η β
η⎜
+1
β
+ 1 ⎥⎥
ac2
⎝
⎢⎣
ac2
⎦
(
)
⎞
r +r
⎟ ≈ b1 π 1 .
⎟
η βac + 1
⎠
(
)
(7-120)
In the feedback macromodel of Figure (7.38b), the amount of signal fed back to the
base of transistor Q3 from the emitter of Q3 is measured by the VCCS, gm1Vb. Although we can
leave this feedback generator untouched, it is more convenient to cast the degree of feedback as a
proportion of the output response variable, which in this case is the signal current, Ios. To this
end, we note in Figure (7.38b) that
⎛ r
⎞
⎛ β
⎞
π1
ac ⎟ ⎡ r
⎟V
(7-121)
= ⎜
g V = g ⎜
r + r ⎤I ,
m1 b
m1 ⎜ r + r ⎟ 2s
⎜ r + r ⎟ ⎢⎣ d2 b1 π 1 ⎥⎦ 2s
⎝ b1 π1 ⎠
⎝ b1 π1 ⎠
where I2s is the signal component of the net emitter current conducted by transistor Q3. We note
that this signal current flows into the input port of the Q1-Q2 feedback subcircuit circuit modeled
in Figure (7.38b). If we adopt the approximate form of resistance rd2 in (7-20), which is reasonable in view of the facts that most monolithic BJTs offer high βac and large Early resistance,
⎡ r +r
⎤
b1
π
1
⎢
⎥ r +r
≈
r r
r +r
m
d2 b1 π 1
⎢η β + 1 ⎥ b1 π 1
⎢⎣
⎥⎦
ac
(7-122)
(
(
=
)
(
)
(
)
)
+r
r +r
π1
≈ b1 π 1 ,
η β +1 +1
η β +1
r
(
b1
ac
)
(
ac
)
whence
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⎤
⎛ β
⎞
⎛ β
⎞⎡ r + r
ac
ac
b1
π
1
⎡
⎤
⎢
⎥I
⎟ r
⎟
= ⎜
g V = ⎜
r +r
I
m1 b
⎜ r + r ⎟ ⎢⎣ d2 b1 π 1 ⎥⎦ 2s
⎜ r + r ⎟ ⎢η β + 1 + 1 ⎥ 2s
⎝ b1 π1 ⎠
⎝ b1 π1 ⎠ ⎢⎣
⎥⎦
ac
(7-123)
α I
I
≈ ac 2s = os ,
(
η
)
(
)
η
which alludes to a transformation of the original VCCS, gm1Vb, into the CCCS, Ios /η. In arriving
at the result in (7-123), we have made use of the fact that Ios, which is the signal current flowing
in the collector of Q3, is the product of αac and the signal emitter current, I2s, conducted by
transistor Q3. Accordingly, the macromodel in Figure (7.38b) can be supplanted by the CCCS
form of the macromodel shown in Figure (7.39a). More importantly, this latter model can be
coalesced with the small signal model of transistor Q3 to produce the amplifier macromodel provided in Figure (7.39b).
I1s
V1s
I2s=Ios /αac
Ios
η
ro1
V2s
rm
(a).
Riw
V1s
Row
rb3
I1s
Is
I
rπ3
Rs
Is−I−I1s
Ios
η
ro1
βac3 I
V2s Ios−βac3I
Ios
η
ro3
Rl
Ios
rm
(b).
Figure (7.39). (a). CCCS form of the feedback macromodel for the Wilson amplifier of
Figure (7.28a). Resistance rm is defined in (7-122). (b). Low Frequency,
small signal model of the Wilson current amplifier.
7.6.1.1. I/O Current Gain
The model in Figure (7.39b) can be analyzed to arrive at the current gain, Aiw, of the
Wilson amplifier. Unfortunately, the requisite algebra underlying an acceptable presentation of
this gain expression is messy but nonetheless, as professors like to quip, “it can be shown that”
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iw
=
Canonic Analog MOS Cells
R r
I
os =
I
s
J. Choma
s
)
(
o1
(
)
⎡ R r +r + r +r ⎤ r + r +R
R r
b3
π3 m ⎦⎥ o3
m
l
⎢ s o1
+ s o1
r + ⎣
m
β r −r
η
ac o3
.
(7-124)
m
The expression at hand is cumbersome and non-descript and thus, it is imperative that we
exercise due diligence to forge an insightful, design-oriented understanding of this gain expression.
We begin our task by observing in the model of Figure (7.39b) that the feedback manifested from the output port to the input port of the Wilson amplifier is represented mathematically by the CCCS, Ios /η. In other words, the input port of the Wilson network is energized by
two sources of signal. The first of these is the obvious signal source current, Is, while the second
is the feedback current, Ios /η. In the case of the feedback generator, a fraction (1/η) of the output
current response, Ios, is redirected to the input port, where it superimposes with the signal source
current to establish a regulated, or more controlled, current response. We note that the feedback
fraction, (1/η) is less than one since, if our first order analysis of the Wilson amplifier accurately
predicts a nominal I/O current gain of η, we should wish to have η > 1. We note further that if
1/η = 0, which corresponds to very large η and thus, an I/O current gain that is large but neither
regulated nor well-controlled, no feedback is observed. Under this zero feedback condition, we
say that the amplifier operates open loop and the resultant gain is termed the open loop gain, say
Aow. From (7-124), we find the open loop gain to be
A
ow
=
I
os
I
=
s 1 =0
η
R r
(
s
)
o1
ac o3
≈
R r
s
o1
r
(
⎡ R r +r + r +r ⎤ r + r +R
b3
π3 m ⎦⎥ o3
m
l
⎢ s o1
r + ⎣
m
β r −r
m
)
(7-125)
,
m
where the approximation reflects the standard presumptions of large βac and large ro3. Since
resistance rm in (7-122) is inversely proportional to (βac + 1), we note that this open loop gain is
large. Moreover, it is interesting that the gain relationship in (7-124) can now be compacted into
the form,
I
A
ow
(7-126)
.
A = os =
iw
A
I
ow
s
1+
η
There are at least two interesting aspects to the simple gain relationship of (7-126). The
first is that the expression gives rise to the block diagram model of the Wilson amplifier, which
we depict in Figure (7.40). We note that the block diagram depiction gives
⎛
⎞
1
I
= A ( ΔI ) = A ⎜ I − I ⎟ ,
(7-127)
os
ow
ow s η os
⎝
⎠
which identically produces the current gain, Ios/Is, in (7-126). The block diagram representation
clearly portrays 1/η as the feedback factor for the circuit. In addition, when the signal flow path
containing this feedback factor block is broken, which is tantamount to opening the loop formed
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by the Aow and 1/η blocks, the I/O gain, reduces to Aow, which purportedly explains why Aow is
referenced as the “open loop gain” of the amplifier. Since Aow is called the open loop gain, it is
only natural to refer to the actual gain, Aiw, as the closed loop gain; that is the gain with the feedback path closed or connected. Finally, the loop gain, which is the gain around the loop formed
of the open loop gain and the feedback factor, is Aow/η.
∆I
Aow
Is
Ios
Σ
1/η
Figure (7.40). Block diagram representation of the Wilson current amplifier.
The second interesting aspect surrounding the closed loop gain in (7-126) is that for a
large loop gain, Aow/η, Aiw ≈ η; that is, the operating condition commensurate with a closed loop
gain that is determined exclusively by transistor geometrical factors is a large loop gain. We
note that for a large loop gain, Ios/Is ≈ η, which in turn constrains the error signal, ΔI = Is – Ios/η,
which is the signal that is effectively applied to the input port of the open loop component of the
feedback amplifier, to virtually zero.
7.6.1.2. Driving Point Output Resistance
In order to arrive at an expression for the driving point output resistance, Row, we can
exploit mathematical ohmmeter methods applied to the amplifier output port or we can make use
of the gain relationships that we have already developed. To wit, the Norton current gain, which
of course is the current gain of the amplifier with the load resistance replaced by a short circuit,
is, by (7-124),
A
nw
= A
iw R =0
l
=
R r
s
)
(
o1
(
)
⎡ R r +r + r +r ⎤ r + r
R r
b3
π3 m ⎦⎥ o3
m
⎢ s o1
+ s o1
r + ⎣
m
β r −r
η
ac o3
.
(7-128)
m
This Norton gain, along with the output resistance, Row, forms the output port macromodel of the
Wilson amplifier shown in Figure (7.41). From this macromodel, we see that
⎛ R
⎞
I
A
os = A ⎜
ow ⎟ =
nw
.
(7-129)
nw
R
⎜R + R ⎟
I
l
s
l⎠
⎝ ow
1+
R
ow
Accordingly, we need only to massage the general closed loop gain current gain expression in (7124) into the algebraic form of (7-128) to deduce the expression for the output resistance. In
particular, we have, from (7-124),
Row
AnwIs
Rl
Ios
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Figure (7.41). Norton equivalent macromodel of the
output port of the Wilson amplifier.
A
iw
=
I
A
os =
I
s
1+
nw
(7-130)
,
R
l
(
r +r
m
o3
+
⎛R r
⎞
β ac ro3 − rm ⎜ s o1 + rm ⎟
⎜ η
⎟
)
⎝
+r + r
( Rs ro1 )
b3
π3
⎠
+r
m
from which we conclude readily that the driving point output resistance, Row, of the Wilson
amplifier is
⎛R r
⎞
s
o1
⎜
β ac ro3 − rm
+r ⎟
m⎟
⎜ η
⎝
⎠ ≈ ⎛ β ac + 1 ⎞ r .
R
= r +r +
(7-132)
⎜⎜
⎟⎟ o3
ow
m
o3
η
R r +r + r +r
⎝
⎠
s o1
b3
π3 m
(
)
)
(
As expected the output resistance is very large. However, it is somewhat compromised (reduced) when the amplifier is designed for a relatively large closed loop current gain, η.
7.6.1.3. Driving Point Input Resistance
The driving point input resistance, Riw, is best determined via conventional
mathematical ohmmeter methods. To this end, the model shown in Figure (7.39b) is adapted to
the ohmmeter topology shown in Figure (7.42). A straightforward, but admitted cumbersome
circuit analysis produces
Riw
Vx
rb3
Ix−I
I
rπ3
Ix
βac I
V2s Ios−βacI
Ios
η
ro1
Ios
η
ro3
Rl
Ios
rm
Figure (7.42). Equivalent circuit used in the determination of the driving point input
resistance, Riw, of the Wilson amplifier. The gain parameter, βac3, used
in the model of Figure (7.39b) is replaced by βac, since βac does not
scale with transistor base-emitter junction area.
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⎡
⎤
⎛r + r + R ⎞
l⎟ r +r +r
⎢ r + ⎜ m o3
⎥
π3 ⎥
m ⎜ β r −r ⎟ m
b3
V
⎢
⎝ ac o3 m ⎠
R
= x = r ⎢
⎥
iw
o1
I
⎛
⎞
r
r
R
+
+
⎢
⎥
1
x
l⎟
+ ⎜ m o3
⎥
⎢
η ⎝⎜ β ac ro3 − rm ⎠⎟
⎥⎦
⎣⎢
(
)
(7-133)
⎡
r +r ⎤
≈ η ⎢ r + b3 π 3 ⎥ .
β ac ⎥
⎢⎣ m
⎦
As expected the input resistance is small. Since resistance rm in (7-122) is nominally inversely
proportional to the geometrical metric, η, this resistance is not significantly compromised by a
relatively large closed loop current gain, which is indeed very nearly η.
7.6.1.4. Summary of Wilson Amplifier Characteristics
Since the Wilson amplifier is a reasonably complex feedback architecture that produces
intricate I/O performance metrics, a review of Wilson performance is arguably wise. The Wilson
current amplifier shown in Figure (7.38a) functions fundamentally as a classic common base
amplifier, but it offers the laudable additional attribute of potentially greater than unity I/O
current gain. Like the classic common base amplifier, the Wilson unit features a reasonably low
input resistance, Riw. From (7-133), (7-122), (7-118) and (7-119), this resistance is given by
⎡ r +r
2 r +r
⎡
r +r ⎤
r +r ⎤
b1 π 1
b3
π
3
b1
π
1
⎢
⎥ ≈ η
(7-134)
= η ⎢r +
+ b1 π 1 ⎥ ≈
R
.
iw
m
⎢η β + 1
β ac ⎥⎦
η β ac ⎥
⎢⎣
+
β
1
⎢⎣
⎥⎦
ac
ac
While this resistance is small and nominally invariant with parameter η (assuming model
parameters are referenced to the parameters of transistor Q1), it is roughly twice the input resistance observed in a common base cell.
(
)
(
(
)
)
The output resistance of the Wilson cell is very large; by (7-132), it is given by
⎛β
⎞
R
(7-135)
≈ ⎜ ac + 1 ⎟ r .
ow
⎜ η
⎟ o3
⎝
⎠
While large, the output resistance herewith is somewhat smaller that the output resistance of a
current driven common base cell, which we recall to be of the order of (βac +1)ro.
From (7-126), the I/O current gain is, assuming a large loop gain, Aow/η, is
I
A
ow
A = os =
≈ η .
iw
A
I
ow
s
1+
(7-136)
η
There are two laudable aspects to this current gain. The first is that unlike the current gain that
can be achieved in a traditional common base amplifier, the Wilson gain can be larger than one.
The second notable attribute to the Wilson gain expression is that the observed current gain can
be accurately controlled and reliably predicted in that it is essentially determined by a ratio of
base-emitter junction injection areas. In particular, the current gain is the ratio of the base-emitter junction area of transistor Q2 in Figure (7.38a) to the base-emitter junction area of transistor
Q1. Current gains of the order of 5 -to- 10 are plausible. Design caution should accompany larMing Hsieh Department of Electrical Engineering
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ger gains in that these require a commensurately larger base-emitter junction area in Q2.
Unfortunately, large junction areas portend of increased device capacitances and hence a potentially degraded circuit bandwidth.
7.6.2. COMMON EMITTER-WILSON CASCODE AMPLIFIER
Since the I/O characteristics of a Wilson amplifier are reminiscent of those of a common base stage, it is hardly surprising that the Wilson unit, like its classic common base counterpart, can function as a cascode component in a broadbanded common emitter stage. To this end,
we posture Figure (7.43) as representative of a common emitter-Wilson cascode network. The
Wilson subcircuit in this network is comprised of transistors Q1, Q2, and Q3, where as is indicated in the diagram, transistors Q2 and Q3 have base-emitter junction areas that are a factor of η
larger than the base-emitter junction area of transistor Q1. When compared with the generic
form of the Wilson amplifier shown in Figure (7.38a), we see that the bias current, IQ, flowing
into the input port of the Wilson stage is supplied as the quiescent collector current of PNP
transistor Q4, which is configured as an emitter-degenerated (Ree), common emitter amplifier
whose applied input signal is the voltage, Vs. On the other hand, the signal current that activates
the input port of the Wilson unit is provided by the Norton signal current, –gme4Vs. In concert
with our earlier modeling disclosures, this current is negative since the small signal, short circuit,
output current in a bipolar transistor is always directed from the collector to the emitter. From
(7-22), the effective transconductance of the Q4 subcircuit is limited by the emitter degeneration
resistance, Ree, and is
+Vcc
Ree
Rl
Io
Rs
+
Route
Riw
Vs
V1
IQ−gme4Vs
Q3
I1
−
Vbb
Rowc
Vo
Q4
−
xη I
3
V2
Q1
I2
x1
+
Q2
xη
Figure (7.43). Schematic diagram of an emitter degenerated, common emitter-Wilson cascode amplifier.
β
g
me4
=
⎛ r
⎞⎛
⎞
R
o4
ee ⎟
⎜
⎟⎜1 −
ac4 ⎜ r + R ⎟ ⎜
β r ⎟
ee ⎠ ⎝
ac4 o4 ⎠
⎝ o4
R +r
s
(
)(
+r + β
+1 R r
π4
b4
ac4
ee o4
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)
≈
α
ac4 .
ee
R
(7-137)
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We should understand that the output resistance, Route, seen looking into the collector of Q4 is the
de facto signal source resistance of the Wilson stage in Figure (7.43). From (7-19), this resistance is very large and is given by
⎛
⎞
β R
ac4 ee
⎟r + R
= ⎜1 +
R
R +r +r
π4
oute
ee
s
b4
⎜
R + R + r + r ⎟ o4
π4 ⎠
ee
s
b4
⎝
(7-138)
⎛
⎞
β R
ac4 ee
⎟r .
≈ ⎜1 +
⎜
R + R + r + r ⎟ o4
π4 ⎠
ee
s
b4
⎝
(
)
We may execute a first order small signal analysis of the cascode in Figure (7.43) by
assuming initially that all transistor base currents are negligibly small. Then the quiescent
collector current of transistor Q1 is the same as the quiescent collector current of transistor Q4.
The signal component of this Q4 collector current is I1s = –gme4Vs. Since the base-emitter junction area of Q2 is η-times that of transistor Q1, it follows that the collector current conducted by
transistor Q2 is I2 = η(IQ + I1s) = η(IQ – gme4Vs). To the extent that base currents are indeed
negligible, Q3 emitter current I3 and output current Io are identical to I2; that is, Io = I3 = I2 =
η(IQ – gme4Vs), whence we witness a signal component, Ios, of the amplifier output current that is
equal to –ηgme4Vs. Accordingly, the signal output voltage, Vos, is Vos = –IosRl = ηgme4RlVs, which
suggests an approximate, small signal I/O voltage gain, of
⎛ R ⎞
V
os ≈ η g
⎜ l ⎟.
(7-139)
R ≈ ηα
me4
l
ac4
⎜R ⎟
V
s
⎝ ee ⎠
where (7-137 is exploited, and the indicated approximation recalls the tacit neglect of all transistor base currents.
A cursory inspection of (7-139) suggests that if the Wilson circuit were obviated in favor of merely terminating the collector of common emitter transistor Q4 in Rl, the ensuing voltage gain magnitude would be simply gme4Rl. Thus, we see that the immediate effect of interposing the Wilson structure between the collector of transistor Q4 and the terminating load
resistance is a multiplication of Rl by the predictable factor, η. Two positive aspects of this
observation are easily deduced. The first is that the Wilson structure in the common emitterWilson cascode amplifier boosts the voltage gain of the circuit by a factor of η without need of
increasing the load resistance, Rl, in the collector circuit of output transistor Q3. By avoiding an
increase in Rl, circuit power dissipation is not exacerbated, and the time constants associated
with the substrate capacitance in transistor Q3 and any load capacitance that might be driven by
the output port of the amplifier are not increased, thereby avoiding a compromised 3-dB bandwidth. A second attribute of the Wilson cascode is that the nominal and presumably acceptable
voltage gain of Rl/Ree can be preserved, despite decreasing Rl by a factor of η, with the
understanding that, as is conveyed by (7-139), Rl is effectively multiplied by η in the Wilson
structure. Accordingly, the time constant at the output port can be reduced by a nominal factor
ofη, without impacting the I/O voltage gain that can be attained by the network.
In the interest of engineering completeness, it is important to point out the Wilson cascode, like the conventional common base cascode, sustains minimal multiplication of the basecollector capacitance of common emitter transistor Q4. This minimized Miller time derives from
the fact that the effective small signal load imposed on the collector of Q4 is the resistance, Riw.
As per (7-134), the Riw indicated in Figure (7.43) is very small.
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Formally, the current gain given in (7-136) remains applicable, provided we remain
mindful that the signal source current activating the input port of the Wilson amplifier is now
gme4Vs, with gme4 given by (7-137). Moreover the source resistance associated with this signal
source is the output resistance, Route, of the common emitter stage formed of transistor Q4 and its
emitter degeneration resistance. This resistance is defined by (7-138). It follows from (7-136)
that
I
A
os
ow
(7-140)
=
≈ η ,
A
g
V
−
me4 s
1 + ow
η
where by (7-125),
A
ow
=
R
)
(
r
oute o1
ac o3
≈
(
⎡ R
r +r + r +r ⎤ r + r +R
b3
π3 m ⎦⎥ o3
m
l
⎢ oute o1
⎣
r +
m
β r −r
R
r
oute o1
r
≈
⎡⎛
⎢ ⎜1 +
R +
⎢⎣ ⎜⎝
ee
m
)
m
(7-141)
⎤
⎞
⎟r ⎥ r
R + r + r ⎟ o4 ⎥ o1
s
b4
π4 ⎠
⎦
,
r
β
R
ac4 ee
m
where we should understand that βac4 is the current gain parameter of PNP transistor Q4, while
βac represents the corresponding gain parameter of all NPN transistors in the subject amplifier.
We can now state that the effective transconductance, say gmwc, of the common emitter-Wilson
cascode is
I
g
A
os = − me4 ow ≈ − η g
(7-142)
g
,
mwc
me4
A
V
ow
s
1+
η
where we have exploited the fact that the loop gain, Aow/η, is very large owing to the large open
loop gain, Aow, defined by (7-141). Since the output voltage response, Vos, is Vos = –IosRl, (7142) leads to a voltage gain expression of
V
g
RA
os = me4 l ow ≈ η g
(7-143)
R .
me4 l
A
V
s
1 + ow
η
This result mirrors the approximate gain (7-139), which is deduced from a priori invocation of
reasonable first order approximations.
7.7.0. BALANCED DIFFERENTIAL AMPLIFIER
The balanced differential amplifier, which is abstracted at a system level in Figure
(7.44), is not an additional canonic cell of analog circuit technology. Rather, it is an interconnection of a matched pair of analog cells and thus, the balanced differential circuit is often cleverly
referenced as a balanced differential pair. The pair of cells embedded within a balanced
differential architecture allow for the application of two distinct input signals −one of which
might be zero− and the generation of multiple output responses. In the subject diagram, the
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applied inputs are delineated as the voltage sources, Vs1 and Vs2, but current source inputs are
also permitted. The output responses can be taken as currents or voltages anywhere in the system. In this exercise, we shall initially focus on output voltage responses. To this end, the three
outputs of immediate interest are the single ended voltages, Vo1 and Vo2, and the indicated
differential voltage, Vdo. By a single ended voltage is meant a voltage measured at a circuit node
with respect to signal ground. In effect, all of the output voltages addressed in our preceding
discussions are single ended voltages. In contrast, the indicated differential voltage is not referred to signal ground and, in attempt to keep Gustav Kirchhoff happy, it is merely the difference between the single ended output voltages, Vo1 and Vo2; that is,
Input Node:
Amplifier #1
Vi1
Ib1
Rs
+
Rb
−
Ib2
Input Node:
Amplifier #2
Rs
Vi2
Output Node:
Amplifier #1
+
Ill
Ree
Ib1+Ib2
Vs1
Vo1
I1
Rb
Vb
Io1
Amplifier
#1
Rl
I1+I2
Vk
Rbb
Ree
Rll
Vdo
Rkk
Vl
Rll
I2
Amplifier
#2
−
Vo2
Io2
Output Node:
Amplifier #2
Rl
+
Vs2
−
Figure (7.44). System level portrayal of a balanced differential amplifier. Amplifiers #1 and
#2 are identical active networks that are biased identically for linear signal
processing purposes. Because no biasing subcircuits are delineated, all indicated
voltage and current variables represent only signal components thereof.
Vdo = Vo1 − Vo2 .
(7-144)
The diagram of Figure (7.44) clearly incorporates two amplifiers. Each of these
amplifiers can be a common emitter unit, a common collector cell, a common base structure, any
of the other more intricate topologies dealt with in preceding sections of material, or any other
configuration innovated by the circuit designer. The key is that the two amplifiers in Figure
(7.44) must be matched. In particular, these amplifier cells must be topologically identical, they
must utilize matched active devices that are biased identically, they must be driven by identical
source resistances, and they must be terminated in identical load resistances. The amplifiers
need not be realized in bipolar technology. They can be implemented with bipolar junction
transistors, a mixture of MOS and bipolar devices (commonly referred to in the literature is
BiCMOS technology), or with III-V compound devices (e.g. gallium arsenide, indium
phosphide, etc.). With identical topological structures that are biased identically for presumably
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linear signal processing purposes, we satisfy the necessary conditions underpinning the ability of
each amplifier to exhibit the same performance characteristics. The resistances, Ree, in the third
amplifier terminal, which is normally the signal ground lead of the amplifier when it is utilized in
a single ended architecture (e.g. the emitter terminal in a common emitter amplifier) must be
matched. The same statement applies to any input port biasing resistances, Rb, which may be
required. Identical topologies that are identically biased and input and output ports that are
terminated in identical impedances guarantee that the two amplifiers deliver equivalent I/O
gains, identical I/O resistances or impedances, the same 3-dB bandwidths, identical transient responses, and in general, correspondingly identical metrics that serve to define the performance
characteristics of the individual amplifiers.
Before proceeding with our analytical investigation of the balanced differential amplifier, it is interesting to point out that while differential technology has existed for decades, the
technology did not rise to prominence until the advent of the modern monolithic age[8]. Prior to
the integrated circuit revolution, the circuit designer had no option but to realize differential
topologies with discrete, off the shelf components. The inherent problem plaguing discrete
components is that matching of presumably like devices and circuit elements is a daunting challenge. This challenge can be mitigated through time-consuming, and therefore costly, individual
component testing and selection or through circuit design heroics that may compromise system
performance, integrity, and efficiency. The matching challenge is far from superficial. For
example, current gain βac of the same type discrete component bipolar junction transistor can differ by factors of as much as 3 -to- 1, and base resistances (rb), Early resistances (ro), and baseemitter junction resistances (rπ) can be at respective variances by many tens of percent. To be
sure, we can offset these effects, perhaps by implementing the two resistive branch elements, Ree,
as judiciously adjusted, non-equivalent resistances. But such a tack invariably engenders increased power dissipation, increased noise levels, and other issues. Even simple, non-precision
resistors rated for the same resistance values have their resistance values stipulated to within error tolerances of at least ±10%. It follows that the likelihood of straightforwardly realizing two
identical resistances, yet alone two identical amplifiers, with discrete, off-the-shelf components
is virtually nil. But when implemented in an integrated circuit, matching among like circuit devices and components, though still strictly imperfect, is au gratis. Indeed, implicit mismatches
between two similar components laid out in close proximity to one another on an integrated circuit chip are virtually imperceptible.
One caveat to the matching attribute of integrated circuits must be flagged when one of
the two input signals, say Vs2, applied to the balanced amplifier is zero. In this case, the source
resistance, Rs, associated with the nonzero input signal voltage, Vs1, is the internal resistance of
the source, which may be an antenna, a CD player, or the output resistance of a preceding stage
of amplification. With Vs2 nonexistent, the terminating resistance, Rs, at the input port of the second amplifier is necessarily implemented as a two terminal resistor that is physically constructed
on chip. In this circumstance, component matching between the two Rs resistances is problematic, particularly since the internal resistance associated with an actual signal source is generally
neither precisely known nor strictly independent of signal source voltage, signal current levels,
and even signal frequencies. The problem at hand is not severe in MOS technology realizations
that feature either a common source or a source follower amplifier input stage for which input
port biasing resistances are not essential (Rb = ∞). In these embodiments, the gate of the input
stage, which comprises the input port of each amplifier, conducts no current, at least at low to
moderately high signal frequencies. As a result, no signal voltage is established across either
resistance, Rs, which is to say that resistances Rs and their unavoidable mismatches are
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inconsequential. Unfortunately, such is not the prevailing case in bipolar technology, whose
base currents are inherently nonzero at all signal frequencies.
7.7.1. DIFFERENTIAL AND COMMON MODE SIGNALS
Because the amplifiers utilized in the differential system of Figure (7.44) are biased to
support linear signal processing of sufficiently small input signals, we can exploit classic
superposition theory to formulate general expressions that link the single ended output voltages,
Vo1 and Vo2, to voltages Vs1 and Vs2. In particular,
Vo1 = A11Vs1 + A12Vs2
(7-145)
,
Vo2 = A21Vs1 + A22Vs2
where the Aij are gain constants that are independent of all signal voltages and signal currents
observed in the differential network. We note that parameter A11 is the voltage gain, Vo1/Vs1, under the condition of Vs2 = 0, while A22 denotes the gain, Vo2/Vs2, with Vs1 = 0. In other words,
A11 is the voltage transfer function of Amplifier #1 with Amplifier #2 serving as a kind of
dummy load on #1 in that no input signal is externally applied to its input port. Similarly, A22 is
the gain of Amplifier #2 when Amplifier #1 functions as the dummy load imposed on Amplifier
#2. But since the two amplifiers in question are matched and the balanced network at hand is
necessarily electrically symmetrical, the subject two voltage gains are identical. Accordingly,
we can assert
A11 ≡ A22 Ai .
(7-146)
is,
We can offer precisely the same stipulation as regards gain parameters A12 and A21; that
(7-147)
A12 ≡ A21 A f .
This stipulation merely asserts that in a balanced differential pair, the sensitivity of output Vo1 to
input Vs2 (with Vs1 = 0) is the same as the sensitivity of Vo2 to Vs1 (with Vs2 = 0). In other words,
the cross-correlated voltage gains of the two amplifiers are identical in a balanced differential
architecture. The preceding two results allow us to simplify (7-145) to the form
Vo1 = Ai Vs1 + A f Vs2
,
(7-148)
Vo2 = A f Vs1 + Ai Vs2
where we witness the need of only two voltage gain parameters, Ai and Af, to relate the single
ended output signal voltages to the single ended input voltages applied to the balanced differential system.
In the process of analyzing the differential network of Figure (7.44), we shall find it
profitable to introduce the concepts of differential and common mode voltage and current signals. To this end, let the differential mode input signal, say Vdi, be defined as the difference between the two applied input signal voltages; namely,
(7-149)
Vdi Vs1 − Vs2 ,
where we note an unmistakable algebraic similarity to the differential output voltage, Vdo, in (7144). The common mode input signal, Vci, is
V + Vs2
Vci s1
(7-150)
,
2
which represents little more than the average of the two inputs. If we simultaneously solve (7149) and (7-150) for voltages Vs1 and Vs2, we get
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V
Vs1 = Vci + di
2
.
(7-151)
Vdi
Vs2 = Vci −
2
Our ninth grade mathematics teachers would be proud of our algebraic acumen. Teacher pride
notwithstanding, the design-oriented interpretations and implications of (7-151) are vital to earning an insightful understanding of both the operation and utility of a balanced differential amplifier.
Input Node:
Amplifier #1
Vi1
Ib1
Rs
−
Input Node:
Amplifier #2
Rs
Rbb
Ree
Rl
Rll
Vdo
Rkk
Vl
Rll
I2
Amplifier
#2
Vo2
Io2
−
Output Node:
Amplifier #2
Rl
−
+
Vci
+
Vdi
2
Ill
I1+I2
Vk
Ib2
Vi2
+
Ree
Ib1+Ib2
Rb
Output Node:
Amplifier #1
−
Vdi
2
Vo1
I1
Rb
Vb
+
Io1
Amplifier
#1
Figure (7.45). Alternative representation of the balanced differential architecture in Figure (7.44).
First, we see that the system in Figure (7.44) can be diagrammed as the circuit in Figure
(7.45), where input signals Vs1 and Vs2 have been replaced by the superposition of differential
and common mode input voltages documented in (7-151). The latter illustration highlights the
fact that the common mode input signal is a constituent (or arguably, a common denominator) of
both Vs1 and Vs2 that serves to activate the input ports of both of the matched amplifiers. As
such, Vci might be indicative of electrical noise radiated to both of the amplifier input ports from
lighting fixtures, nearby electrical appliances, or proximately located electronics. Of course, the
feasibility of both input ports witnessing precisely the same unwanted electrical interference assumes that these ports are physically laid out on chip with minimal geometrical separation. The
common mode input can also reflect fluctuations in biasing applied commonly to both input
ports. Such fluctuations might be incurred by electrical noise coupled to the biasing line from
which the input port biasing level is derived, temperature-induced changes in device or circuit
parameters, routine battery degradation, and the like. As long as these network parasitic effects
induce small changes in the common mode input voltage level, the differential system continues
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to respond linearly to common mode signal fluctuations, which is an underlying requirement of
(7-148).
A laudable design goal inspired by these arguments is a differential network that in fact
does not respond to Vci and is therefore impervious to common mode phenomena. A clue that
we might be able to achieve, or at least to approximate, this design outcome is offered by (7-151)
and Figure (7.45) in that the differential input signal, Vdi = (Vs1 − Vs2), is independent of the
common mode input. It indeed stands to reason that if a signal, parasitic or otherwise, is applied
simultaneously (or “commonly”) to both of the amplifier inputs, the difference signal between
these two input port voltages automatically cancels the common mode excitation. The rational
conclusion we draw from this argument is that if the balanced differential network can be designed in such a way as to respond only to differential inputs, the output responses of the system
are divorced of any ramifications attributed to common mode input excitation.
A second implication of the differential and common mode concepts is that the
superposition equations in (7-148) can be rewritten as
⎛ Ai − A f ⎞
Vo1 = Ai + A f Vci + ⎜
⎟ Vdi
2
⎝
⎠
(7-152)
;
⎛ Ai − A f ⎞
Vo2 = Ai + A f Vci − ⎜
⎟ Vdi
2 ⎠
⎝
that is, the single ended output responses, Vo1 and Vo2, are individually a superposition of
differential and common mode input excitations. This discovery is hardly anything to write
home about since the outputs are inherently a superposition of the effects of Vs1 and Vs2, and Vs1
and Vs2, in turn, are linear functions of Vdi and Vci. But (7-152) conveniently serves to define
three traditionally adopted performance metrics of a balanced differential amplifier. The first of
these is the differential voltage gain, say Ad, which is the ratio of the differential output voltage
to the differential input voltage under the condition of a common mode input voltage that is constrained to zero. Recalling (7-144),
V
V − Vo2
Ad do
= o1
= Ai − A f .
(7-153)
Vdi V =0
Vdi
V =0
(
)
(
)
ci
ci
In the course of formulating (7-153), we observe that the differential output response of a balanced differential pair is invariant with common mode input excitation, which is to say that there
is no common mode signal component to the differential output voltage response. If we accept
our view of a common mode input as reflecting undesirable electrical phenomena, this independence of differential output voltage to common mode input voltage is commendable. The downside, however, is that since Vdo is not a single ended voltage response, it is impossible to maintain
a common signal ground between input signals and the differential output response. This shortfall is troublesome in most electronic systems, but it can be circumvented through the incorporation of a differential to single ended converter, which we address later.
The second important performance metric is the common mode voltage gain, Ac, which
is the ratio of the common mode output voltage to the common mode input voltage when the
differential input signal is held at zero. A null differential input signal requires Vs1 = Vs2 and
therefore equal signal excitations applied to both of the amplifier input ports. Borrowing from
(7-150), the common mode output voltage, Vco, is defined as
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Vo1 + Vo2
.
2
This definition and (7-152) combine to deliver
V
Ac co
= Ai + A f .
Vci V =0
Vco J. Choma
(7-154)
(7-155)
di
In the idealized situation of a zero common mode response, we see that gain parameter Af must
be the negative of gain parameter Ai, which, by (7-153) gives a differential voltage gain of Ad =
2Ai or equivalently, (−2Af).
The final performance metric of interest is the common mode rejection ratio, ρ, which
is simply the ratio of differential mode to common mode gains. From (7-153) and (7-155),
Ai − A f
A
ρ d =
.
(7-156)
Ac
Ai + A f
The common mode rejection ratio, as its name implies, is a measure of the ability of a differential network to reject, or at least substantively attenuate, the network responses to common mode
input signals. Since Ac is zero for complete rejection of applied common mode signals, the idealized value of the common mode rejection ratio is ρ = ∞.
Equations (7-153), (7-155), and (7-156) can be used to express the output responses in
(7-152) in the form,
A ⎛
2V ⎞
⎛A ⎞
Vo1 = AcVci + ⎜ d ⎟ Vdi = d ⎜ 1 + ci ⎟Vdi
2 ⎝
ρVdi ⎠
⎝ 2 ⎠
.
(7-157)
⎛
⎞
A
A
2V
⎛
⎞
Vo2 = AcVci − ⎜ d ⎟ Vdi = − d ⎜ 1 − ci ⎟Vdi
2 ⎝
ρVdi ⎠
⎝ 2 ⎠
We have already seen, as is confirmed by the foregoing result, that the differential output response in a balanced differential network is divorced of a common mode signal component. But
interestingly, we now gather that
A ⎛
2V ⎞
⎛A ⎞
⎛A ⎞
Vo1 = AcVci + ⎜ d ⎟ Vdi = d ⎜ 1 + ci ⎟Vdi ≈ ⎜ d ⎟Vdi
2 ⎝
ρVdi ⎠
⎝ 2 ⎠
⎝ 2 ⎠
,
(7-158)
Ad ⎛
2Vci ⎞
⎛ Ad ⎞
⎛ Ad ⎞
Vo2 = AcVci − ⎜
⎜1 −
⎟Vdi ≈ − ⎜
⎟ Vdi = −
⎟Vdi
2 ⎝
ρVdi ⎠
⎝ 2 ⎠
⎝ 2 ⎠
which is approximately independent of the common mode input signal, provided that
⎛V ⎞
(7-159)
ρ ⎜ di ⎟ >> Vci .
⎝ 2 ⎠
Absolute value signs are adopted in the last relationship to allow for the possibility that Vdi, Vci,
and/or ρ may be negative in a particular application. In short, the individual single ended output
responses show no significant common mode deterioration if either the common mode rejection
ratio is large and/or the common mode input signal is not especially large. For this special, yet
practical, case, we note that the magnitude of the single ended to differential input voltage gains,
Vo1/Vdi and Vo2/Vdi, are identical and equal to one-half of the differential gain of the of the entire
differential amplifier. Moreover, the individual single ended output responses are 180° out of
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phase with one another, which gives the circuit designer flexibility over choosing a phase inverted or a non-phase inverted single ended output response.
Although we have focused herewith on only the output voltage responses of the balanced differential amplifier under consideration, the general form of the results disclosed is
applicable to any voltage or current variable in the network. A synopsis of this general form is
Circuit Variable = Common Mode Component
(7-160)
± Half Differential Mode Component ,
where it is understood that the plus (+) sign applies when the circuit variable of interest is associated with that part of the network that is driven by +Vdi/2, and the minus (−) sign applies to that
part of the system that is driven by −Vdi/2. For example, consider currents I1 and I2 in Figure
(7.45), where I1 flows out of Amplifier #1, which is excited at its input port by a signal voltage
whose differential component is +Vdi/2. On the other hand, current I2 flows out of Amplifier #2,
whose input differential signal is −Vdi/2. We note in accord with the defining nature of common
mode signals, that both amplifiers are excited by a common mode signal component, Vci. Letting
subscript “d” designate differential mode response and subscript “c” denote common mode response, we use (7-160) to write for currents I1 and I2,
I
I1 = I c1 + d 1
2
.
(7-161)
I d1
I 2 = I c1 −
2
Because of circuit linearity, we understand that current Ic1 is linearly related to the common
mode input voltage, Vci, while differential current Id1 is directly proportional to the differential
input excitation, Vdi. Although currents I1 and I2 have different values because of the phase
inversion ascribed to their differential components, both currents share the same common mode
ingredient and the same magnitude of differential component. This observation synergizes with
our perception of a balanced amplifier. Its propriety can be confirmed qualitatively by mentally
applying superposition theory to the network in Figure (7.45). To wit, if Vdi is set to zero,
thereby constraining the differential components of all circuit variables to zero, voltage Vci is the
only voltage applied to the input ports of each amplifier. But because each amplifier and its
terminations are identical in all electrical respects, a current of I1 = Ic1 generated by Vci applied to
Amplifier #1 must mirror the common mode component of current I2 spawned by Vci, which is
simultaneously applied to Amplifier #2. With Vci set to zero, the common mode components of
all network variables are vanquished, and +Vdi/2 is applied to Amplifier #1, while the negative of
this voltage excites the input port of Amplifier #2. Once again, linearity allows us to state that if
+Vdi/2 causes a current of Id1/2 to flow in the third lead of Amplifier #1, the corresponding lead
of Amplifier #2 necessarily conducts a current of −Id1/2. Yes, a negative differential current is
plausible for we must remember that all of these currents represent only signal components of
corresponding net currents; that is, they are changes about respective quiescent operating levels.
A problem with the foregoing heuristic arguments occurs with respect to the voltages,
Vb, Vk, and Vl, which are established at circuit nodes lying on the electrical centroid of the network. In other words, are the differential components of these centroid variables associated with
+Vdi/2 or with −Vdi/2? One way of addressing this dilemma, which we will exemplify with voltage Vk, entails blindly writing
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V
Vk = Vck + dk
2
.
(7-162)
Vdk
Vk = Vck −
2
Clearly, (7-162) makes engineering sense only if the presumed differential part, Vdk, of voltage
Vk is zero. This postulate infers that Vk contains no differential component and therefore only a
common mode component, Vck. Our argument is reasonable in that if the indicated +Vdi/2 incurs
a rise in voltage Vk, the corresponding −Vdi/2 applied to the second amplifier causes a decrease in
Vk by precisely the same amount as the observed initial increase. Hence, no net change is manifested in voltage Vk if only a differential input signal is applied to the overall configuration.
The situation just described is reminiscent of the seesaws we enjoyed in our childhood.
Upon mounting the seesaw, a push downward by our friend sitting at one end of the seesaw is
matched by our swinging upward by precisely the same amount as the initial downward travel at
the other end, and vice versa. Accordingly, there is “differential swing” in that the motion downward (upward) at one end of the equipment is mirrored at the other end of the seesaw by upward
(downward) displacement. But despite the amount of “differential swing,” the fulcrum of the
seesaw, which is effectively the centroid of the equipment, moves neither upward nor downward.
In other words, there is no differential displacement change at the seesaw centroid. In effect, the
fulcrum is grounded, thereby allowing us to measure the amount of displacement at either end of
the seesaw with respect to the fulcrum.
An alternative way of addressing the problem at hand is to compute voltage Vk in terms
of the currents, I1 and I2, disclosed in (7-161). We glimpse in Figure (7.45) that the current flowing through resistance Rkk, which returns to ground the circuit node at which voltage Vk is established, is (I1 + I2). But from (7-161), we see that (I1 + I2) has only a common mode constituent
(actually twice the common mode current indigenous to either current I1 or current I2). If there is
no differential current implicit to (I1 + I2), there can be, if Georgey Ohm is to be placated, no
differential part to voltage Vk, which appears directly across resistance Ree.
7.7.2. HALF CIRCUIT ANALYSES
The straightforward way to assess the small signal performance of the differential pair
considered herewith entails chasing the solutions to the Kirchhoff equations written subsequent
to replacing each amplifier by its appropriate small signal model. This tack can prove both
formidable and annoying, particularly if the individual amplifiers are complex architectures.
Unfortunately, formidable analyses invariably foster complicated, if not intractable, disclosures
that inhibit an insightful understanding of circuit operation. A better analytical approach is
predicated on exploiting the architectural symmetry inherent in a balanced differential network.
7.7.2.1. Differential Mode Half Circuit
With superposition in mind, consider first the case of zero common mode input voltage,
which fosters zero common mode components to all network branch currents and node voltages.
As indicated in Figure (7.46a), voltage Vo1 sits at +Vdo/2, Vo2 = −Vdo/2, and Vi1 = −Vi2 = +Vd1/2,
where Vd1 is the voltage difference, Vd1 = (Vi1 − Vi2). For reasons that are articulated in the
preceding subsection, voltage Vk in Figure (7.45), which can assume only a common mode stature, is remanded to zero when, in fact, the common mode input signal is null. In effect, the node
at which voltage Vk is established acts as a virtual signal ground when the only prevailing input
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signal is differential in nature. Voltage Vb in the same diagram is analogous to Vk in the sense
that the node that supports this voltage, like the node supporting voltage Vk, also lies at signal
ground potential. Let us now examine voltage Vl. An inspection of the current, Ill, conducted by
the series interconnection of the two resistances labeled Rll reveals
Vd1 /2
Rs
Vdi
2
Rdi
+
Id1 /2
Rb
Ree
0
Rbb
−Idb /2
Vdi
2
Ill
Rl
0
Vk = 0
Rb
Ree
Rll
Vdo
Rkk
Vl = 0
Rdo
Rll
−Id1 /2
−
Amplifier
#2
−Vd1 /2
Rs
+
Idb /2
Vb = 0
−
Vdo /2
Amplifier
#1
−Vdo /2
Rl
−
+
(a).
Rdi /2
Rdo /2
Vd1 /2
Rs
Vdi
2
+
Amplifier
#1
Vdo /2
Idb /2
Id1 /2
Rb
Ree
Rl
Rll
−
(b).
Figure (7.46). (a). The balanced differential architecture of Figure (7.44) under the condition of null
common mode input excitation. (b). The differential mode half circuit model of the
network in (a).
Vdo
− Vl
Vdo
(7-163)
I ll =
= 2
,
2Rll
Rll
which immediately confirms Vl = 0. Like the nodes at which voltages Vk and Vb are sustained,
the junction supporting voltage Vl with respect to ground is a virtual signal ground. These
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revelations allow us to replace, for exclusively differential input excitation, the entire differential
architecture in Figure (7.45) by the half circuit offered in Figure (7.46b). Either the top half or
the bottom half of the circuit in Figure (7.45) can form the basis of this differential mode half
circuit. We have chosen the top half. If we had opted for the bottom half, the only changes
would be an input signal of −Vdi/2 and a resultant output response of −Vdo/2.
In the half circuit in Figure (7.46b), the I/O voltage gain, which is the ratio of output
signal voltage Vdo/2 to applied input signal voltage Vdi/2, is equal to the differential voltage gain,
Ad, defined by (7-153) of the balanced differential amplifier shown in Figure (7.44). We
enthusiastically note that this gain metric is obtainable through consideration of only one-half of
the original balanced network. The analytical simplifications that ensue from an investigation of
only a compressed architecture are likely to be enhanced further in that there is a distinct
possibility that Amplifier #1 in Figure (6.42b) is a familiar architecture. For example, Amplifier
#1 may be one of the networks we have already studied in depth, or it could be a combination of
two or more of these previously investigated active networks. In this event, an evaluation of the
differential gain amounts to little more than adapting previously derived results to the half circuit
model at hand.
The foregoing gain assertions apply equally well to the input and output resistances, but
we must exercise care when interpreting these resistance results. To wit, the input resistance
seen by the signal source in the differential mode half circuit model is delineated as Rdi/2 in Figure (7.46b). Parameter Rdi symbolizes the differential mode input resistance, which is to say
that it is the net effective resistance seen by the net differential input voltage, Vdi, under the
condition of zero source resistance; that is, Rs = 0. In other words, Rdi is the input resistance
referenced to the two amplifier input nodes that support voltages Vi1 and Vi2 in Figure (7.44).
But since the network in Figure (7.46) is only one-half of the original balanced configuration,
wherein all centroid nodes are returned to signal ground, the input resistance actually evaluated
in the subject half circuit diagram is literally one-half of the true differential input resistance of
the entire amplifier. An analogous situation applies to the differential mode output resistance,
Rdo, where in the present case, we have elected to include resistances Rl and Rll in the calculation.
The schematic diagram in Figure (7.46b) correctly shows that a resistance evaluation pursued at
the output port of the half circuit results in one-half of the actual differential output resistance of
the original circuit.
7.7.2.2. Common Mode Half Circuit
Having studied the balanced differential amplifier for the differential mode case in
which the common mode input signal, Vci, is held to zero, let us now turn to the common mode
situation for which the input differential signal, Vdi, is set to zero. The electrical conditions
corresponding to exclusively common mode signal excitation are highlighted in Figure (7.47a),
where all branch currents and node voltages assume their common mode values. The
corresponding common mode half circuit appears in Figure (7.47b). Several differences become
apparent when we compare this model to its differential mode counterpart in Figure (7.46b). We
can begin to underscore these differences by first examining the common mode voltage, Vcb,
which is developed at the node to which the two resistances of value Rb and the resistance, Rbb,
are incident. Unlike the differential value, Vdb, of voltage established at the subject circuit node
when the common mode signal is set to zero, voltage Vcb is not zero in that it must support the
flow of current through Rbb. This current is twice the common mode current, Icb, conducted by
each of the two resistances, Rb, whence Vcb = 2IcbRbb. The common mode half circuit, which we
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Vc1
Vco
Amplifier
#1
Icb
Rci
Rs
J. Choma
Rb
Ill = 0
Ree
2Icb
Vcb
+
Ic1
2Ic1
Vck
Rbb
Rb
Ree
Icb
Rl
Rll
Rco
0
Rkk
Rll
Ic1
Vc1
−
Amplifier
#2
Vco
Rs
Rci
Rco
−
Vci
+
Rl
(a).
Rci
Rco
Vc1
Rs
Icb
+
Vci
−
Amplifier
#1
Ic1
Rb
Vcb
Vco
Ree
Rl
Vck
2Rbb
2Rkk
(b).
Figure (7.47). (a). The balanced differential architecture of Figure (7.44) under the condition of
null differential mode input excitation. (b). The common mode half circuit model of
the network in (a).
arbitrarily choose to construct from the top half of the network in Figure (7.44a), must be faithful
to the current conducted by resistance Rb, as well as to the voltage, Vcb. Since a current of (2Icb)
rattling through a resistance of Rbb develops the same voltage that does a current of Icb conducted
by an effective resistance of (2Rbb), we place a resistance of (2Rbb) in series with the resistance,
Rb, which we have noted in Figure (7.47a) as conducting a current of Icb. An entirely analogous
situation is pervasive of resistances Rk and Rkk, whence (2Rkk) appears in series with Rk in the
common mode half circuit. Resistances Rll in Figure (7.44a) are not embedded in Figure (7.47b)
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for the simple reason that neither Rll conducts any current. This null value of current is caused
by the fact that the voltages appearing with respect to signal ground at both of the single ended
amplifier output ports are identical and, in fact, equal to the common mode voltage response, Vco.
It follows that the differential voltage generated between these two ports, and which appears
across the series interconnection of the two circuit resistances, Rll, is zero, which reflects the zero
differential signal input state to which attention is presently focused. If no current flows through
a branch, no electrical purpose is served by the branch, and it can therefore be trashed.
We now see that the voltage gain, Vco/Vci, of the common mode half circuit in Figure
(7.47b) is precisely the common mode voltage gain, Ac, of the entire balanced differential amplifier. As in the case of the differential voltage gain, which derives as the voltage gain of the
differential mode half circuit, this gain can usually be evaluated either by inspection or with the
minimal amount of analysis fostered by our experiences with previously encountered similar circuit cells. The input resistance of the common mode half circuit is denoted as Rci and is termed
the common mode input resistance. It represents the net resistance with respect to signal ground
established at both of the two amplifier input port nodes, where signal voltages Vi1 and Vi2
respectively appear in the system of Figure (7.44). Similarly, the common mode output resistance, Rco, of the balanced differential network is identical to the output resistance witnessed in
the common mode half circuit. It is the resistance with respect to signal ground at either of the
two output port nodes of the original balanced network.
7.7.2.3. Utility Of The Half Circuit Models
In the interest of clarity, it is worthwhile placing the analytical issues deriving from the
half circuit models of a balanced differential pair into perspective. Let us start with I/O gain issues. The differential gain, Ad, which is quite literally the voltage transfer function of the
differential mode half circuit in Figure (7.46b), is the ratio of the differential output voltage to
the difference between the two applied signals in the balanced pair of Figure (7.44). Specifically,
V
V − Vo2
,
Ad = do = o1
(7-164)
Vdi
Vs1 − Vs2
where we understand that all stipulated voltages are small signal components divorced of any
biasing levels. In contrast, the common mode gain, Ac, which derives as the voltage transfer
function, Vco/Vci, of the common mode half circuit in Figure (7.47b), is
Vo1 + Vo2
Vco
V + Vo2
2
(7-165)
Ac =
=
= o1
.
Vs1 + Vs2
Vci
Vs1 + Vs2
2
At least four single ended gain relationships may be of at least tacit interest to the circuit designer. The first of these is the ratio of the single ended voltage, Vo1, in Figure (7.44) to
the applied input signal, Vs1, under the condition that input signal Vs2 is held fast at zero. Using
(7-149), (7-150), and (7-157),
V
AcVs1 AdVs1
+
Vco + do
Vo1
A + Ac
2
2
2
=
=
= d
≡ A11 ,
(7-166)
Vs1 V =0
Vs1
Vs1
2
s2
Vs2 =0
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where we introduced constant A11 in the superposition relationship of (7-145). Because of the
balanced nature of the differential amplifier undergoing scrutiny, this gain can be shown to be
the same as the ratio of the second of the two available single ended output voltages, Vo2, to the
second applied input signal, Vs2, under the constraint of Vs1 = 0. In short,
Vo2
V
A + Ac
≡ o1
= d
≡ A22 ≡ A11 ≡ Ai ,
(7-167)
Vs2 V =0
Vs1 V =0
2
s1
s2
The voltage gain from the second input signal to the first single ended output, for the case of Vs1
= 0, is
V
AcVs2 Ad ( −Vs2 )
Vco + do
+
Vo1
A − Ac
2
2
2
(7-168)
=
=
= − d
≡ A12 .
Vs2 V =0
Vs2
Vs2
2
s1
Vs1 =0
Finally, the voltage gain from the first input signal to the second single ended output with Vs2 = 0
is the same as the gain just disclosed. In other words, the balanced nature of the amplifier at
hand delivers
Vo2
V
A − Ac
≡ o1
=− d
≡ A21 ≡ A12 ≡ A f .
(7-169)
Vs1 V =0
Vs2 V =0
2
s2
s1
We observe that if |Ac| << |Ad|, which reflects the requirement of a large common mode rejection ratio, ρ, all of the gains in (7-166) through (7-169) are nominally independent of the network
common mode gain and given quite simply as ±Ad/2.
The interpretation of the differential mode and common mode input and output resistances is facilitated by the conceptual port models advanced in Figure (7.48)[9]. We begin with
the input port model shown in Figure (7.48a). There is little to argue about the fact that the common mode input resistance, Rci, terminates each input port of the balanced differential amplifier
to ground. However, a potential argument surfaces concerning the resistance, Rxi, which is
shown connecting together the subject two input ports. It seems almost natural to view this resistance as the differential input resistance. Ostensibly natural inclinations can be fallacious, and
the present case supports such a prophecy. In particular, we must remember that Rdi represents
the net resistance established differentially across the two amplifier input ports. As such, we
recognize that Rdi must make due account of the port loading effected by the two common mode
input resistances, Rci. Accordingly, we must select resistance Rxi in such a manner that the net
resistance seen between input ports 1 and 2 is the differential input resistance, Rdi, computed
from the differential mode half circuit. In particular,
Rdi
Input Node:
Amplifier #1
Rxi
Vi1
Rdo
Input Node:
Amplifier #2
Vi2
Rci
Output Node:
Amplifier #1
Rci
Vo1
Output Node:
Amplifier #2
Vo2
Rco
(a).
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Rco
(b).
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Figure (7.48). (a). Conceptual circuit model for the input ports of the balanced differential amplifier in Figure
(7.44). (b). Conceptual circuit model for the output ports of the balanced differential amplifier in
Figure (7.44).
Rdi = Rxi ( 2Rci ) ,
(7-170)
which we can solve for Rxi to deliver
2Rci Rdi
Rxi =
.
(7-171)
2Rci − Rdi
As expected, large Rci, which implies minimal common mode loading of the amplifier input
ports, promotes Rxi ≈ Rdi. The situation at the output ports, which is abstracted in Figure (7.48b),
mirrors that of the input ports. Thus, we offer without analytical fanfare,
2Rco Rdo
Rxo =
.
(7-172)
2Rco − Rdo
In order to demonstrate the utility of the port resistance models, let us suppose that the
balanced differential pair of Figure (7.44) is operated with signal voltage Vs2 equal to zero and
that we wish to determine the input resistance, say Rin, seen by the signal applied to input port
#1. The applicable circuit crutch is the resistive network of Figure (7.49a), where we have terminated input port #2 to ground in the physical resistance, Rs, which, of course, must be matched in
principle to the internal resistance associated with signal source Vs1. By inspection of the subject
model, we see that
Input Node:
Amplifier #1
Input Node:
Amplifier #2
Rxi
Vi1
Vi2
Rci
Rci
Output Node:
Amplifier #1
Rxo
Vo1
Rs
Vo2
Rco
Rco
Rout
Rin
(a).
Output Node:
Amplifier #2
Rout
(b).
Figure (7.49). (a). Model used to evaluate the input resistance, Rin, seen at port #1 of the balanced differential
amplifier in Figure (7.44) under the condition that signal source Vs2 is zero. (b). Model used to
compute the output resistance, Rout, at either output port of the balanced differential amplifier in
Figure (7.44).
⎡ 2Rci Rdi
⎤
(1-173)
Rin = Rci ⎡⎣ Rxi + ( Rci Rs ) ⎤⎦ = Rci ⎢
+ ( Rci Rs ) ⎥ .
⎣ 2Rci − Rdi
⎦
We note that this input resistance is dependent on resistance Rs. But once again, this particular
Rs is not the source resistance associated with the first signal voltage, Vs1. Instead, it is the port
#2 physical resistance required to match both of the input ports of the differential configuration.
Figure (7.49b) is the model pertinent to computing the output port resistance, Rout,
which, because of amplifier symmetry, is identical for both output ports. By inspection of this
model and with (7-172) in mind, we find that the output resistance is
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⎡ 2Rco Rdo
⎤
Rout = Rco [ Rxo + Rco ] = Rco ⎢
+ Rco ⎥
⎣ 2Rco − Rdo
⎦
(1-174)
⎡⎛ 2Rco + Rdo ⎞
⎤
= Rco ⎢⎜
⎟ Rco ⎥ .
⎣⎝ 2Rco − Rdo ⎠
⎦
Equation (7-174) in general projects a net output resistance that is larger than Rco/2 for given
common mode and differential mode output resistances. We see, however, that Rout ≡ Rco if Rdo
= 2Rco, which, by (7-172), is tantamount to an infinitely large output port coupling resistance,
Rxo.
7.7.3. BALANCED DIFFERENTIAL PAIR CIRCUIT ANALYSIS
Because balanced differential circuit technology does not generally advance new analog circuit cells, its circuit level analysis relies largely on an awareness of the properties,
characteristics, and models of commonly encountered single ended circuit structures. Balanced
amplifier analysis therefore presents few challenges, save possibly for the fact that the differential and common mode performance metrics associated with balanced circuit architectures must
be clearly understood, properly interpreted, and judiciously applied to relevant problems. This
caveat renders prudent a consideration of a specific example of a balanced differential amplifier
and to that end, we shall examine the somewhat imposing structure offered in Figure (7.50). For
this amplifier, we wish to determine expressions for the low frequency, single ended, small signal voltage gain, Av = Vo2s/Vs, the input resistance, Rin, seen by the signal source comprised of the
series interconnection of Thévenin signal voltage Vs and Thévenin source resistance Rs, and the
output resistance, Rout. Although we can assuredly determine these and other amplifier metrics
accurately by considering the effects of all device model parameters, we shall adopt herewith a
simplified analytical strategy that is premised on several operating presumptions and stipulations.
(1). We shall assume that all transistors are biased in their active regimes and have very large
Early resistances. It follows that the low frequency, small signal, output port model of
every transistor consists merely of a current controlled current source, βacI, directed from
collector terminal to emitter terminal, where βac is, of course, the forward current gain of a
device, and I symbolizes the signal component of transistor base current. While this
simplified analytical procedure may be distasteful to the analytical purist, it is justifiable
from a design-oriented perspective. In particular, acceptable or desirable responses deduced from analyses predicated on simplified approximations can be viewed as a necessary condition that underpins a successful design venture. Stated bluntly, a circuit that
does not evoke proper I/O functionality under simplified −perhaps almost idealized−
conditions has little, if any, hope for functionality with realistic device models and due
consideration given to all circuit and system parasitics. To be sure, performance estimates
derived under approximate operating circumstances constitute only design necessity, sans
design sufficiency. In turn, sufficiency is best promoted by definitive manual and computer-based analyses and in more extreme cases, prototype testing.
(2). Implicit to the device modeling assumption voiced in the preceding paragraph is the
presumption that the signal frequencies implicit to signal source Vs are not so high as to require a consideration of transistor capacitances (base-emitter junction and diffusion
capacitances, base-collector transition capacitance, and collector-substrate capacitance)
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+Vcc
Rl
Q3
Vo1
R
Rx
Rl
Vy1
Q4
Vo2
Vy2
Q2
Vbias
Ru
Q3a
Q2a
Rout
Q4a
C1
C1
Ry
Q1
Q1a
Q5
C2
Rs
Rin
Rb
Ree
Ree
Rb
Rs
Rw
+
Vs
−
Rkk
Figure (7.50). An example of a balanced differential pair realized in bipolar junction transistor technology. The low frequency, small signal analysis of the amplifier is carried out in the text
for the simplifying approximation of very large Early resistances in all transistors.
(3). The circuit capacitances, C1 and C2, are chosen to behave as short-circuited branch elements for all radial signal frequencies above a proscribed minimum, say ωmin. Thus, while
we shall be cavalier by referring to the amplifier as a lowpass amplifier, in truth, the network operates acceptably only for frequencies above ωmin. Our cavalier stance is tolerable
if the 3-dB bandwidth is significantly larger than frequency ωmin.
(4). We are told that the amplifier is a balanced configuration. This balance requires that
transistor Qi be geometrically and electrically matched to transistor Qia for i = 1, 2, 3, 4.
Note that transistor Qj or Qja need not be respectively matched to transistor Qi or Qia in
order for operational balance to be effected. Thus, for example, while transistors Q2 and
Q2a must be identical, inclusive of junction areas, transistors Q1 and Q1a, which must be
a matched pair, need not have the junction areas as do Q2 and Q2a.
7.7.3.1. Casual Circuit Analysis
Viewing any comparatively intricate circuit diagram for the first time can be a daunting
ordeal for even the more venerable of circuit design engineers. This taxing experience is all too
often exacerbated by an inclination to initiate mathematical analysis without an adequate
appreciation of the design targets of the circuit at hand and without a meaningful strategy that
encourages streamlined analytical procedures that ultimately produce response disclosures
couched in mathematically meaningful and insightful forms. An impressively precise and definitive analysis that illuminates no results that are transparently applicable to circuit design is arguably a moot accomplishment in the electronic systems and circuits discipline. But approximate
disclosures whose sources of error are clearly understood and understandable are priceless assets
when we profit from them in the course of successfully navigating a design challenge. We therefore argue that the best first step to conducting a meaningful analysis of a practical circuit is to
put the pencil and paper down and to turn away from the computer. Instead, let us begin by carefully studying the circuit schematic provided us −albeit in only qualitative or visceral senses− to
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ascertain the functionality of the various active and passive circuit components embedded in the
network. If we execute this type of investigation with care and without violating any of the
fundamental precepts of circuit analysis, we just might deduce first order, but sufficiently accurate, response results that can form an engineering basis for more definitive manual and computer-assisted follow-up circuit analyses from which an optimal design realization can ultimately
ensue. Practicing this analytical tack for a variety of circuit structures has long-term benefits in
that it increases our intuitive abilities to gauge circuit dynamics and in the process, our design
skills are ultimately honed.
Let us return to the circuit schematic diagram in Figure (7.50) to deduce the basic
functionality and purposes of the various components therein.
(1). We know that a balanced differential amplifier exploits two amplifiers whose architectures, biasing, I/O terminations, and other electrical characteristics at circuit nodes and
within circuit branches are matched. We see that one of the requisite amplifiers in the balanced configuration of Figure (7.50) is forged by transistors Q1, Q2, Q3, and Q4. The
other amplifier, which is necessarily matched to the first, is formed of transistors Q1a,
Q2a, Q3a, and Q4a.
(2). We recognize transistors Q1 and Q1a as common emitter amplifiers in that signal is applied to the base terminal of Q1 with the understanding that in strict mathematical terms, a
signal of null value is likewise applied to the base of transistor Q1a. Moreover, the outputs of these transistors are extracted at their collector terminals. The common source
amplifiers at hand are emitter degenerated via resistances Ree. We recall from our earlier
travels that this emitter degeneration resistance desensitizes amplifier gain with respect to
the forward transconductances of its embedded active elements. Resistance Rkk, is required to provide a current path to ground for the emitter currents conducted by transistors
Q1 and Q1a. Without Rkk, the emitter current of one of these two transistors would be
constrained to be the negative of the net emitter current of the other transistor, which is
clearly an impossible situation.
(3). The collector current outputs of the Q1-Q1a pair are applied to common base transistors
Q2 and Q2a, ostensibly for the purpose of mitigating Miller multiplication of the basecollector depletion capacitances of transistors Q1 and Q1a. We note that the bases of Q2
and Q2a are grounded, via capacitance C2, for all signal frequencies of immediate interest,
leaving only their emitter terminals as input ports and their collectors as output ports. The
bases of these two common base transistors are biased by the power line divider comprised
of resistances Rx and Ry. It is notable that neither of these latter two devices plays a role in
the small signal performance of the amplifier. In particular, resistance Ry is shorted directly to ground through capacitance C2. Recall that C2, like all other indicated circuit
capacitances, is chosen to emulate a short circuit for frequencies of interest, presumably
under both differential and common mode circumstances. On the other hand, both
terminals of resistance Rx lay at signal ground, assuming that the power line is driven by
an essentially ideal voltage source, Vcc.
(4). A similar divider −this one formed of resistances Ru and Rw and diode-connected transistor
Q5 (which is deployed for thermal compensation of the base-emitter biasing voltages of
Q1 and Q1a)− powers up the base terminals of the common emitter transistors, Q1 and
Q1a. Only a very small static current is conducted by transistor bases and no static current
can flow through the coupling capacitances, C1. Thus, only minimal static current flows
through the bias resistances Rb. Accordingly, the static voltage developed at the collector
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terminal of transistor Q5 in the diode divider topology approximates the static voltage
manifested at the base terminals of transistors Q1 and Q1a.
(5). The load imposed on the common emitter-common base cascode formed of transistor pairs
Q1-Q1a and Q2-Q2a consists of the interconnection of the single ended resistances, Rl,
and the differentially connected resistance, R. The voltages, Vy1 and Vy2, developed across
this terminating load structure are coupled to the amplifier output ports through the balanced emitter follower comprised of the transistor pair, Q3-Q3a. We see that each of these
two emitter follower transistors is terminated in active loads formed of the matched
transistor pair, Q4-Q4a. Because only a constant bias voltage, Vbias, is applied to the base
terminals of the latter two devices, no base-emitter signal voltage prevails for either Q4 or
Q4a. Since no emitter degeneration appears in these active loads, their small signal models are comprised of only collector to emitter Early resistances. But since all device Early
resistances are presumed very large, the small signal models of Q4 and Q4a reduce to
effective open circuits at their respective collector sites. This state of affairs is indicative
of the fact that Q4 and Q4a conduct only constant currents that necessarily have no signalinduced change and therefore, zero small signal current value. In short, transistors Q4 and
Q4a behave as open circuits for the signals applied to the differential amplifier.
The foregoing engineering observations encourage us to simplify the given schematic
diagram expressly for the purpose of small signal analysis. The specific simplification that supports efficient small signal analysis is the so-called signal schematic diagram provided in Figure
(7.51). This diagram crops all biasing issues from the schematic picture, which is the reason that
the Vcc power line is now shown as a signal short circuit (this action assumes that the power line
exudes very small Thévenin impedance). More formally, the battery voltage, Vcc, has been replaced by its small signal value, which is zero, if Vcc emulates a constant voltage source. With
the line voltage removed, all variables in the circuit assume their respective small signal values.
Thus, voltage Vy1 in Figure (7.50) becomes Vy1s in Figure (7.51), voltage Vo1 is supplanted by
Vo1s, and so forth, where as usual the subscript, “s,” is understood to identify a small signal value
of a branch current or a node voltage variable. Because of the signal short circuit natures of Vcc
and capacitance C2, resistances Rx and Ry in Figure (7.50) do not appear in the signal schematic
version of the amplifier because these branch elements are short circuited for the signal frequencies of interest. In concert with the discussion above, transistors Q4 and Q4a in Figure (7.50)
become open circuits in Figure (7.51). Since transistor Q5 is a diode-connected two terminal
branch element, it is replaced by its small signal resistance value. From (7-45), this resistance,
Rd5, derives as
r +r
(7-175)
= b5 π 5 .
R
d5
β
+1
ac5
Finally, capacitances C1 are replaced by short circuits on the presumption that we are currently
focused on the signal processing characteristics of the differential amplifier for frequencies
above the lowest frequency, ωmin, of interest.
Before turning to the actual analysis of the circuit in Figure (7.51), we should also note
that since the emitter follower transistors, Q3 and Q3a, are terminated in open circuits, their
individual voltage gains are unity because of the assumptions of large Early resistances. This
fact follows immediately from the disclosures in Section (7.42). Consequently, Vy1s = Vo1s and
Vy2s = Vo2s. More definitively,
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Rl
Q3
Rl
R
Vy1s
Vo1s
J. Choma
Q3a
Vy2s
Q2
Q2a
Vo2s
Rout
Rin
Q1
Rs
Rb
Q1a
Ree
Ree
Rb
Rs
Ru
+
Vs
−
Rkk
Rd5+Rw
Figure (7.51). The signal schematic equivalent of the balanced differential amplifier shown in Figure (7.50).
V
A V
Vo1s = Vco + do = AcvVci + dv di = V y1s
2
2
,
(7-176)
Vdo
AdvVdi
Vo2s = Vco −
= AcvVci −
= V y2s
2
2
where Adv denotes the differential mode voltage gain of the balanced amplifier, and Acv is its
common mode voltage gain. From (7-149), the differential input voltage, Vdi, applied to the balanced pair is
(7-177)
Vdi = Vs ,
while by (7-150), the corresponding common mode input signal voltage, Vci, is
V
Vci = s .
(7-178)
2
It follows from (7-169) that the desired overall voltage gain, Av, of the network undergoing
investigation is
V
A − Acv
Av = o2s = − dv
.
(7-179)
Vs
2
which underscores our need to evaluate the differential and common mode gains in order to
determine the overall single ended voltage gain of the balanced differential amplifier.
7.7.3.2. Refined Circuit Analysis
We shall rely on the pertinent half circuit models that we conceptually developed in
Section (7.7.2) to evaluate the differential mode and common mode voltage gains of the circuit
before us. Figure (7.52a) is the differential mode half circuit model of the simplified amplifier
schematic of Figure (7.51). In concert with our earlier discussions, the circuit node to which
resistance Rkk is connected, the node to which the resistances, Ru and (Rd5+Rw), are incident, and
the mid point of resistance R are grounded. Since the half model in question applies only to
differential mode, all circuit node voltages, as well as all branch currents, are divorced of common mode components and indeed have only half amplitude differential mode signal compoMing Hsieh Department of Electrical Engineering
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nents. Indeed, the input signal applied to the half circuit is now Vdi/2. At the output port, we
have made use of the fact that the emitter follower transistor, Q3, delivers unity gain, whence its
output signal voltage, Vdo/2, is identical to the signal voltage that prevails at its base terminal.
Rl
Rl
Q3
Vdo /2
R/2
Q3
Vco
Vdo /2
Rdi /2
Vdii /2
Vdi
2
+
Ico
Rco
Ido /2
Rdo /2
Q2
Q2
Rs
Vco
Rci
Ic1
Vcii
Id1 /2
Q1
Q1
Rs
Rb
Ree
Rb
Ree
+
2(Rd5+Rw)||Ru
Vci
−
2Rkk
−
(b).
(a).
Figure (7.52). (a). Differential mode half circuit schematic diagram of the balanced differential amplifier in
Figure (7.50). (b). Common mode half circuit schematic diagram of the balanced differential
pair in Figure (7.50). All branch and node variables in either diagram are understood to be signal currents and voltages.
We observe further that the indicated input resistance is Rdi/2; that is, it is one-half of
the differential input resistance of the entire balanced amplifier. Using (7-15),
R
di = R ⎡ r + r + β
+1 R ⎤ ≈ R ,
(7-180)
b ⎣ b1 π 1
ac1
ee ⎦
b
2
where the indicated approximation is valid if gain parameter βac1 for transistor Q1 is sufficiently
large. Recalling our work with emitter followers, and particularly remembering (7-61), the indicated half differential output resistance, Rdo/2, is simply the resistance presented by transistor Q3
at its emitter terminal. Within the framework of our Early resistance approximation, this resistance is
⎛
R⎞
⎜ Rl 2 ⎟ + rb3 + rπ3
R
⎠
do = ⎝
(7-181)
.
β
+1
2
(
)
ac3
We now turn to the calculation of the differential voltage gain, Adv. In Figure (7.52a),
the signal voltage, Vdii/2, established at the base node of transistor Q1 is simply a voltage divider
function of the input signal, Vdi/2. This is to say that the Thévenin signal voltage, say VdiT, driving the base of transistor Q1 derives from
⎛ R
⎞V
V
k V
diT = ⎜
b ⎟ di = b di ,
(7-182)
⎜R + R ⎟ 2
2
2
s⎠
⎝ b
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where
Rb
(7-183)
Rb + Rs
is the Thévenin input port divider. Of course, the Thévenin resistance seen by the Q1 base is
simply Rb||Rs = kbRs. In view of these disclosures the signal collector current of Q1 is
I
⎛ kbVdi ⎞
d1 = g
(7-184)
,
me1 ⎜⎜ 2 ⎟⎟
2
⎝
⎠
where the forward transconductance, gme1, of transistor Q1 (and Q1a) is, appealing to (7-22),
kb =
=
β ac1
(7-185)
.
+r + β
+1 R
b s
b1 π 1
ac1
ee
With a presumed infinitely large Early resistance, the output resistance of transistor Q1 in the
signal schematic of (7-52a), which is the resistance of the current signal source that activates
transistor Q2, is infinitely large. Accordingly, (7-84) projects a common base current gain in the
present case of αac2. It follows from (7-184) and (7-185) that the half differential output current,
Ido/2, is
I
⎛ I d1 ⎞
⎛ kbVdi ⎞
do = α
g
=α
⎜
⎟
ac2 ⎜ 2 ⎟
ac2 me1 ⎜⎜ 2 ⎟⎟
2
⎝
⎠
⎝
⎠
(7-186)
⎤⎛ k V ⎞
⎡
α ac2 β ac1
⎥ ⎜ b di ⎟ .
= ⎢
⎢k R + r + r + β
+ 1 R ⎥⎥ ⎜⎝ 2 ⎟⎠
ac1
ee ⎦
⎣⎢ b s b1 π 1
Because transistor Q3 is terminated in an active current sink boasting infinitely large input resistance, the resistance presented to the single ended output port by the base of transistor Q3 is simply the parallel interconnection of resistances Rl and R/2. This shunt resistance connection conducts a half differential current of Ido, which gives rise to a half differential output voltage, Vdo/2,
of
V
I
do = − ⎛ do ⎞ ⎛ R R ⎞
⎜⎜
⎟⎟ ⎜ l
⎟
2
2
2⎠
⎝
⎠⎝
(7-187)
⎡
⎤
α ac2 β ac1
⎛ kbVdi ⎞
R
⎛
⎞
⎥ R
= −⎢
⎜
⎟ .
⎢k R + r + r + β
⎥ ⎜⎝ l 2 ⎟⎠ ⎜ 2 ⎟
+
1
R
⎝
⎠
⎢⎣ b s b1 π 1
ac1
ee ⎥⎦
g
me1
k R +r
(
)
(
)
(
)
The differential voltage gain of the balanced pair in Figure (7-44), now follows as
⎡
⎤
V
α ac2 β ac1kb
⎥⎛R R ⎞ .
= −⎢
A = do
dv
⎥ ⎜⎝ l 2 ⎟⎠
⎢k R + r + r + β
V
1
R
+
di V =0
ac1
ee ⎦⎥
⎣⎢ b s b1 π 1
(
ci
)
(7-188)
We should be clear about the proviso, Vci = 0, which is appended as a subscript of this voltage
gain equation. The subject qualifier is automatically satisfied in the differential mode half circuit
of Figure (7.52a). In particular, Figure (7.52) applies exclusively to differential mode excitation,
which means that the common mode component, Vci, of the applied signal source is naturally
constrained to zero. As expected, we see in (7-188) that the emitter degeneration resistance, Ree,
reduces the differential gain sensitivity to transistor gain parameter βac1. Of course, the price
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paid for this reduced sensitivity is reduced gain. We also notice that since the divider constant,
kb, is obviously less than one, kb reduces the voltage gain magnitude. Such degradation is kept
minimal if the biasing resistance, Rb, in (7-183) is selected to be significantly larger than signal
source resistance Rs.
Figure (7.52b) is the common mode half circuit equivalent for the subject balanced
differential amplifier. In this model, the signal source is the common mode input voltage, Vci,
and all node voltage and branch currents, inclusive of the output voltage variables, assume their
respective common mode signal values. No differential mode voltage or current components
prevail in this model because the differential part, Vdi, of the applied input signal is set to zero.
Three topological differences prevail between the common mode half circuit and its differential
mode brethren. First, the nodes to which resistances Rb, Ru, and (Rd5+Rw) are incident in Figure
(7.51) are not grounded for common mode excitation. Since an amplifier operated with common
mode input has common mode signal voltage applied to both input ports of a balanced pair, the
current conducted by the shunt interconnection of resistances Ru and (Rd5 + Rw) is necessarily
twice the signal current that flows through either resistance Rb. Thus, the common mode model
places a resistance of 2(Rd5 + Rw)||Ru in series with biasing resistance Rb, as shown in Figure
(7.52b). For the second topological difference, the argument just invoked applies equally well to
resistance Rkk in Figure (7.51), whence we place a resistance of 2Rkk in series with the emitter
degeneration element, Ree. Finally, resistance R/2 no longer shunts the drain load resistance, Rl.
In Figure (7.51) we witness R as connected between the two output ports. Since both of these
output nodes support the same common mode signal response, Vco, no current flow through R
can be supported, which allows resistance R to be removed from the circuit.
By inspection of the common mode half circuit in Figure (7.52b), the indicated common mode input resistance, Rci, is
R = ⎡ R + 2 R + R ⎤ ⎡r + r + β
+ 1 R + 2R ⎤ ,
(7-189)
ci
d5
w ⎦ ⎣ b1 π 1
ac1
ee
kk ⎦
⎣ b
where we have exploited the insights we gained about the input resistance of common emitter
amplifiers whose utilized BJTs have very large Early resistances.. The effective input resistance,
Rin, can now be determined through a direct substitution of (7-189) and (7-180) into (7-173).
This substitution exercise is a task best left to the reader. But for the generally practical case
entailing large Rkk, large βac1 (which combine to deliver Rci ≈ Rb) and Rb >> 2(Rd5 + Rw),
(7-190)
Rin ≈ Rb ,
which synergizes with our intuitive view of the input port of the amplifier in Figure (7.51).
(
)
(
)(
)
An inspection of the output port in Figure (7.52b) reveals a common mode output resistance, Rco, of
R +r +r
b3
π3 ,
(7-191)
R = l
co
β
+1
ac3
which approximates Rdo/2 in (7-181) if, as is likely if differential voltage gain is not to be seriously compromised, R/2 >> Rl. Using (7-174), (7-191) and (7-181) yield the analytical expression for the net output resistance, Rout. To the extent that R/2 >> Rl, which reduces Rco to Rco ≈
Rdo/2,
R +r +r
b3
π3 .
(7-192)
R ≈ R = l
co
co
β
+1
ac3
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J. Choma
This result is self-evident in that if resistance R is large in Figure (7.51), the output port resistance of the balanced differential amplifier is little more than the output resistance of emitter follower Q3a, whose expression is (7-192) when the device Early resistance is taken to be infinitely
large.
The only major task remaining is the derivation of the common mode gain of the
differential network. In Figure (7.52b), the Thévenin (open circuit) value, say VciT of the common mode signal voltage, Vcii, developed at the base of transistor Q1 is seen as
⎧ R + ⎡2 R + R
R ⎤ ⎫
⎪
b ⎣
d5
w
u⎦ ⎪
(7-193)
V
= ⎨
⎬Vci = kcVci ,
ciT
⎪ Rb + ⎡ 2 Rd5 + Rw Ru ⎤ + Rs ⎪
⎣
⎦
⎩
⎭
where the input port Thévenin divider, kc, is
R + ⎡2 R + R
R ⎤
b ⎣
d5
w
u⎦
k =
.
(7-194)
c
⎡
⎤
R + 2 R +R
R + R
b ⎣
d5
w
u⎦
s
The common mode signal collector current, Ic1, conducted by transistor Q1 follows as
(
(
(
I
c1
= g
mc1
)
(
)
)
)
( kcVci ) ,
(7-195)
where, noting an effective emitter degeneration resistance of (Ree + 2Rkk), the common mode
value, gmc1, of Q1 forward transconductance is
β ac1
=
α ac1
≈
(7-196)
.
R + 2R
+r + β
+ 1 R + 2R
ee
kk
c s
b1 π 1
ac1
ee
kk
In arriving at (7-196), we have used the fact that the Thévenin source resistance driving the base
of transistor Q1 under common mode excitation conditions is
R + ⎡2 R + R
R ⎤ R ≡ k R .
(7-197)
b ⎣
d5
w
u⎦
s
c s
with constant kc given by (7-194).
g
mc1
{
(
k R +r
(
)(
)
}
)
The signal component, Ico, of the common mode load current is, in accordance with our
understanding of common emitter amplifier cell dynamics,
I
co
= α
I
ac2 c1
= α
g
ac2 mc1
( kcVci )
⎡
α β
ac2 ac1
= ⎢
⎢k R + r + r + β
+ 1 R + 2R
ac1
ee
kk
⎣⎢ c s b1 π 1
(
)(
)
⎤
⎥ kV
⎥ c ci
⎦⎥
(
)
(7-198)
⎛ α α
⎞
≈ ⎜ ac2 ac1 ⎟ k V .
⎜ R + 2R ⎟ c ci
kk ⎠
⎝ ee
This current flows through common base transistor Q2 and load resistance Rl so that the common
mode signal output voltage, Vco, is
(
Ming Hsieh Department of Electrical Engineering
)
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USC Viterbi School of Engineering
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V
co
Canonic Analog MOS Cells
= − I R = −α
co l
g
J. Choma
( c ci )
R kV
ac2 mc1 l
⎡
α ac2 β ac1Rl
= −⎢
⎢k R + r + r + β
+ 1 R + 2R
⎢⎣ c s b1 π 1
ac1
ee
kk
(
)(
)
⎤
⎥ kV
⎥ c ci
⎥⎦
(
)
⎛α α R ⎞
≈ − ⎜ ac2 ac1 l ⎟ k V .
⎜ R + 2R ⎟ c ci
kk ⎠
⎝ ee
Clearly, the common mode voltage gain, Acv, is
V
α ac2 β ac1kc Rl
= −
A = co
cv
V
+ 1 R + 2R
k R +r +r + β
ci V =0
c s
b1 π 1
ac1
ee
kk
di
(
)
(
≈ −
(7-199)
α ac2α ac1kc Rl
R
ee
+ 2R
)(
)
(7-200)
.
kk
The low frequency, small signal, single ended voltage gain, Vo2s/Vs, of the balanced network in Figure (7.50) can now be determined simply by plugging (7-200) and (7-188) into (7179). The delineation of the resultant “exact” gain is left as an exercise for the reader. But we
can formulate a useful approximate gain relationship by observing that the biasing resistance, Rb,
should be large to avoid excessive static current drain in the biasing of the balanced amplifier.
With Rb indeed large, the Thévenin divider constant, kb, in (7-183) closely approximates divider
constant kc in (7-194). Assume further that load resistance Rl is implemented as a resistance that
is significantly smaller than R/2. This circumstance is a likely design tack owing to circuit biasing constraints, and the desire to avoid significant differential gain degradation. Finally, we shall
assume that βac1 and/or Ree are sufficiently large so that (βac1 +1)Ree >> kbRs + rb1 + rπ1. The
resultant (approximate) differential voltage gain, Adv, is
⎡
⎤
⎡α α k R ⎤
α β k R
ac2
ac1
b
l
⎢
⎥
(7-201)
A ≈ −
≈ − ⎢ ac2 ac1 b l ⎥ .
dv
⎢k R + r + r + β
⎥
R
⎢
⎥
+1 R ⎥
ee
⎣
⎦
ac1
ee ⎦
⎣⎢ b s b1 π 1
This result and the approximate form of the common mode gain in (7-200) nets us an approximate overall, single ended voltage gain of
⎛ α α k R ⎞ ⎛ 2R
⎞
⎛ k R ⎞ ⎛ 2R
⎞
V
kk
kk
⎟ ≈ ⎜ b l ⎟⎜
⎟,
(7-202)
A = o2s ≈ ⎜ ac2 ac1 b l ⎟ ⎜
v
⎜
⎟ ⎜ 2R + R ⎟
⎜ 2R ⎟ ⎜ 2R + R ⎟
V
2R
s
ee
ee ⎠
ee ⎠
⎝
⎠ ⎝ kk
⎝ ee ⎠ ⎝ kk
where the last approximation invokes the reasonable presumptions of large βac1 and large βac2.
(
)
We note in the last result that finite Rkk serves to incur a slight attenuation of the single
ended voltage gain of the differential amplifier. Obviously, large Rkk minimizes this gain
degradation. In (7-200), we note that large Rkk, engenders a small common mode gain, which we
earlier hypothesized as a desirable design target. Recall that a small common mode gain is tantamount to an appreciable rejection of common mode inputs, which is especially laudable when
such inputs are manifested by undesirable parasitic signals or other spurious phenomena. We are
therefore led to believe that a small common mode gain tracks with minimal degradation of single ended gain. Moreover, and in light of the fact that the differential mode gain is independent
of Rkk, we are led to believe that the common mode rejection ratio is rendered large if Rkk is large.
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We can easily confirm the latter contention by combining (7-201) and (7-200) with (7-156) to
arrive at the first order approximation of the common mode rejection ratio, ρ, of
A
2R
(7-203)
ρ = dv ≈ 1 + kk ,
A
R
cv
ee
which advances rejection as rising linearly with Rkk. Unfortunately, there are practical limits as
to how large Rkk can be in the circuit at hand. Specifically, a large Rkk burdens the supply voltage, Vcc, in that independent of its resistance value, Rkk must conduct the sum of currents flowing
through transistors Q1 and Q1a. For large Rkk, Georgey O. warns us that the resultant potential
drop across Rkk, which must be supplied by voltage Vcc, is commensurately large.
+Vcc
Rl
Q3
Vo1
Rx
R
Rl
Vy1
Q4
Vo2
Vy2
Q2
Vbias1
Ru
Q3a
Q2a
Rout
Q4a
C1
C1
Ry
Q1
Q5
Q1a
C2
Rs
Rin
Rb
Ree
Ree
Rb
Rs
Rw
+
Vs
−
Vbias2
Q6
Figure (7.53). Modified version of the balanced differential amplifier in Figure (7.50). In this version,
resistance Rkk in Figure (7.50) is replaced by an active current sink formed by transistor
Q5 and its base-emitter biasing voltage, Vbias2.
We can, however, get our proverbial cake (large Rkk) and be allowed to eat it too (no
excessive burden imposed on Vcc), by replacing Rkk with an active current sink, as is suggested in
the modified schematic diagram of Figure (7.53). The active current sink in question is forged
by transistor Q6, whose base-emitter biasing potential is supplied by a constant, and thus signal
invariant, voltage, Vbias2. Because the base-emitter voltage of transistor Q6 is constant, no βac6I
controlled source prevails in the small signal model of this transistor. Indeed, said model is comprised solely of a collector-emitter Early resistance, say ro6. This means that in (7-198) through
(7-200) and in (7-202) and (7-203) resistance Rkk is supplanted by ro6, which, depending on the
geometry, collector biasing current, and collector-emitter quiescent voltage of transistor Q6, can
be several tens of thousands of ohms It follows that the common mode rejection ratio, ρ, can be
rendered very large. Indeed, if we continue our previously established precedent of very large
Early resistances in the modified amplifier of Figure (7.53), ρ tends toward its idealized value of
infinity. Intuitive support for this contention derives from a casual re-inspection of the common
mode half model in Figure (7.52b). If in this structure, resistance Rkk, which is presently replaced by ro6, tends toward infinity, the emitter terminal of transistor Q1 is left open circuited,
which obviously precludes any signal current flow through Q1, Q2, and the load termination, Rl.
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With zero current conducted by Rl, the common mode output response, Vco, is held at zero,
whence zero common mode gain and correspondingly infinitely large common mode rejection
ratio ensue.
In the preceding paragraph, we suggest that Early resistance ro6 can be rendered significantly larger than the previously utilized passive resistance, Rkk. For reasonable collector currents, a large Early resistance invariably requires a proportionately large device geometry, which
in our minds automatically flags potential frequency response issues. But the frequency response
capabilities of transistor Q6 are immaterial since for differential mode, the circuit node to which
the collector of Q6 is connected is a virtual ground. And it should be noted from (7-158) that for
the very large common mode rejection ratio bred by a large Early resistance in Q6, differential
operation is the only operational mode of consequence. A final noteworthy point is that unlike
the electrical ramifications of a large passive resistance, Rkk, a large ro6 does not require an
overtly large collector to emitter voltage on Q6. To be sure, we require Q6 to operate in its active regime in order to achieve large Early resistance. But active operation requires only that the
collector-emitter voltage of transistor Q6, which effectively replaces the original potential drop
across Rkk, be slightly larger than its base-emitter biasing potential. This operating voltage can
be quite small and indeed, it is typically of the order a volt or even less.
7.7.4. DIFFERENTIAL TO SINGLE ENDED CONVERTER
AcVci+
Balanced
Differential
Amplifier
+
−
−
+
Vods
= Ads AdVdi
Vdi
2
Vci
+
Vdi
2
Rs
+
AdVdi
−
AdVdi
AcVci −
2
−
Rs
AdVdi
2
Figure (7.54). Conceptual illustration of the use of a differential to single ended converter (DSEC) in
conjunction with a balanced differential amplifier.
We have learned that the differential output response of a balanced differential amplifier is divorced of a common mode signal component regardless of the magnitude of the common mode rejection ratio of the amplifier. Extracting an amplifier output response in a strictly
differential form is therefore appealing from the standpoint of obliterating common mode spurs
that result from undesirable electrical phenomena coupling to the input ports of a balanced pair.
But in communication circuits and in a multitude of other system applications, the inability of a
differential output response to maintain a common ground between amplifier input and output
ports is invariably undesirable. The differential to single ended converter, or DSEC, addresses
this problem by converting the ungrounded differential output signal of a balanced pair to a single ended output signal (referenced to a ground that is common between input and output ports).
As is abstracted in Figure (7.54), the ungrounded differential output, AdVdi, of the balanced pair
serves as the input to the differential to single ended converter whose function is to process this
input in order to generate a single ended output response, Vods, which is proportional to its
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differential input. The constant of proportionality, Ads, of the DSEC is effectively its voltage
gain, where it is understood that the magnitude of Ads can be one, less than one, or greater than
one. In most cases, we opt for a DSEC gain that is near one in order to avoid bandwidth
degradation precipitated by large gains. In the subject diagram, voltages Vdi and Vci and parameters Ad and Ac have their usual differential circuit and system technology connotations.
+Vcc
Q2
Q2a
Cl
Vods
Q1
Q1a
Rs
AdVdi
2
+
Rs
Vbias
Q3
−
−
+
Rl
AdVdi
2
+
VQ + AcVci
−
Figure (7.55). Simplified schematic example of a differential to single ended converter
(DSEC) realized in bipolar junction transistor technology.
Figure (7.55) offers a basic bipolar technology realization of a differential to single
ended converter. Included in the common mode signal generator, AcVci, is a bias voltage, VQ.
This standby voltage prevails at the output ports of the predecessor balanced stage and is used to
bias transistors Q1 and Q1a in the DSEC. All transistors in the DSEC operate in their active domains, Q1 and Q1a are matched pairs, and likewise, Q2-Q2a are matched transistors. The DSEC
input signal voltage, (AcVci + AdVdi/2), which is applied to the base of transistor Q1, and voltage
(AcVci – AdVdi/2), which activates the base terminal of transistor Q1a, are the single ended
Thévenin output signal voltages of the preceding balanced differential pair. The source resistances, Rs, in Figure (7.55), represent the single ended output port resistances of the differential
driver whose ungrounded differential voltage response is to be converted linearly to a single
ended output response. This output response is denoted as the voltage, Vods, which appears
across load resistance Rl. Since the load resistance is capacitively coupled to the DSEC output
port, no static voltage appears across load resistance Rl. Thus, the output response contains only
a signal component. We assume that capacitance Cl is chosen large enough to enable its behavior as a short circuit for all signal frequencies of interest. In the subject figure, coupling capacitance Cl connects this output port to the collector of PNP transistor Q2a, which mirrors the current that flows through the diode-connected PNP device, Q2. In turn, the Q2-Q2a mirror is
driven by the current output signals of Q1 and Q1a.
Because the load imposed on transistor Q1 differs from the load imposed on Q1a, the
network in Figure (7.55) is not a balanced network, as are all previous differential circuits we
have encountered. In effect, the circuit at hand is a different type of differential configuration.
Circuit differences should (must) not be cause for alarm, and they are hardly a justification for
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calling 911. Rather, such differences comprise an opportunity to demonstrate circuit insights and
analytical creativity, as well as a possible opportunity to contrive conclusions that are not ubiquitously known throughout the electronic circuits community. We shall attempt to foster these
engineering goals merely through application of the basic network concepts we have exploited
throughout this document.
In1
In2
Q1
Idn1=gdn A dVdi
Q1a
Q1
Rs
AdVdi
2
Rs
Q3
+
−
+
−
Rs
AdVdi
2
AdVdi
2
+
−
+
VQ + AcVci
(b).
−
Collector
Of Q1
(a).
Icn1=gcn AcVci
gdn AdVdi
2
Collector
Of Q1a
gdn AdVdi
2
ro1
ro1
Q1
(d).
Rs
Collector
Of Q1
2ro3
+
AcVci
gcn AcVci
−
(c).
Collector
Of Q1a
gcn AcVci
Roc
Roc
(e).
Figure (7.56). (a). Circuit used to determine the Norton equivalent output signal currents of the Q1-Q1a
differential pair in the differential to single ended converter of Figure (7.55). (b). Differential
mode half circuit of the network in (a). (c). Common mode half circuit of the network in (a).
(d). Differential mode Norton equivalent output port circuit for the balanced circuit in (a).
(e). Common mode Norton equivalent output port circuit for the balanced circuit in (a).
To the foregoing ends, we partition the Q1-Q1a pair from the load subcircuit comprised
of Q2, Q2a, and the capacitively coupled load resistance for the purpose of determining the short
circuit (Norton) signal currents say In1 and In2, which are conducted by the collectors of transistors Q1 and Q1a, respectively. This partitioning produces the balanced configuration shown in
Figure (7.56a). In this model, we have removed voltage VQ from the input subcircuit because of
our present focus on exclusively small signal short circuit current responses. Because the
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subcircuit at hand is balanced, currents In1 and In2 are expressible in terms of their stereotypical
common mode and differential mode components, Icn1 and Idn1, respectively, as
I
I n1 = I cn1 + dn1
2
.
(7-204)
I dn1
I n2 = I cn1 −
2
In concert with the differential network theory propounded earlier, Icn1 is understood to be directly proportional to common mode input signal, Vci, and independent of differential mode input
signal, Vdi. Analogously, current Idn1 is independent of Vci and directly proportional to Vdi.
Specifically, we may write for the differential mode, Idn1, Norton signal current flowing in the
short circuited collector of Q1,
I
A V
dn1 = g ⎛ d di ⎞ ,
(7-205)
⎜
dn ⎜ 2 ⎟⎟
2
⎝
⎠
where by inspection of the differential mode half circuit in Figure (7.56b) and our understanding
of the fundamental characteristics of common emitter topologies, the differential mode Norton
transconductance is
≈
β ac1
(7-206)
.
+r
s
b1 π 1
In the process of deducing this transconductance result, (7-22) is used as a basis equation,
wherein an account has been made of the fact that transistors Q1 and Q1a do not use emitter
degeneration resistances. Moreover, we assume large Early resistance in the two transistors. In
the differential mode output port equivalent circuit of Figure (7.56d), we show differential mode
current sources of value ±gdnAdVdi/2, in accordance with (7-205) and (7-206). The Thévenin
resistance associated with either of these controlled sources is, by (7-19) simply the Early resistance, ro1, of Q1 (or of Q1a). Of course, this shunting resistance is very large, which means that
the controlled differential current sources behave as ideal current sources.
g
dn
R +r
On the other hand, the common mode Norton signal current, Icn1, which is highlighted
in the common mode half circuit of Figure (7.56c), is
β ac1
α
1
(7-207)
≈
≈ ac1 ≈
g
.
cn
2r
2r
+1 r
R +r +r +2 β
o3
o3
s
b1 π 1
ac1
o3
where we have once again used (7-22). In this result, ro3 represents the Early resistance of current sink transistor Q3 in Figure (7.56a). We should note that if we continue to assume infinitely
large Early resistances in all transistors embedded in the differential to single ended converter,
gcn vanishes. In other words, there is negligible common mode component to the Norton collector currents presently under investigation when the Early resistance in transistor Q3 is very large.
(
)
The common mode Thévenin shunt resistance, which we represent as Roc in Figure
(7.56e), derives from (7-19). This resistance is extremely large because of the presumption of
large ro1 and because of the very large emitter degeneration resistance of 2ro3 embraced by
transistor Q1. For all practical engineering purposes, therefore, the controlled sources in both the
differential mode output port circuit of Figure (7.56d) and the common mode output port circuit
of Figure (7.56e) are ideal current sources.
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The small signal performance characteristics of the DSEC in Figure (6.51) can now be
evaluated with the aid of the Norton output port models just developed for the input transistor
pair, Q1-Q1a. We shall continue the simplifying approximations of infinitely large Early resistances in all transistors and additionally, we shall assume that all transistors in the DSEC have
very large gain parameters, βac. With Early resistances presumed infinitely large, we arrive at
the small signal representation shown in Figure (7.57). In this model, the power supply voltage,
Vcc, is set to zero to reflect the attention focused on only small signal circuit characteristics.
Additionally, capacitance Cl is replaced by a short circuit in that its capacitance value is selected
to emulate a short circuited branch element for all signal frequencies of interest. By inspection
of the subject model, we see that the current delineated as I2s is
Q2
Q2a
I2as
Vods
Ids
I2s
gdn AdVdi
2
gcn AcVci
Ios
Ios
gcn AcVci
gdn AdVdi
2
Rl
Figure (7.57). Signal schematic macromodel of the differential to single ended converter postured
in Figure (7.55). The driving circuit for the converter has been replaced by its
Norton equivalent model. The signal schematic diagram exploits the assumptions of
infinitely large Early resistances in all transistors.
I
= g
AV
+
g
A V
dn d di .
(7-208)
2
This current flows through the diode-connected PNP transistor, Q2. To the extent that βac in
transistors Q2 and Q2a is large, current I2s is nominally the current observed in the collector and
emitter of transistor Q2. Since transistors Q2 and Q2a are matched devices possessed of identical base-emitter junction injection areas and since the base-emitter voltages applied to these two
PNP devices are the same, current I2as mirrors the Q2 collector current, which is about equal to
I2s; that is,
g A V
I
≈ I = g A V + dn d di .
(7-209)
2as
2s
cn c ci
2
Now current Ids is, by inspection of the schematic diagram in Figure (7.57),
g A V
I = g A V − dn d di .
(7-210)
ds
cn c ci
2
It follows that the output signal current, Ios, conducted by the load resistance, Rl is
(7-211)
I = I
−I ≈ g A V ,
2s
os
cn c ci
2as
ds
dn d di
which is independent of the common mode current component generated in the drain circuits of
transistor Q1 and Q1a. Since common mode responses are inherently (at least in the idealized
sense of infinitely large Early resistances and large βac) absent in the load resistance branch, we
can dispute the necessity of transistor Q3 in Figure (7.55), as opposed to the deployment of a
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simple resistance connected from the emitter terminals of Q1-Q1a and ground. In particular, (7211) confirms that the invariably large Early resistance, ro3, of transistor Q3, coupled with large
βac, substantially attenuates the common mode current response for a given common mode input
voltage signal. But since common mode currents disappear at the DSEC load, a reasonable resistance supplanting Q3 arguably suffices. Continuing with (7-211), we see that an output signal
voltage, Vods, is manifested as
V
ods
(
= I R = g
os l
)
R A V
dn l
d di
(7-212)
,
which confirms a single ended output voltage response that is proportional to the ungrounded
voltage, AdVdi, developed differentially across the output terminals of the predecessor balanced
differential amplifier. Equation (7-212) suggests, with the help of the diagram in Figure (7.54),
that the apparent single ended output to differential input voltage gain, Ads, of the DSEC is
V
Ads = ods = g dn Rl .
(7-213)
Ad Vdi
The foregoing results are, of course, only approximate in light of the approximations on
which they are predicated. Nevertheless, sufficiently large Early resistances and sufficiently
large βac in all active devices are reasonable approximations that render the approximate disclosures acceptable for design-oriented applications.
7.8.0. REFERENCES
[1]. S. Dimitrijev, Understanding Semiconductor Devices. New York: Oxford University Press,
2000, pp. 334-341.
[2]. J. M. Early, “Effects of Space-Charge Layer Widening in Junction Transistors,” Proc. of the
IRE, vol. 46, pp. 1141-1152, Nov. 1958.
[3]. H. N. Ghosh, “A Distributed Model of the Junction Transistor and its Application in the Prediction of the Base-emitter Diode Characteristic, Base Impedance, and Pulse Response of the Device,” IEEE Trans. on Electron Devices, vol. ED-12, pp. 513-531, Oct. 1965.
[4]. J. R. Hauser, “The Effects of Distributed Base Potential on Emitter Current Injection Density
and Effective Base Resistance for Stripe Transistor Geometries,” IEEE Trans. on Electron Devices, vol. ED-11, pp. 238-242, May 1965.
[5]. J. J. Ebers and J. L. Moll, “Large-Signal Behavior of Junction Transistors,” Proc. of the IRE,
vol. 42, pp. 1761-1772, Dec. 1954.
[6]. R. L. Geiger and E. Sánchez-Sinencio, “Active Filter Design Using Operational Transconductance Amplifiers: A Tutorial,” IEEE Circuits and Devices Magazine, pp. 20-32, March 1985.
[7]. D. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons,
Inc., 1997, chap. 15.
[8]. L. J. Giacoletto, Differential Amplifiers. New York: Wiley-Interscience, 1970.
[9]. S. A. Witherspoon and J. Choma, Jr., “The Analysis of Balanced Linear Differential Circuits,”
IEEE Transactions on Education, vol. 38, pp. 40-50, February 1995.
Ming Hsieh Department of Electrical Engineering
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