DESIGN/ANALYSIS CONSULTANTS, INC.
www.daci-wca.com
The Designer’s Analyst
Is Thermal Runaway Possible?
KEY THERMAL FORMULAS for SWITCHMODE FETS
by Ed Walker
Rev B
© DACI. This document is for the sole use of DACI's Design Master™ Professional Edition subscribers
In the last group session, I asked everyone to bring with them today the remains of an
unsuccessful FET power circuit. I see that all of you have at least one charred and melted
mess with you; good! Look around everyone; you are not alone. Doesn’t that make you feel
better? No? Well, let’s see what we can do to prevent this from happening in the future.
First, I will tell you a secret. …Let me close the shades and be sure the door is locked… there.
Now, here’s the awful truth that you must know: Even though you’ve been told that FETs are
immune to thermal runaway, it isn’t true.
***
USING ANALYSIS TO AVOID FET
THERMAL BLOWUPS
Use this application note for coolrunning FET power designs
Some FET vendors like to say that their devices
are “free from thermal runaway.” Yet if you
check the temperature coefficient of the FET’s
on-resistance RDSon --- assuming the vendor
provides the data --- you will see that it is
positive, around 0.4% to over 1.0% per degree
C, depending on the FET. Therefore as a power
FET heats up during operation, RDSon will
increase. As RDSon increases, the FET will heat
up further, which increases RDSon, which heats
up the FET even more, until…
“Your Circuit
Melted!”
Vin
Pout
Now, if you recall your basic feedback theory, you know
that the above scenario will only occur if the positive
thermal feedback loop gain = 1. In fact, it is possible to
have an appreciable amount of positive feedback and still
be perfectly stable. For example, the positive thermal
feedback in FETs is essential in allowing them to be used
in parallel. So it is only if this positive feedback becomes
too large that we have a problem.
Avoiding Thermal Problems in Switchmode FETs_RevB / Page 1 of 4
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The positive thermal loop gain for a FET is
given by
Rtot * Irms^2 * RDSon25 * TCRDS
Therefore, thermal runaway can occur for the
following condition:
Irms
Psw
Pmisc
RDSon25
Rtot
Criterion for FET Thermal Runaway
Rtot * Irms^2 * RDSon25 * TCRDS = 1
[1]
Ta
TCRDS
TERMS
rms amps through FET
FET switching losses, watts
total of all other losses contributing to
FET rms amps
FET on-resistance at 25C, ohms
total thermal resistance from FET
junction to air, C/W
= Rjc + Rcs + Rsa
Rjc = FET junction-case thermal
resistance, C/W
Rcs = case-sink insulator thermal
resistance, C/W (if required)
Rsa = heat sink to air thermal
resistance, C/W
maximum ambient temperature (e.g.
air temperature around heat sink), C
FET on-resistance temperature
coefficient, /C
maximum desired FET junction
temperature, C
However, it is not enough to simply avoid the
TjMAX
critical point. Although operation will be
thermally stable when the left side of the
criterion is less than 1, you can still experience a significant increase in FET junction temperature as the
loop gain approaches 1. This is called thermal amplification. To keep Tj from being grossly amplified,
the loop gain should be much less than 1:
Minimizing Thermal Amplification
Rtot * Irms^2 * RDSon25 * TCRDS << 1
[2]
The above criterion holds true for any topology; buck, boost, flyback, etc. Keeping the thermal loop gain
small will not only avoid obvious thermal problems like FET overheating and blowup, but will also help to
prevent more subtle effects, such as loss of regulation due to excessive RDSon.
…the experienced designer
will always use the value of
RDSon for the targeted
maximum junction
temperature of the FET
Fortunately, even if blissfully unaware of the above criterion, the
experienced designer will always use the value of RDSon for the
targeted maximum junction temperature of the FET when crafting a
circuit. It turns out that this standard design practice, plus other
considerations such as RDSon selection for efficiency purposes, will
automatically result in a small loop gain …usually.
Therefore, yes, it is possible for FETs to experience thermal runaway. But no, in practice this will not
normally occur, provided the high-temp RDSon was considered. If you have any doubts about your existing
designs, apply [2] above to them. If the loop gain is more than about 0.2, you may want to double-check
your FET junction temperature and heat sink, as discussed next.
FET JUNCTION TEMPERATURE and HEAT SINK, including THERMAL FEEDBACK
You can use the formulas below (derived in Appendix A) to analytically confirm your FET’s maximum
junction temperature, or to select a heat sink. These formulas are applicable to any FET switchmode
topology. For a sample analysis, see "FET Thermal Stress Boost & Flyback.DM."
Avoiding Thermal Problems in Switchmode FETs_RevB / Page 2 of 4
Use this formula to check the junction temperature of FET switchmode power devices:
(Ta + Rtot * (Irms^2 * RDSon25 * (1 - TCRDS * 25) + Psw + Pmisc))
Tj =
---------------------------------------------------------------------------------------------------------------------------------------------
C
[3]
(1 - Rtot * Irms^2 * RDSon25 * TCRDS)
Use this formula to check heat sink requirements for FET switchmode power devices:
TjMAX - Ta
Rtot =
--------------------------------------------------------------------------------------------------------------------------------------
C/W
[4]
Irms^2 * RDSon25 * (1 + TCRDS * (TjMAX - 25)) + Psw + Pmisc
Rtot is the total path thermal resistance. To define your heat sink, subtract Rjc (FET junction-case thermal
resistance) and Rcs (insulator thermal resistance) to obtain the allowable heat sink thermal resistance
Rsa, C/W.
The derived expression for Tj [3] above indicates the critical point for thermal blowup as discussed earlier;
i.e. when the denominator equals zero.
HEAT SINK SELECTION EXAMPLE
150W commercial flyback converter:
and
so
Ta = 50C max spec + 10C internal rise
= 60C
TjMAX = 150C
Pout = 150W
fS = 75KHz
Vin = 200V
FET = IRFIB5N65A (560V 5.1A)
RDSon25 = 0.93 ohms max
D = 0.40 at 150W output
TCRDS = 0.014 /C (use a straight-line
approximation in the highertemperature region of interest; see
red line)
VdsOFF = 400V
tFI = 18ns typ * 1.5 max est = 27ns
Pin = Pout/Eff
Eff = efficiency = ~90% (estimated allowance)
Iin = Ipk/2*D since Ipk is sawtooth
Iin = Pin/Vin = Pout/(Eff*Vin)
Ipk = 2*Iin/D = 2*Pout/(Eff*Vin*D)
= 2*150/(0.9*200*0.4) = 4.17Apk
Irms for sawtooth = SQR(D/3) * Ipk = SQR(0.4/3) * 4.17 = 1.52Arms
Pcond = 1.52^2 * 0.93 * (1+0.014 * (150 – 25)) = 5.91W
Psw = 75E3*4.17*400*27E-9 = 3.38W
Pmisc = 5W
Check 90% efficiency assumption: Actual = 150/(150+5.91+3.38+5) = 91%; ok
Avoiding Thermal Problems in Switchmode FETs_RevB / Page 3 of 4
Heat Sink:
Rtot = (TjMAX – Ta)/(Irms^2 * RDSon25 * (1 + TCRDS * (TjMAX – 25)) + Psw +Pmisc)
= (150 – 60)/(1.52^2 * 0.93 * (1 + 0.014 * (150 – 25)) + 3.38 + 5)
= 6.3 C/W
1
Heat sink Rsa = Rtot – Rjc – Rcs = 6.3 – 2.1 – 0.3 = 3.9 C/W
Stability Criterion = Rtot * Irms^2 * RDSon25 * TCRDS = 6.3 * 1.52^2 * 0.93 * 0.014
= 0.19 << 1; OK
Note 1: When tolerances are included for the above per WCA+ methodology, the actual heat sink Rsa will be less.
Considering the tolerances is more accurate / cost effective than arbitrarily using a derating factor for TjMAX.
APPENDIX A
The junction temperature of the FET is given by
Tj = Ta + Rtot * (Pcond + Psw + Pmisc), C
= Ta + Rtot * (Irms^2 * RDSon + Psw + Pmisc)
Accounting for the temperature coefficient of RDSon
RDSon = RDSon(25C) * (1 + TCRDS * (Tj – 25)), ohms
Tj = Ta + Rtot * (Irms^2 * RDSon(25C) * (1 + TCRDS * (Tj – 25)) + Psw + Pmisc), C
From the above, the junction temperature term Tj also appears on the right side of the equation; i.e.,
thermal feedback. Rearranging to obtain Tj alone on the left side,
Tj = Ta + Rtot * (Irms^2 * RDSon25 * (1+TCRDS * (Tj – 25)) + Psw + Pmisc)
= Ta + Rtot * Irms^2 * RDSon25 * (1+TCRDS * (Tj – 25)) + Rtot * (Psw + Pmisc)
= Ta + Rtot * Irms^2 * RDSon25 + Rtot * Irms^2 * RDSon25 * TCRDS * Tj - Rtot * Irms^2 * RDSon25 *
TCRDS * 25 + Rtot * (Psw + Pmisc)
Tj - Rtot * Irms^2 * RDSon25 * TCRDS * Tj =
Ta + Rtot * (Irms^2 * RDSon25
- Irms^2 * RDSon25 * TCRDS * 25 + Psw +Pmisc)
Tj * (1 - Rtot * Irms^2 * RDSon25 * TCRDS) =
Ta + Rtot * (Irms^2 * RDSon25 * (1 - TCRDS * 25) + Psw +Pmisc)
Tj = (Ta + Rtot * (Irms^2 * RDSon25 * (1 - TCRDS * 25) + Psw + Pmisc)) /
(1 - Rtot * Irms^2 * RDSon25 * TCRDS) C
Solving for Rtot:
TjMAX = Ta + Rtot * (Irms^2 * RDSon25 * (1+TCRDS * (Tj – 25)) + Psw +Pmisc) C
Rtot = (TjMAX – Ta)/(Irms^2 * RDSon25 * (1+TCRDS * (TjMAX – 25)) + Psw +Pmisc) C/W
Avoiding Thermal Problems in Switchmode FETs_RevB / Page 4 of 4