Precision Analog Microcontroller
Small Package, 12-bit Analog I/O, ARM7TDMI® MCU
ADuC7020/ADuC7021/ADuC7022
Preliminary Technical Data
FEATURES
On-Chip Peripherals
UART, dual I2C and SPI Serial I/O
14-Pin GPIO Port
2 X General Purpose Timers
Wake-up and Watchdog Timers
Power Supply Monitor
PLA – Programmable Logic (Array)
Power
Specified for 3V operation
Active Mode: 6mW (@1MHz)
300mW (@45MHz)
Packages and Temperature Range
40 Pin LFCSP 6x6mm body package
Fully specified for –40°C to 85°C operation
Tools
Low-Cost QuickStart Development System
Full Third-Party Support
Analog I/O
Multi-Channel, 12-bit, 1MSPS ADC
- 5 Channels on the ADuC7020
- 8 Channels on the ADuC7021
- 10 Channels on the ADuC7022
Differential and single-ended modes
0 to Vref Analog Input Range
Multi-Channel 12-bit Voltage Output DACs
- 4 Outputs on the ADuC7020
- 2 Outputs on the ADuC7021
On-Chip 20ppm/°C Voltage Reference
On-Chip Temperature Sensor (±3°C)
Uncommitted Voltage Comparator
Microcontroller
ARM7TDMI Core, 16/32-bit RISC architecture
JTAG Port supports code download and debug
Clocking options: - Trimmed On-Chip Oscillator (± 2%)
- External Watch crystal
- External clock source
45MHz PLL with Programmable Divider
Memory
62k Bytes Flash/EE Memory, 8k Bytes SRAM
In-Circuit Download, JTAG based Debug
Software triggered in-circuit re-programmability
APPLICATIONS
Optical Networking – Laser Power Control
Base Station Systems
Precision Instrumentation, Smart Sensors
Optical Transceivers – Digital Diagnostic Monitoring
(See general description on page 10)
FUNCTIONAL BLOCK DIAGRAM
ADC0
... ...
... ...
ADC5*
MUX
ADC7*
ADuC7020
ADuC7021
ADuC7022
1MSPS
12-BIT ADC
ADC8**
ADC9**
CMP0
+
CMP1
CMP OUT
-
TEMP
SENSOR
BANDGAP
REF
VREF
POR
OSC
& PLL
PSM
DAC0***
12-BIT DAC
DAC1***
12-BIT DAC
DAC2****
12-BIT DAC
DAC3****
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
PLA
RST
12-BIT DAC
2kX32 SRAM
31kX16 FLASH/EEPROM
4 GEN. PURPOSE TIMERS
SERIAL I/O
UART, SPI, 2xI2C
GPIO
JTAG
* not on the ADuC7020
** ADuC7022 only
*** not on the ADuC7022
**** ADuC7020 only
Figure 1
Rev. PrC
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Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
© 2004 Analog Devices, Inc. All rights reserved.
Fax: 781.326.8703
ADuC7020/ADuC7021/ADuC7022
Preliminary Technical Data
TABLE OF CONTENTS
ADuC7020/21/22—Specifications ................................................. 3
General Description....................................................................... 10
Absolute Maximum Ratings............................................................ 7
Overview of the ARM7TDMI core.......................................... 10
Ordering Guide............................................................................. 7
Memory organisation ................................................................ 11
Pin function descriptions ................................................................ 8
Outline Dimensions ....................................................................... 16
Rev. PrC | Page 2 of 16
Preliminary Technical Data
ADuC7020/ADuC7021/ADuC7022
ADUC7020/21/22—SPECIFICATIONS1
Table 1. (AVDD = IOVDD = 2.7 to 3.6V, VREF = 2.5 V Internal Reference, fCORE = 45MHz, All specifications TA = TMAX to TMIN, unless otherwise noted.)
Parameter
ADC CHANNEL SPECIFICATIONS
DC Accuracy 2, 3
Resolution
Integral Nonlinearity
Integral Nonlinearity 4
Differential Nonlinearity
Differential Nonlinearity 4
DC Code Distribution
CALIBRATED ENDPOINT ERRORS 5
Offset Error
Offset Error Match
Gain Error
Gain Error Match
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR) 6
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk 7
ANALOG INPUT
Input Voltage Ranges
Differential mode
Single-ended mode
Leakage Current
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Accuracy
Reference Temperature Coefficient
Power Supply Rejection Ratio
Output Impedance
Internal VREF Power-On Time
EXTERNAL REFERENCE INPUT9
Input Voltage Range
Input Impedance
DAC CHANNEL SPECIFICATIONS
DC ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Gain Error Mismatch
ADuC7020/21/22
Unit
12
±1.5
±0.5
±2.0
+1/-0.9
±0.5
+1/-0.9
1
Bits
LSB max
LSB typ
LSB max
LSB max
LSB typ
LSB max
LSB typ
±5
±1
±5
±1
LSB max
LSB typ
LSB max
LSB typ
Test Conditions/Comments
fSAMPLE = 1MSPS
2.5V internal reference
2.5V internal reference
1.0V external reference
2.5V internal reference
2.5V internal reference
1.0V external reference
ADC input is a dc voltage
Fin = 10kHz Sine Wave, fSAMPLE = 1MSPS
71
-78
-78
-80
dB typ
dB typ
dB typ
dB typ
VCM8±VREF/2
0 to VREF
±5
20
Volts
Volts
µA max
pF typ
2.5
±10
±10
80
10
1
V
mV max
ppm/°C typ
dB typ
Ω typ
ms typ
0.625
AVDD
TBD
V min
V max
KΩ typ
During ADC Acquisition
0.47µF from VREF (pin 55) to AGND
Measured at TA = 25°C
RL = 5kΩ, CL = 100pF
12
±2
±1
±2
±5
±0.5
TBD
Bits
LSB typ
LSB max
mV max
mV max
% max
% typ
Rev. PrC | Page 3 of 16
Guaranteed Monotonic
DAC output unbuffered
DAC output buffered
% of fullscale on DAC0
ADuC7020/ADuC7021/ADuC7022
Parameter
ANALOG OUTPUTS
Output Voltage Range_0
Ouput Voltage Range_1
Output Voltage Range_2
Output Impedance
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Voltage Output Settling Time
Digital to Analog Glitch Energy
COMPARATOR
Input Offset Voltage
Input Bias Current
Input Voltage Range
Input Capacitance
Hysteresis
Response Time
TEMPERATURE SENSOR
Voltage Output at 25°C
Voltage TC
Accuracy
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection
Power Supply Trip Point Accuracy
Watchdog Timer (WDT)4
Timeout Period
Flash/EE MEMORY
Endurance10
Data Retention11
Digital Inputs
Input Leakage Current
Input Capacitance
Logic Inputs4
VINL, Input Low Voltage
VINH, Input High Voltage
Logic Outputs
VOH, Output High Voltage
VOL, Output Low Voltage
MCU CLOCK RATE
STARTUP TIME
At Power-On
From Idle Mode
From Power-Down Mode
Programmable Logic Array (PLA)
Propagation Delay
Preliminary Technical Data
ADuC7020/21/22
Unit
Test Conditions/Comments
0 to DACREF
0 to 2.5V
0 to DACVDD
V typ
V typ
DACREF range: DACGND to DACVDD
10
Ω typ
10
15
TBD
µs typ
µs typ
nV-sec typ
DAC Output buffered
DAC Output unbuffered
I LSB change at major carry
±10
5
AVDD-1.2
7
5
10
1
10
mV
nA typ
V max
pF typ
mV min
mv max
µs min
µs max
Hysteresis can be turned on or off via the CMPHYST
bit in the CMPCON register
Response time may be modified via the CMPRES bits
in the CMPCON register
TBD
-2.0
±3
mV typ
mV/°C typ
°C typ
2.79
3.07
±2.5
V
V
% max
0
TBD
ms min
ms max
10,000
30
Cycles min
Years min
±10
±1
10
µA max
µA typ
pF typ
0.4
2.0
V max
V min
2.4
0.4
355.5
45.5
V min
V max
kHz min
MHz max
V typ
Two selectable Trip Points
Of the selected nominal Trip Point Voltage
TJ = 55°C
All digital inputs including XTAL1 and XTAL2
All Logic inputs including XTAL1 and XTAL2
ISOURCE = 20µA
ISINK = 1.6mA
8 programmable core clock selections within this
range
Core Clock = TBD MHz
TBD
TBD
TBD
TBD
ns typ
Rev. PrC | Page 4 of 16
From input pin to output pin
Preliminary Technical Data
Parameter
POWER REQUIREMENTS 12, 13
Power Supply Voltage Range
AVDD – AGND and IOVDD - IOGND
ADuC7020/ADuC7021/ADuC7022
ADuC7020/21/22
Unit
2.7
3.6
V min
V max
Power Supply Current Normal Mode
3mA
5
50
60
mA typ
mA max
mA typ
mA max
Power Supply Current Idle Mode
1
mA max
Power Supply Current Power Down
Mode
30
100
µA typ
µA max
1
Test Conditions/Comments
1MHz clock
1MHz clock
45MHz clock
45MHz clock
External Crystal or Internal Osc ON
External Crystal or Internal Osc ON
Temperature Range -40° to +85°C
All ADC Channel Specifications are guaranteed during normal MicroConverter core operation.
3
These specification apply to all ADC input channels.
4
These numbers are not production tested but are supported by design and/or characterization data on production release.
5
Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint and achieve these specifications..
6
SNR calculation includes distortion and noise components.
7
Channel-to-channel crosstalk is measured on adjacent channels.
8
The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
9
When using an external reference input pin, the internal reference must be disabled by setting the lsb in the REFCON Memeory Mapped Register to 0.
10
Endurance is qualified to 50,000 cycles as per JEDEC Std. 22 method A117 and measured at -40°C, +25°C and +85°C. Typical endurance at 25°C is 70,000 cycles.
11
Retention lifetime equivalent at junction temperature (Tj) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime will derate with junction temperature.
12
Power supply current consumption is measured in normal, idle and power-down modes under the following conditions:
Normal Mode:
TBD
Idle Mode:
TBD
Power-Down:
TBD
13
DVDD power supply current increases typically by TBD mA during a Flash/EE memory program or erase cycle.
2
Rev. PrC | Page 5 of 16
ADuC7020/ADuC7021/ADuC7022
Preliminary Technical Data
Terminology
ADC Specifications
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point 1/2
LSB below the first code transition and full scale, a point 1/2
LSB above the last code transition.
Differential Nonlinearity
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitisation process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
Total Harmonic Distortion is the ratio of the rms sum of the
harmonics to the fundamental.
DAC SPECIFICATIONS
This is the deviation of the first code transition (0000 . . . 000) to
(0000 . . . 001) from the ideal, i.e., +1/2 LSB.
Gain Error
This is the deviation of the last code transition from the ideal
AIN voltage (Full Scale – 1.5 LSB) after the offset error has been
adjusted out.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error.
Voltage Output Settling Time
This is the amount of time it takes for the output to settle to
within a 1 LSB level for a full-scale input change..
Rev. PrC | Page 6 of 16
Preliminary Technical Data
ADuC7020/ADuC7021/ADuC7022
ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings (TA = 25°C unless otherwise noted)
Parameter
AVDD to DVDD
AGND to DGND
DVDD to DGND, AVDD to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
VREF to AGND
Analog Inputs to AGND
Operating Temperature Range
Industrial ADuC7020/21/22
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
(ADuC7020/21/22BCP)
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
TBD
TBD
TBD
TBD
TBD
TBD
TBD
–40°C to +85°C
PIN CONFIGURATION
40-Lead CSP
40
31
PIN 1
IDENTIFIER
1
30
TOP VIEW
(Not to Scale)
TBD
TBD
TBD
21
10
11
TBD
TBD
20
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ORDERING GUIDE
Model
ADuC7020BCP
ADuC7021BCP
ADuC7022BCP
EVAL_ADuC7020QS
Temperature Range
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
Package Description
40-Lead Chip Scale Package
40-Lead Chip Scale Package
40-Lead Chip Scale Package
Development System
Contact the factory for chip availability.
ESD Caution
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrC | Page 7 of 16
Package Option
CP-40
CP-40
CP-40
ADuC7020/ADuC7021/ADuC7022
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin# ADuC702X
Mnemonic
Type*
ADC0
ADC1
ADC2/CMP0
ADC3/CMP1
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
I
I
I
I
I
I
I
I
I
I
6
GNDREF
S
6
7
8
9
7
8
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
TMS
TDI
I/O
I/O
I/O
I/O
I
I
10
10
9
BM/P0.0/CMPOUT/P
LAI[7]
I/O
11
11
10
P0.6/T1/MRST/PLA
O[3]
O
12
12
11
TCK/XCLK
I
13
14
15
13
14
15
12
13
14
TDO
IOGND
IOVDD
O
S
S
16
16
15
LVDD
S
17
18
19
17
18
19
16
17
18
DGND
TRST
RST
S
I
I
20
20
19
IRQ0/P0.4/CONVST
ART/PLAO[1]
I/O
21
21
20
IRQ1/P0.5/ADCBUSY
/PLAO[2]
I/O
22
22
21
P2.0/SPM9/PLAO[
5]/CONVSTART
I/O
23
23
22
P0.7/ECLK/SPM8/P
LAO[4]
I/O
7020
38
39
40
1
2
-
7021
37
38
39
40
1
2
3
4
-
7022
36
37
38
39
40
1
2
3
4
5
3
5
4
5
6
7
8
9
Function
Single-ended or differential Analog input 0
Single-ended or differential Analog input 1
Single-ended or differential Analog input 2 / Comparator Positive Input
Single-ended or differential Analog input 3 / Comparator Negative Input
Single-ended or differential Analog input 4
Single-ended or differential Analog input 5
Single-ended or differential Analog input 6
Single-ended or differential Analog input 7
Single-ended or differential Analog input 8
Single-ended or differential Analog input 9
Ground voltage reference for the ADC. For optimal performance the
analog power supply should be separated from IOGND and DGND
DAC0 Voltage Output / Single-ended or differential Analog input 12
DAC1 Voltage Output / Single-ended or differential Analog input 13
DAC2 Voltage Output / Single-ended or differential Analog input 14
DAC3 Voltage Output / Single-ended or differential Analog input 15
JTAG Test Port Input - Test Mode Select. Debug and download access
JTAG Test Port Input – Test Data In. Debug and download access
Multifunction I/O pin:
Boot Mode. The ADuC702X will enter UART serial download mode if BM
is low at reset and will execute code if BM is pulled high at reset through
a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage
Comparator Output/ Programmable Logic Array Input Element 7
Multifunction pin: driven low after reset
General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output
/ Programmable Logic Array Output Element 3
JTAG Test Port Input - Test Clock. Debug and download access / Input to
the internal clock generator circuits
JTAG Test Port Output - Test Data Out. Debug and download access
Ground for GPIO. Typically connected to DGND
3.3V Supply for GPIO and input of the on-chip voltage regulator.
2.5V. Output of the on-chip voltage regulator. Must be connected to a
0.47µF capacitor to DGND
Ground for core logic.
JTAG Test Port Output - Test Reset. Debug and download access
Reset Input. (active low)
Multifunction I/O pin:
External Interrupt Request 0, active high / General Purpose Input-Output
Port 0.4 / Start conversion input signal for ADC / Programmable Logic
Array Output Element 1
Multifunction I/O pin:
External Interrupt Request 1, active high / General Purpose Input-Output
Port 0.5 / ADCBUSY signal / Programmable Logic Array Output Element 2
Serial Port Multiplexed:
General Purpose Input-Output Port 2.0 / UART / Programmable Logic
Array Output Element 5/ Start conversion input signal for ADC
Serial Port Multiplexed:
General Purpose Input-Output Port 0.7 / Output for External Clock signal
Rev. PrC | Page 8 of 16
Preliminary Technical Data
Pin# ADuC702X
Mnemonic
ADuC7020/ADuC7021/ADuC7022
Type*
7020
7021
7022
24
24
23
XCLKO
O
25
24
24
XCLKI
I
26
26
25
P1.7/SPM7/PLAO[
0]
I/O
27
27
26
P1.6/SPM6/PLAI[6]
I/O
28
28
27
P1.5/SPM5/PLAI[5]
I/O
29
29
28
P1.4/SPM4/PLAI[4]
I/O
30
30
29
P1.3/SPM3/PLAI[3]
I/O
31
31
30
P1.2/SPM2/PLAI[2]
I/O
32
32
31
P1.1/SPM1/PLAI[1]
I/O
33
33
32
P1.0/T1/SPM0/PLA
I[0]
I/O
34
-
-
P4.2/PLAO[10]
I/O
35
34
33
VREF
I/O
36
37
35
36
34
35
AGND
AVDD
S
S
Function
/ UART / Programmable Logic Array Output Element 4
Output to the crystal oscillator inverter
Input to the crystal oscillator inverter and input to the internal clock
generator circuits
Serial Port Multiplexed:
General Purpose Input-Output Port 1.7 / UART / SPI / Programmable
Logic Array Output Element 0
Serial Port Multiplexed:
General Purpose Input-Output Port 1.6 / UART / SPI / Programmable
Logic Array Input Element 6
Serial Port Multiplexed:
General Purpose Input-Output Port 1.5 / UART / SPI / Programmable
Logic Array Input Element 5
Serial Port Multiplexed:
General Purpose Input-Output Port 1.4 / UART / SPI / Programmable
Logic Array Input Element 4
Serial Port Multiplexed:
General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable
Logic Array Input Element 3
Serial Port Multiplexed:
General Purpose Input-Output Port 1.2 / UART / I2C1 /Programmable
Logic Array Input Element 2
Serial Port Multiplexed:
General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable
Logic Array Input Element 1
Serial Port Multiplexed:
General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I2C0 /
Programmable Logic Array Input Element 0
General Purpose Input-Output Port 4.2 / Programmable Logic Array
Output Element 10
2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor
when using the internal reference.
Analog Ground. Ground reference point for the analog circuitry
3.3V Analog Power
*
I = Input, O = Output, S = Supply.
- No pin assigned.
Rev. PrC | Page 9 of 16
ADuC7020/ADuC7021/ADuC7022
Preliminary Technical Data
GENERAL DESCRIPTION
The ADuC7020/21/22 are fully integrated, 1MSPS, 12-bit data
acquisition systems incorporating a high performance multichannel ADC, a 16/32-bit MCU and Flash/EE Memory on a
single chip.
The ADC consists of 5/8/10 single-ended inputs. An additional
2/4 inputs are available on the ADuC7021/20 but are
multiplexed with the 2/4 DAC output pins. The ADC can
operate in single-ended or differential input modes with a fully
flexible front end. The ADC input voltage is 0 to VREF. Low drift
bandgap reference, temperature sensor and voltage comparator
complete the ADC peripheral set.
The part also integrates 2/4 buffered voltage output DACs onchip. The DAC output range is 0 to AVDD max.
The device operates from the on-chip oscillator and PLL
generating an internal high-frequency clock of 45 MHz. This
clock is routed through a programmable clock divider from
which the MCU core clock operating frequency is generated.
The microcontroller core is an ARM7TDMI, 16/32-bit RISC
machine, offering up to 45 MIPS peak performance. 62k Bytes
of non-volatile Flash/EE are provided on-chip as well as 8k
Bytes of SRAM. Both the Flash/EE and SRAM memory arrays
are mapped into a single linear array.
compressed into 16-bits, the Thumb instruction set. Faster
execution from 16-bit memory and greater code density can
usually be achieved by using the Thumb instruction set instead
of the ARM instruction set, which makes the ARM7TDMI core
particularly suitable for embedded applications.
However the Thumb mode has two limitations:
- Thumb code usually uses more instructions for the same job,
so ARM code is usually best for maximising the performance
of the time-critical code.
- The Thumb instruction set does not include some
instructions that are needed for exception handling, so ARM
code needs to be used for exception handling.
See ARM7TDMI User Guide for details on the core
architecture, the programming model and both the ARM and
ARM Thumb instruction sets.
Long multiple (M)
The ARM7TDMI instruction set includes four extra
instructions which perform 32-bit by 32-bit multiplication with
64-bit result and 32-bit by 32-bit multiplication-accumulation
(MAC) with 64-bit result.
EmbeddedICE (I)
On-chip factory firmware supports in-circuit serial download
via the UART and JTAG serial interface ports while nonintrusive emulation is also supported via the JTAG interface.
These features are incorporated into a low cost QuickStart
system supporting this MicroConverter family.
EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and
watchpoint registers which allow code to be halted for
debugging purposes. These registers are controlled through the
JTAG test port.
The parts operate from 2.7V to 3.6V and are specified over an
industrial temperature range of -40°C to 85°C. When operating
@45MHz the power dissipation is 300mW. The
ADuC7020/21/22 are available in a 40-lead LFCSP package.
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers may be inspected as well as the Flash/EE, the
SRAM and the Memory Mapped Registers.
OVERVIEW OF THE ARM7TDMI CORE
Exceptions
The ARM7 core is a 32-bit Reduced Instruction Set Computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8, 16 or 32 bits and the length of the
instruction word is 32 bits.
The ARM7TDMI is an ARM7 core with 4 additional features:
- T support for the Thumb (16 bit) instruction set.
- D support for debug
- M support for long multiplies
- I include the EmbeddedICE module to support embedded
system debugging.
ARM supports five types of exceptions, and a privileged
processing mode for each type. The five type of exceptions are:
- Normal interrupt or IRQ. It is provided to service generalpurpose interrupt handling of internal and external events
- Fast interrupt or FIQ. It is provided to service data transfer or
communication channel with low latency. FIQ has priority
over IRQ
- Memory abort
- Attempted execution of an undefined instruction
- Software interrupt (SWI) instruction which can be used to
make a call to an operating system.
Thumb mode (T)
An ARM instruction is 32-bits long. The ARM7TDMI
processor supports a second instruction set that has been
Typically the programmer will define interrupts as IRQ but for
higher priority interrupt, i.e. faster response time, the
programmer can define interrupt as FIQ.
Rev. PrC | Page 10 of 16
Preliminary Technical Data
ADuC7020/ADuC7021/ADuC7022
ARM Registers
ARM7TDMI has a total of 37 registers, of which 31 are general
purpose registers and six are status registers. Each operating
mode has dedicated banked registers.
When writing user-level programs, 15 general purpose 32-bit
registers (r0 to r14), the program counter (r15) and the current
program status register (CPSR) are usable. The remaining
registers are used only for system-level programming and for
exception handling.
When an exception occurs, some of the standard register are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (r13) and the link register (r14) as represented in
Figure22. The fast interrupt mode has more registers (8 to 12)
for fast interrupt processing, so that the interrupt processing
can begin without the need to save or restore these registers and
thus save critical time in the interrupt handling process.
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
CPSR
usable in user mode
system modes only
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_abt
r13_fiq r13_svc r14_abt
r14_svc
r14_fiq
The maximum IRQ latency calculation is similar, but must
allow for the fact that FIQ has higher priority and could delay
entry into the IRQ handling routine for an arbitrary length of
time.
The minimum latency for FIQ or IRQ interrupts is four cycles
in total which consists of the shortest time the request can take
through the synchronizer plus the time to enter the exception
mode.
Note that the ARM7TDMI will always be run in ARM (32-bit)
mode when in privileged modes, i.e. when executing interrupt
service routines.
MEMORY ORGANISATION
The ADuC7020/21/22 incorporate two separate blocks of
memory, 8kByte of SRAM and 64kByte of On-Chip Flash/EE
memory. 62kByte of On-Chip Flash/EE memory are available to
the user, and the remaining 2kBytes are reserved for the factory
configured boot page. These two blocks are mapped as shown
Figure 3.
Note that by default, after a reset, the Flash/EE memory is
mirrored at address 0x00000000. It is possible to remap the
SRAM at address 0x00000000 by clearing bit 0 of the REMAP
MMR. This remap function is described in more details in the
Flash/EE memory chapter.
FFFFFFFFh
MMRs
FFFF0000h
r13_und
r13_irq
r14_und
r14_irq
Reserved
0008FFFFh
Flash/EE
SPSR_fiq
SPSR_svc
SPSR_abt
SPSR_irq
00080000h
SPSR_und
Reserved
00011FFFh
user mode
fiq
mode
svc
mode
abord
mode
SRAM
00010000h
irq undefined
mode
mode
0000FFFFh
Re-mappable Memory Space
(Flash/EE or SRAM)
Figure22: register organisation
00000000h
Figure 3: Physical memory map
Interrupt latency
The worst case latency for an FIQ, assuming that it is enabled,
consists of the longest time the request can take to pass through
the synchronizer, plus the time for the longest instruction to
complete (the longest instruction is an LDM) which loads all
the registers including the PC, plus the time for the data abort
entry, plus the time for FIQ entry. At the end of this time, the
ARM7TDMI will be executing the instruction at 0x1C (FIQ
interrupt vector address). The maximum total time is 44
processor cycles, which is just over 975 nanoseconds in a system
using a continuous 45 MHz processor clock.
Memory Access
The ARM7 core sees memory as a linear array of 232 byte
location where the different blocks of memory are mapped as
outlined in Figure 3 above.
The ADuC7020/21/22 memory organisation is configured in
little endian format: the least significant byte is located in the
lowest byte address and the most significant byte in the highest
byte address.
Rev. PrC | Page 11 of 16
ADuC7020/ADuC7021/ADuC7022
bit31
Byte3
9
5
1
...
A
6
2
bit0
Byte0
...
...
...
B
7
3
Byte2 Byte1
Preliminary Technical Data
8
4
0
0xFFFFFFFF
0xFFFFF820
0xFFFFFFFFh
0xFFFFF800
0x00000004h
0x00000000h
Flash Control
Interface
0xFFFFF46C
GPIO
0xFFFFF400
0xFFFF0B54
32 bits
PLA
Figure 4: little endian format
0xFFFF0B00
0xFFFF0A14
Flash/EE Memory
SPI
The total 64kBytes of Flash/EE are organised as 32k X 16 bits.
31k X 16 bits are user space and 1k X 16 bits is reserved for boot
loader. The page size of this Flash/EE memory is 256Bytes.
62kBytes of Flash/EE are available to the user as code and nonvolatile data memory. There is no distinction between data and
program as ARM code shares the same space. The real width of
the Flash/EE memory is 16 bits, which means that in ARM
mode (32-bit instruction), two accesses to the Flash/EE are
necessary for each instruction fetch. It is therefore
recommended to use Thumb mode when executing from
Flash/EE memory for optimum access speed. The maximum
access speed for the Flash/EE memory is 45MHz in Thumb
mode and 22.5MHz in full ARM mode. More details on
Flash/EE access time are outlined later in ‘Execution from
SRAM and Flash/EE’ section of this datasheet.
0xFFFF0A00
0xFFFF0948
I2C1
0xFFFF0900
0xFFFF0848
I2C0
0xFFFF0800
0xFFFF0730
UART
0xFFFF0700
0xFFFF0620
DAC
0xFFFF0600
0xFFFF0538
ADC
0xFFFF0500
0xFFFF0490
0xFFFF048C
Bandgap
Reference
SRAM
0xFFFF0448
8kBytes of SRAM are available to the user, organized as 2k X 32
bits, i.e. 2kWords. ARM code can run directly from SRAM at
45MHz , given that the SRAM array is configured as a 32-bit
wide memory array. More details on SRAM access time are
outlined later in ‘Execution from SRAM and Flash/EE’ section
of this datasheet.
0xFFFF0440
0xFFFF0420
0xFFFF0404
0xFFFF0370
0xFFFF0360
Memory Mapped Registers
0xFFFF0350
The Memory Mapped Register (MMR) space is mapped into
the upper 2 pages of the Flash/EE space and accessed by
indirect addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the core registers
reside in the MMR area. All shaded locations shown in Figure 6
are unoccupied or reserved locations and should not be
accessed by user software. Table 4 shows a full MMR memory
map. The ‘Access’ column corresponds to the access time
reading or writing a MMR. Table 4 shows a full MMR memory
map.
0xFFFF0340
0xFFFF0334
0xFFFF0320
Power Supply
Monitor
PLL &
Oscillator Control
Watchdog
Timer
Wake Up
Timer
General Purpose
Timer
0xFFFF0310
Timer 0
0xFFFF0300
0xFFFF0238
0xFFFF0220
0xFFFF0110
0xFFFF0000
Remap &
System Control
Interrupt
Controller
Figure 5: Memory Mapped
Rev. PrC | Page 12 of 16
Preliminary Technical Data
ADuC7020/ADuC7021/ADuC7022
Table 4. Complete MMRs list
Address
Name
Byte
Access
Type
Page
Address
Name
Byte
Cycle
IRQ address base = 0xFFFF0000
Access
Page
Type
Cycle
0x0414
PLLCON
1
RW
2
PLLKY2
1
W
2
0x0000
IRQSTA
4
R
1
0x0418
0x0004
IRQSIG
4
R
1
PSM address base = 0xFFFF0440
0x0008
IRQEN
4
RW
1
0x0440
PSMCON
2
RW
2
0x000C
IRQCLR
4
W
1
0x0444
CMPCON
2
RW
2
0x0010
SWICFG
4
W
1
Reference address base = 0xFFFF0480
0x0100
FIQSTA
4
R
1
0x048C
0x0104
FIQSIG
4
R
1
ADC address base = 0xFFFF0500
0x0108
FIQEN
4
RW
1
0x0500
ADCCON
0x010C
FIQCLR
4
W
1
0x0504
System Control address base = 0xFFFF0200
0x0220
REMAP
1
RW
0x0230
RSTSTA
1
0x0234
RSTCLR
1
RW
2
1
RW
2
ADCCP
1
RW
2
0x0508
ADCCN
1
RW
2
1
0x050C
ADCSTA
1
RW
2
R
1
0x0510
ADCDAT
4
R
2
W
1
0x0514
ADCRST
1
RW
2
0x0530
ADCGN
2
RW
2
ADCOF
2
RW
2
Timer address base = 0xFFFF0300
REFCON
1
0x0300
T0LD
2
RW
2
0x0534
0x0304
T0VAL
2
R
2
DAC address base = 0xFFFF0600
0x0308
T0CON
2
RW
2
0x0600
DAC0CON
1
RW
2
0x030C
T0CLRI
1
W
2
0x0604
DAC0DAT
4
RW
2
0x0320
T1LD
4
RW
2
0x0608
DAC1CON
1
RW
2
0x0324
T1VAL
4
R
2
0x060C
DAC1DAT
4
RW
2
0x0328
T1CON
2
RW
2
0x0610
DAC2CON
1
RW
2
0x032C
T1CLRI
1
W
2
0x0614
DAC2DAT
4
RW
2
0x0330
T1CAP
4
RW
2
0x0618
DAC3CON
1
RW
2
0x0340
T2LD
4
RW
2
0x061C
DAC3DAT
4
RW
2
0x0344
T2VAL
4
R
2
UART base address = 0xFFFF0700
0x0348
T2CON
2
RW
2
0x0700
0x034C
T2CLRI
1
W
0x0360
T3LD
2
0x0364
T3VAL
0x0368
0x036C
COMTX
1
RW
2
2
COMRX
1
R
2
RW
2
COMDIV0
1
RW
2
2
R
2
COMIEN0
1
RW
2
T3CON
2
RW
2
COMDIV1
1
R/W
2
T3CLRI
1
W
2
0x0708
COMIID0
1
R
2
0x070C
COMCON0
1
RW
2
PLL base address = 0xFFFF0400
0x0704
0x0404
POWKY1
1
W
2
0x0710
COMCON1
1
RW
2
0x0408
POWCON
1
RW
2
0x0714
COMSTA0
1
R
2
0x040C
POWKY2
1
W
2
0x0718
COMSTA1
1
R
2
0x0410
PLLKY1
1
W
2
0x071C
COMSCR
1
RW
2
Rev. PrC | Page 13 of 16
ADuC7020/ADuC7021/ADuC7022
Address
Name
Byte
Access
Preliminary Technical Data
Page
Type
Cycle
Address
Name
1
Access
Page
Type
Cycle
RW
2
0x0720
COMIEN1
1
RW
2
0x0944
0x0724
COMIID1
1
R
2
SPI base address = 0xFFFF0A00
0x0728
COMADR
1
RW
2
0x0A00
SPISTA
1
R
2
0X072C
COMDIV2
2
RW
2
0x0A04
SPIRX
1
R
2
0x0A08
SPITX
1
W
2
I2C0 base address = 0xFFFF0800
I2C1ID3
Byte
0x0800
I2C0MSTA
1
R
2
0x0A0C
SPIDIV
1
RW
2
0x0804
I2C0SSTA
1
R
2
0x0A10
SPICON
2
RW
2
0x0808
I2C0SRX
1
R
2
PLA base address = 0xFFFF0B00
0x080C
I2C0STX
1
W
2
0x0B00
PLAELM0
2
RW
2
0x0810
I2C0MRX
1
R
2
0x0B04
PLAELM1
2
RW
2
0x0814
I2C0MTX
1
W
2
0x0B08
PLAELM2
2
RW
2
0x0818
I2C0CNT
1
RW
2
0x0B0C
PLAELM3
2
RW
2
0x081C
I2C0ADR
1
RW
2
0x0B10
PLAELM4
2
RW
2
0x0824
I2C0BYTE
1
RW
2
0x0B14
PLAELM5
2
RW
2
0x0828
I2C0ALT
1
RW
2
0x0B18
PLAELM6
2
RW
2
0x082C
I2C0CFG
1
RW
2
0x0B1C
PLAELM7
2
RW
2
0x0830
I2C0DIVH
1
RW
2
0x0B20
PLAELM8
2
RW
2
0x0834
I2C0DIVL
1
RW
2
0x0B24
PLAELM9
2
RW
2
0x0838
I2C0ID0
1
RW
2
0x0B28
PLAELM10
2
RW
2
0x083C
I2C0ID1
1
RW
2
0x0B2C
PLAELM11
2
RW
2
0x0840
I2C0ID2
1
RW
2
0x0B30
PLAELM12
2
RW
2
0x0844
I2C0ID3
1
RW
2
0x0B34
PLAELM13
2
RW
2
0x0B38
PLAELM14
2
RW
2
I2C1 base address = 0xFFFF0900
0x0900
I2C1MSTA
1
R
2
0x0B3C
PLAELM15
2
RW
2
0x0904
I2C1SSTA
1
R
2
0x0B40
PLACLK
1
RW
2
0x0908
I2C1SRX
1
R
2
0x0B44
PLAIRQ
4
RW
2
0x090C
I2C1STX
1
W
2
0x0B48
PLAADC
4
RW
2
0x0910
I2C1MRX
1
R
2
0x0B4C
PLADIN
4
R
2
0x0914
I2C1MTX
1
W
2
0x0B50
PLADOUT
4
RW
2
0x0918
I2C1CNT
1
RW
2
GPIO base address = 0xFFFFF400
0x091C
I2C1ADR
1
RW
2
0xF400
GP0CON
4
RW
1
0x0924
I2C1BYTE
1
RW
2
0xF404
GP1CON
4
RW
1
0x0928
I2C1ALT
1
RW
2
0xF408
GP2CON
4
RW
1
0x092C
I2C1CFG
1
RW
2
0xF40C
GP3CON
4
RW
1
0x0930
I2C1DIVH
1
RW
2
0xF410
GP4CON
4
RW
1
0x0934
I2C1DIVL
1
RW
2
0xF420
GP0DAT
4
RW
1
0x0938
I2C1ID0
1
RW
2
0xF424
GP0SET
1
W
1
0x093C
I2C1ID1
1
RW
2
0xF428
GP0CLR
1
W
1
0x0940
I2C1ID2
1
RW
2
0xF430
GP1DAT
4
RW
1
Rev. PrC | Page 14 of 16
Preliminary Technical Data
Address
Name
Byte
Access
ADuC7020/ADuC7021/ADuC7022
Page
Type
Cycle
0xF434
GP1SET
1
W
1
0xF438
GP1CLR
1
W
1
0xF440
GP2DAT
4
RW
1
0xF444
GP2SET
1
W
1
0xF448
GP2CLR
1
W
1
0xF450
GP3DAT
4
RW
1
0xF454
GP3SET
1
W
1
0xF458
GP3CLR
1
W
1
0xF460
GP4DAT
4
RW
1
0xF464
GP4SET
1
W
1
0xF468
GP4CLR
1
W
1
An entry level, low cost development system is available for the
ADuC702X family. This system consists of the following PCbased (Windows® compatible) hardware and software
development tools:
Hardware:
- ADuC702X Evaluation board
- Serial Port programming cable
- JTAG emulator
Software:
- Integrated Development Environment, incorporating
assembler, compiler and non intrusive JTAG-based
debugger
- Serial Downloader software
- Example Code
Miscellaneous:
CD-ROM Documentation
Flash/EE base address = 0xFFFFF800
0xF800
FEESTA
1
R
1
0xF804
FEEMOD
1
RW
1
0xF808
FEECON
1
RW
1
0xF80C
FEEDAT
2
RW
1
0xF810
FEEADR
2
RW
1
0xF818
FEESIGN
3
R
1
0xF81C
FEEPRO
4
RW
1
Development Tools
In-Circuit Serial Downloader
The Serial Downloader is a Windows application that allows
the user to serially download an assembled program (Intel Hex
format file) to the on-chip program FLASH/EE memory via the
serial port on a standard PC.
The ‘Access’ column corresponds to the access time reading or
writing a MMR. It depends on the AMBA (Advanced
Microcontroller Bus Architecture) bus used to access the
peripheral. The processor has two AMBA busses, AHB
(Advanced High-performance Bus) used for system modules
and APB (Advanced Peripheral Bus) used for lower
performance peripheral.
Rev. PrC | Page 15 of 16
ADuC7020/ADuC7021/ADuC7022
Preliminary Technical Data
OUTLINE DIMENSIONS
6.00
BSC SQ
PIN 1
INDICATOR
31
30
PIN 1
INDICATOR
0.50
BSC
5.75
BSC SQ
TOP
VIEW
0.50
0.40
0.30
12 8MAX
1.00
0.90
0.80
40
1
4.25
3.70 SQ
1.75
BOTTOM
VIEW
10
11
21
20
4.50
REF
1.00 MAX
0.65 NOM
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 6. 40-Lead Frame Chip Scale Package [LFCSP] (CP-40)—Dimensions shown in millimetres
Rev. PrC | Page 16 of 16
PR04772-0-3/04(PrC)
0.60 MAX
0.60 MAX