Stratus™ High-Level Synthesis
Making the IP you design more valuable
Qiang Zhu
CDNLive Shanghai
August 2015
High-level synthesis (HLS) usage today
• 15 of top 20 semiconductor companies
• 10M-30M gate HLS projects
• 10X productivity improvement
• 5X faster and better verification
“With our high-level synthesis flow and
the Stratus platform, we're now doing the
kinds of things that we couldn't have
imagined doing previously.”
“Having an early working prototype is
having a significant business impact in
terms of our potential customers'
enthusiasm and confidence."
- Ray McConnell, chief technology officer
of Blu Wireless Technology
• 20% better QoR for power, performance, and area
• Behavioral IP is more flexible, more valuable
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© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
Stratus high-level synthesis momentum
Millions of Dollars
ESL Market Segment Growth
70
60
50
40
30
20
10
0
Imaging
Sensor
Camera
Compression
Video
2012 2013 2014 2015 2016 2017 2018
ESL Market Segment Share
18%
26%
50%
Cadence
Synopsys
Calypto
Bluespec
6%
Source: Gary Smith EDA, November 2014
3
Controllers
Microcontroller
Printers
Blu-ray / DVD
Flash
Cache coherency
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
HEVC
H.265
H.264
Comms
LTE
MIMO
WiFi
Bluetooth
WiGig
100G
PHY, Switch
Image processing
Communications
Video processing
Controllers
Graphics processing
Security devices
Pachinko machine
Digital TV
Error correction
Automotive
Audio processing
What is high-level synthesis?
Constraints
Stratus™ HLS
DataPath
FSM
Detail
Technology Library
Abstraction
SystemC, C, C++
Synthesizable Behavioral Models
HLS takes
abstract descriptions
MUL
ADD
DIV
FPU
RTL - Verilog
4
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and adds detail
to produce RTL
Introducing Stratus high-level synthesis (HLS)
• 10x productivity and IP reuse
– Separates functionality from implementation
– Re-targetable high-level IP
• 5x faster, better verification
– Fast TLM simulation models
– Consistent verification platform
• 20% better Quality of Results
– Power/Area/Performance
– Beat hand-coded RTL results
• Broad applicability
Incisive® and JasperGold®
Verification Platform
# Laptop
define clk_p 800
set precision 32
set r_bits 11
set g_bits 11
set b_bits 10
void
MPEG4::sync_signal()
{
if (rst) {
out.write(0);
} else {
int tmp = in1 & in2;
out.write( in3 ? tmp : ~tmp);
}
}
C++/SysC
Constraint File
Stratus™ HLS
// RTL
module foo ( …)
….
……
RTL
Encounter® Digital
Implementation System
– Can be utilized across an entire system-on-chip (SoC) design
– Addresses real-world challenges of ECO, low power, routing congestion,
and IP reuse
5
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
What provides the productivity benefit?
A higher level of abstraction
• 5x TAT improvement
on the first generation of design
Functionality
• 10x + TAT improvement
on derivative designs
Architecture
User
Manages
Constraints
"We don't want our engineers writing
Verilog, we want them inventing
concepts and transferring them into
silicon and software using automated
processes.”
Yoshihito Kondo – GM, Sony Corporation
in EDA Graffiti, July 2009
Schedule of operations
FSM encoding
Timing
Pipeline registers
Area reduction
ECO
Clock gating
Consistent RTL style
Sharing datapath components
6
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
Stratus™ HLS
Automatically
Manages
Abstraction improves Verification
• Transaction level (TLM)
Reuse Testbench At All Levels
TLM Testbench
TLM interface
• Protocol accurate
TLM Testbench
PIN interface
Protocol
Accurate
Verification
TLM Design
TLM interface
TLM Design
PIN interface
Stratus™ HLS
• RTL
− Integration with RTL simulators
− Reuse testbench
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© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
TLM Testbench
PIN interface
RTL
Validation
RTL
Verify
I/O and Timing
− Pin-accurate interfaces
− Reuse testbench
High-speed
Functional
Verification
Verify
Functionality
− High-speed simulation
− Reduces coding effort
− 5-10x more effective verification
Abstraction improves Quality of Results
• Create multiple implementations from one
behavioral IP description
− Remove guesswork in picking “best” architecture
− “Best” architecture varies for different applications
− Explore to find optimal tradeoffs
• Micro-architecture exploration
−
−
−
−
void
MPEG4::sync_signal()
{
if (rst) {
out.write(0);
} else {
int tmp = in1 & in2;
out.write( in3 ? tmp : ~tmp);
}
}
C++/SysC
# Cell phone
define clk_p 27
set precision 8
set r_bits 3
set g_bits 3
set b_bits 2
# Theatre
define clk_p 3200
set precision 96
set r_bits 32
set g_bits 32
set b_bits 32
Directive Files
Stratus HLS
Automated by Stratus™ HLS
Ex: Sharing vs. parallelism in the datapath
Ex: Changing perf. constraints or pipeline depth
Ex: Array storage as memory vs. reg. file vs. flops
• Macro-architecture exploration
− Assisted by Stratus HLS
− Ex: Changing I/O interfaces
− Ex: Functional and algorithmic changes
8
# Laptop
define clk_p 800
set precision 32
set r_bits 11
set g_bits 11
set b_bits 10
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are trademarks of Cadence
©Design
2015 Cadence
All rights
reserved
worldwide..
Systems,Design
Inc. In Systems,
the UnitedInc.
States
and other
countries.
All other trademarks are the property of their respective owners and
are not affiliated with Cadence
Abstraction improves Reuse
• One IP model  different
architectures and/or interfaces
− C++ is golden source code
− Directive files drive implementation for
each application
void
MPEG4::sync_signal()
{
if (rst) {
out.write(0);
} else {
int tmp = in1 & in2;
out.write( in3 ? tmp : ~tmp);
}
}
C++/SysC
# Cell phone
define clk_p 27
set precision 8
set r_bits 3
set g_bits 3
set b_bits 2
# Theatre
define clk_p 3200
set precision 96
set r_bits 32
set g_bits 32
set b_bits 32
Directive Files
Stratus HLS
• Behavioral IP is easy to change
− “Minor” algorithmic changes would
require complete RTL rewrite
− With Stratus™ HLS, reuse most of
design and verification environment
• Extends useful life of your IP
9
# Laptop
define clk_p 800
set precision 32
set r_bits 11
set g_bits 11
set b_bits 10
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are trademarks of Cadence
©Design
2015 Cadence
All rights
reserved
worldwide..
Systems,Design
Inc. In Systems,
the UnitedInc.
States
and other
countries.
All other trademarks are the property of their respective owners and
are not affiliated with Cadence
Making the IP you design more valuable
Improved Verification
+
Improved QoR
+
Improved Reuse
Improved value of
your IP
Stratus™ HLS improves the ROI
on your IP development
10
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
Case study: HEVC / H.265
HLS helps Renesas to be first to market
• Challenges:
– Develop H.265-compliant IP with proprietary new algorithm in time to
lead the market
– Support multiple PPA and I/O requirements of mobile, consumer,
vehicle information systems, industrial equipment
• Results:
– 70% reduction in design and verification time
– 6x faster verification
– Utilized HLS ECO Flow to overcome late functional change
"Deploying the system-level design approach … for the entire design
addressed this challenge, and we were able to implement the new algorithm
very efficiently, achieving a good time-to-market for our advanced new IP.”
Toyokazu Hori – Department Manager, Renesas Electronics Corporation
11
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are trademarks of Cadence
©Design
2015 Cadence
All rights
reserved
worldwide..
Systems,Design
Inc. in Systems,
the UnitedInc.
States
and other
countries.
All other trademarks are the property of their respective owners and
are not affiliated with Cadence
Stratus HLS details
12
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
Example sub-system
Accelerator subsystem for high speed printer
Testbench
ARM
Core
Source
Memory
Sink
Master
Slave
Master
AXI 4
M/S
Slave
M/S
M/S
Slave
M/S
DMA1
IMG Accelerator
DMA2
DMA3
FP Accelerator
DMA4
Design
13
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
Example sub-system
Design and verify algorithms, interfaces, synchronization
AXI 4
IP Blocks
Design Blocks
Synchronization
Channel
Configuration
Register
AXI Slave Interface
Decoder and Registers
CDC
Error Diffusion
32-bit
Unpack
Filter
Line Buffer
24-bit pixels
5x5
Zoom
Line Buffer
24-bit pixels
2x2
IMG Accelerator
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pix-24
pix-3
Dual Port
Adapter
Feedback
RAM
Pack
32-bit
Cadence synthesizable IP
Pre-verified building blocks accelerate design and verification
Interface IP
Memory IP generator
Floating Point IP
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Category
Available IP Blocks
Data types
Fixed point
Complex
Floating point
Building blocks
Computational math
FIFOs
Line buffers
CDCs
Memories
Generic
communication
Point-to-point channels
with put()/get() APIs
Configurable
bus interfaces
Simple bus
AXI3
AXI4-Lite, AXI4
Custom interfaces
Can be created by users
Design services available
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
Top-down ECO via incremental HLS
Minimize impact of late stage changes
• Input:
− SystemC with ECO change
− Previously verified results
ECO
Stratus™ HLS
DB
Stratus™ HLS
• Incremental HLS:
− Adds similarity as a cost metric
RTL
• Output:
RTL
− RTL with minimal changes
RTL Compiler
• Encounter® Conformal®
ECO Designer
Netlist
− RTL Functional ECO
− Translates RTL changes to the netlist
− Pre/post-mask physical ECO
EDI System
− Implements the changes on the physical
design
DEF
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© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
P&R
Netlist
Encounter®
Conformal
ECO Designer
Stratus high-level synthesis
More that just a point tool…
• Integrated design environment
− SystemC, C, C++ design entry
− Complete graphical analysis
with links to source code
− Flow automation
• Stratus synthesizable IP
− Pre-verified building blocks
− Interfaces, floating point
• Knowledge base and training
− Articles and examples
− Tool and flow training
17
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide..
Summary: Why use Stratus high-level synthesis?
SystemC  RTL in 10 days
vs. manual RTL in 3 months
I/F controller IP
FPGA retargeting in
1-2 days vs. 2-3 weeks (manual)
Motion-detection IP
5x faster, better verification
(mW)
10x+ productivity increase
20% better quality of results
18
More valuable, more reusable IP
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are trademarks of Cadence
©Design
2015 Cadence
All rights
reserved
worldwide..
Systems,Design
Inc. In Systems,
the UnitedInc.
States
and other
countries.
All other trademarks are the property of their respective owners and
are not affiliated with Cadence
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and Stratus is a trademark of Cadence
Design Systems, Inc. in the United States and other countries. ARM is a registered trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All other
trademarks are the property of their respective owners.