Faculty of Engineering and Architectural Science
Department of Electrical and Computer Engineering
Course Outline
ELE504: Electronics Circuits II
Prerequisites
ELE 404
Course Web Page http://www.ee.ryerson.ca/~courses/ele504/
Compulsory
Texts:
Reference
Text:
“Microelectronic Circuits”, Sedra and Smith, 6th edition, Oxford University Press, 2010.
Calendar
Description
Advanced course on the analysis and design of electronic circuits. Topics include non-ideal
Op-Amp amplifier characteristics, practical amplifier designs, linear/non-linear Op-Amp
circuits, filters and tuned amplifiers, oscillators, signal generators, power output stages, etc.
Circuit applications to such areas as instrumentation, signal processing and conditioning,
and control are considered. Key design concepts are experienced through laboratory work
and a major design project, use of electronic circuit simulation tools, and solving design
problems. Lect: 3 hrs./Lab: 2 hrs.
Learning
Objectives
“Operational Amplifiers with Linear Integrated Circuits”, Stanley, Prentice-Hall., 2002.
At the end of this course, the successful student will be able to:
1. Analyze, design and implement use of Op-Amp based linear/non-linear electronic
circuits to solve engineering problems. Understand, and effectively use, engineering
principles and theories to formulate design problems (issues) based on the required
specifications/functionalities. (4a) and (4b)
Assessment Methods: Midterm and Final Exam Design Problems and Questions;
and successful completion and meeting Lab and major project design milestones.
Assessment Measures: Specific Midterm/Final Exam Problems; and through
Design analysis on Labs and the Major Project (MP) per established Pre-lab
milestones.
2. Use analysis, modeling and design simulation/development tools to seek, and decide
on, optimal design solution(s). (4f) and (4g)
Assessment Methods: Successful completion and verification of the overall design
through effective use of analysis, simulation and development tools for the
established milestone deliverables.
Assessment Measures: Directly assessed through scores obtained for effective use
of analysis, design simulation and development tools in various individual assessed
Pre-Lab requirements of the Major Project (MP), and various Labs.
1
3. Use of engineering tool (MultiSim Electronics Circuit Simulator) to allow
verification of design/problem analysis through use of real devices’ simulation
models. (5c)
Assessment Methods: Successful completion and verification of the Pre-Lab
assigned design/problem analysis using the MultiSim Simulation tool.
Assessment Measures: Directly assessed through scores obtained for successful
completion and effective use of Simulation tool based on individually assigned PreLab design/problems in the Major Project (MP), and various Labs.
4. Demonstrate the main design features of the Major-Project and answer critical and
project specific questions during project demo and oral sessions. Write a formal
technical report (following the prescribed template and guidelines) reflecting the
design process used for the Major Project (MP), where all the reports are evaluated
based on their completeness, technical content and proper use of the English
language. (7a)
Assessment Methods: Demonstration of the Major Project (MP), and assess
answers to critical and design specific questions; and through Formal technical
report of the Major Project.
Assessment Measures: Evaluation of the Individual component of the Major Project
(MP) through demonstration and oral questions; and formal technical report.
Course project summary and interim report grading.
Note: Numbers in parentheses refer to the graduate attributes required by the Canadian Engineering Accreditation Board.
For more information, see: http://www.feas.ryerson.ca/quality_assurance/accreditation.pdf
Course
Organization
3 hours of lecture per week for 13 weeks.
2 hours of lab per week for 12 weeks.
1 Teaching Assistant (TA) per 24 students.
Course
Evaluation
Midterm exam
Major Project (MP)
Labs [L1-A (3%), L1-B (4%), L2 (5%) & L3 (3%)]
Final exam
Total



25%
15%
15%
45%
100%
Midterm Exam:- A single midterm exam will be held. No make-ups will be held for a missed
midterm exam.
Major Project & Individual Labs:- The Pre-Lab assignments will be graded for each student,
whereas the in-lab work and lab reports (short-form and formal) are graded for each lab-group’s
contribution. Details on the grading scheme and deliverables are provided in each Lab/MP
descriptions available on the ELE504 course website.
To achieve a passing grade, student must pass both the Theory (Midterm & Final Exams) and
Laboratory/project (Labs and MP) components.

2
Examinations
Midterm exam is normally in Week 7 (TBA), 2.0 hours, closed book (covers Weeks 1-6 of
course material).
Final exam scheduled during December exam-period, 3 hours, closed book (covers Weeks
1-13 of course material).
Course Content
Topic Description
Operational Amplifiers
Ideal Op-Amp & Applications – Review
Difference Amplifiers
Non-Ideal Op-amp: DC imperfections
 Finite open-loop gains and bandwidths
 Large signal operations
Integrators and Differentiators
Practical Applications
Approx.
Hours
8
Text - sections
2.1,2.2,2.3
2.4
2.6
2.7
2.8
2.5
10
Waveform Shaping Circuits
17.4
17.5
4.5
17.9
17.6, 17.7
Bistable Multivibrators
Square and Triangular waveform generations
Basic Rectifier & Superdiode
Precision Rectifier Circuits
Pulse Generation & Integrated-Circuit Timers
Practical Applications
2
8
Midterm Exam
Signal Generators
Oscillation principles
Op-amp – RC Oscillators
LC and Crystal Oscillators
Practical applications
TBA
17.1
17.2
17.3
7
Active Filters
Filter Concepts
Butterworth filters
Chebyshev filters
Second order filters (Sallen Key)
Sensitivity analysis
16.1, 16.2
16.3, notes.
16.3, notes.
16.4,16.5
16.9
Output Stages of Power Amplifiers
Class A
Class B
Class AB
4
11.1
11.3
11.4, notes.
3
Course Content
Analysis
Major Design
Project & Labs
Mathematics & Basic
Science
5%
Engineering Science
Engineering Design
40%
55%
Refer to the detailed project description & deliverables of the Major Design Project and
each Lab, available on the ELE504 course website.
Labs & Major Project - Schedule
Week
Week of:-
Project
Activities
No Lab – Purchase Kit on Friday 5th, 2014 in Room ENG310
Select OpAmp Circuits (Review) - submission of Short-Form report
on next scheduled lab period.
Non-ideal OpAmp Characteristics & Design – analysis & expt.
Design implementation, testing and demo + submission of ShortForm report on next scheduled lab period.
VCFG Design: Analysis & Simulations
1
2
Sep. 2nd - 5th
Sep. 8th -12th
--L1A
3
4
Sep. 15th -19th
Sep. 22nd- 26th
L1B
L1B
5
Sep. 29thOct.3rd
Oct. 6th -10th
Oct. 14th -20th
Oct. 21st -27th
Oct.28th Nov.3rd
Nov. 4th - 10th
Nov. 11th 17th
Nov. 18th 24th
Nov.25th–
Dec.1st
MP
6
7
8
9
10
11
12
13
MP
MP
MP
MP
L2
L2
L2
L3
Design analysis, implementation & testing [Milestone #1]
Design implementation & testing [Milestone #2]
Design implementation, testing & demonstration [Milestone #2/3]
Final design demonstration; + Formal report due on next scheduled
lab period [Milestone #3/4]
Oscillators & 555 Timer designs. - PreLab (i) & (iii) due.
PreLab (ii) due. Final design demonstration of parts (A) and (C).
Design demo of part (B) + submission of Short-Form report on next
scheduled lab period.
Butterworth & Chebyshev LP Filter Design:Design demonstration + submission of deliverables by end of week.
The Pre-lab will include design and simulations of Butterworth and Chebyshev filters but
only the Butterworth filter is required to be implemented and tested in the Lab. The shortform lab report is due no later than Monday, December 1st. The Monday lab sections on
Dec 1st can hand in the lab report by the end of the following day.
Notes:1) Failure to submit and/or demonstrate the above deliverables as scheduled will result in an automatic zero mark for each of the missed milestone. No exceptions. 2) Each student must complete the analysis/evaluation of his/her project design work (Pre‐Lab) for each lab, prior to carrying out each project in the lab. 3) Laboratory materials and Supplementary Lecture Notes are posted on the Blackboard. 4) It is the student's responsibility to have all required circuit components ready prior to the start of each lab. 5) Lab kit will be sold on Friday, Sept. 5th, 2014 from 10:30am – 4:30pm, in Room ENG 310. 4
6) If there are kits left over, they will be available for purchase in room ENG418 from 12:15PM to 1PM, until September 30th. 7) If you wish to purchase the lab components elsewhere, a list of components in the lab kit is posted in the “Labs” folder of the BlackBoard. 8) If there is any change on the laboratory activities, lecture materials, or counseling hours, announcement will be made on BlackBoard. Important Notes
1.
All of the required course-specific written reports will be assessed not only on their technical/academic merit, but also on
the communication skills exhibited through these reports.
2. All assignment and lab/tutorial reports must have the standard cover page which can be completed and printed from the
Department website at www.ee.ryerson.ca. The cover page must be signed by the student(s) prior to submission of the
work. Submissions without the cover pages will not be accepted.
3. Students who miss a final exam for a verifiable reason and who cannot be given a make-up exam prior to the submission
of final course grades, must be given a grade of INC (as outlined in the Grading Promotion and Academic Standing
Policy) and a make-up exam (normally within 2 weeks of the beginning of the next semester) that carries the same
weight and measures the same knowledge, must be scheduled.
4. Medical or Compassionate documents for the missing of an exam must be submitted within 3 working days of the exam.
Students are responsible for notifying the instructor that they will be missing an exam as soon as possible.
5. Requests for accommodation of specific religious or spiritual observance must be presented to the instructor no later
than two weeks prior to the conflict in question (in the case of final examinations within two weeks of the release of the
examination schedule). In extenuating circumstances this deadline may be extended. If the dates are not known well in
advance because they are linked to other conditions, requests should be submitted as soon as possible in advance of the
required observance. Given that timely requests will prevent difficulties with arranging constructive accommodations,
students are strongly encouraged to notify the instructor of an observance accommodation issue within the first two
weeks of classes.
6. The results of the first test or mid-term exam will be returned to students before the deadline to drop an undergraduate
course in good Academic Standing.
7. Students are required to adhere to all relevant University policies including:
Undergraduate Grading, Promotion and Academic Standing, http://www.ryerson.ca/senate/policies/pol46.pdf
Student Code of Academic Conduct, http://www.ryerson.ca/senate/policies/pol60.pdf
Student Code of Non-Academic Conduct, http://www.ryerson.ca/senate/policies/pol61.pdf
Undergraduate Academic Consideration and Appeals, http://www.ryerson.ca/senate/policies/pol134.pdf
Examination Policy, http://www.ryerson.ca/senate/policies/pol135.pdf
Accom. of Student Relig., Abor. and Spir. Observance, http://www.ryerson.ca/senate/policies/pol150.pdf
Est. of Stud. Email Accts for Official Univ. Commun., http://www.ryerson.ca/senate/policies/pol157.pdf
8. Students are required to obtain and maintain a Ryerson Matrix e-mail account for timely communications between the
instructor and the students.
9. Any changes in the course outline, test dates, marking or evaluation will be discussed in class prior to being
implemented.
10. In-class use of cellular telephones is not permitted. Please turn off your cell phone prior to class. Quiet use of laptops,
text-messengers and similar non-audible devices are permitted only in the rear rows of the class. This restriction allows
use of such devices by their users while limiting audible and visual distractions to other students. This policy may
change without notice.
11. Labs, projects handed in past the due date and time will not be accepted for marking and will receive a mark of ZERO.
In some genuine cases late submission will be allowed with a penalty of 5% per day.
12. Students found to have plagiarized any portion of their labs and final project will receive a grade of zero.
Instructor _______________________________ Date ______________________________ Approved by _______________________________ Date ________________________________ Program Director /Chair 5