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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
High-Speed Driving Scheme and Compact
High-Speed Low-Power Rail-to-Rail Class-B
Buffer Amplifier for LCD Applications
Chih-Wen Lu, Member, IEEE
Abstract—A high-speed driving scheme and a compact
high-speed low-power rail-to-rail class-B buffer amplifier, which
are suitable for small- and large-size liquid crystal display applications, are proposed. The driving scheme incorporates two output
driving stages in which the output of the first output driving
stage is connected to the inverting input and that of the second
driving stage is connected to the capacitive load. A compensation
resistor is connected between the two output stages for stability.
The second output stage is used to improve the slew rate and the
settling time. The buffer draws little current while static but has
a large driving capability while transient. The circuit achieves
the large driving capability by employing simple comparators
to sense the transients of the input to turn on the output stages,
which are statically off in the stable state. This increases the
speed of the circuit without increasing static power consumption
too much. A rail-to-rail folded-cascode differential amplifier is
used to amplify the input signal difference and supply the bias
voltages for the second stage. An experimental prototype output
buffer implemented in a 0.35- m CMOS technology demonstrates
that the circuit draws only 7- A static current and exhibits the
settling times of 2.7 s for rising and 2.9 s for falling edges for
a voltage swing of 3.3 V under a 600-pF capacitance load with
a power supply of 3.3 V. The active area of this buffer is only
46.5 57 m2 .
Index Terms—Class-B buffer amplifier, compensation resistor,
high-speed, LCD, liquid crystal display, low-power, rail-to-rail,
settling time, slew rate, stability.
I. INTRODUCTION
W
ITH the evolution of compact, light-weight, low-power
and high-quality displays, there is a large demand to
develop a low-power dissipation, high-speed, high-resolution
and large output swing liquid-crystal display (LCD) driver
[1], [2]. An LCD driver is generally composed of column
drivers, gate drivers, a controller, and a reference source.
The column drivers are especially important for achieving
high-speed driving, high resolution, low power dissipation, and
large output swing [3]–[5]. A column driver generally includes
registers, data latches, digital-to-analog converters (DACs) and
output buffers. Among those, the output buffers determine the
speed, resolution, voltage swing, and power dissipation of the
column drivers [6], [7]. Due to the thousands of output buffer
Manuscript received September 9, 2003; revised May 7, 2004. This work was
supported by the National Science Council of Taiwan, R.O.C., under Contract
NSC 92-2218-E-260-002-.
The author is with the Department of Electrical Engineering, National Chi Nan University, Puli, Nantou Hsien, Taiwan, R.O.C. (e-mail:
cwlu@ncnu.edu.tw).
Digital Object Identifier 10.1109/JSSC.2004.835821
amplifiers built into a single chip, the buffer should occupy
a small die area, and its static power consumption should be
small. The output buffer should offer an almost rail-to-rail
voltage driving which can accommodate higher gray levels.
Also, the settling time should be smaller than the horizontal
scanning time. For a UXGA (1600 1200) display, the pixel
clock frequency is 162 MHz and its horizontal scanning time
is only 9.877 s [3].
The output buffers, which are usually made of operational
amplifiers, are used to drive highly capacitive column lines of
the display panel. Because the load capacitance depends on the
size of the display panel, the output buffer should drive a wide
range of load capacitance [1], [8]. In addition, because the buffer
amplifiers are required to have a high open-loop gain to obtain a low value of the systematic offset voltage, a two-stage
buffer amplifier is usually used in the LCD driver [6], [7]. This
two-stage amplifier requires compensation for stability and the
conventional compensation scheme requires a Miller capacitance, which occupies a large area in an LCD driver. Some
buffer amplifiers adopt the output node as a dominant pole to
achieve enough stability without a Miller capacitance. For example, Lu et al. [9] proposed a class-AB output buffer for flat
panel display application, where the driving capability of the circuit is achieved by adding comparators which sense the rising
and/or falling edges of the input waveform to turn on a push/pull
transistor to charge/discharge the output load. Weng et al. [10]
proposed a compact, low-power, and rail-to-rail class-B output
buffer for driving the large column line capacitance of LCDs,
where a nonlinear element in feedback path is modified from
the current-mirror amplifier to obtain the area and power advantages. The above buffer amplifiers demonstrate high-speed
driving and low static power consumption. However, the phase
margin will be reduced for a lower value of output capacitance.
Although increasing the bias current of the differential stage will
increase the phase margin, it will also increase the power consumption. Hence, this type of buffer amplifier is not suitable
for a small-size LCD. Recently, Itakura et al. [11] proposed an
output amplifier in which the phase compensation is achieved by
introducing a zero, which is formed by the load capacitance and
the phase compensation resistor connected between the output
of the amplifier and the capacitive load. The stability is improved but the slew rate is limited to the compensation resistor.
Due to a small slew rate, the settling time will be large for a
large capacitive load. Hence, this type of buffer amplifier is not
suitable for a large-size LCD.
This work proposes a high-speed driving scheme and a compact high-speed low-power rail-to-rail class-B buffer amplifier,
0018-9200/04$20.00 © 2004 IEEE
LU: DRIVING SCHEME AND COMPACT RAIL-TO-RAIL CLASS-B BUFFER AMPLIFIER FOR LCD APPLICATIONS
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Fig. 2. Configuration of the buffer amplifier with the zero compensation.
Fig. 1. Open-loop frequency characteristic of the amplifier with the dominant
pole and zero compensation techniques.
which are suitable for small- and large-size LCD applications.
The driving scheme incorporates two output driving stages in
which the output of the first output driving stage is connected to
the inverting input and the output of the second driving stage is
connected to the capacitive load. The zero compensation technique, in which the compensation resistor is connected between
the outputs of the two output driving stages, is used for stability.
However, the slew rate is improved by the second output stage.
Hence, this scheme is suitable for a wide range of load capacitance. The proposed buffer draws only a little current while
static, but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple
comparators to sense the transients of the input to turn on the
output transistors, which are statically off in the stable state. This
increases the speed of the circuit without increasing static power
consumption too much.
Section II describes the proposed high-speed driving scheme,
while Section III shows the schematic of the proposed buffer
amplifier. Section IV demonstrates the experimental results, and
conclusions are presented in Section V.
II. PROPOSED HIGH-SPEED DRIVING SCHEME
In this section, the dominant pole and the zero compensation techniques are briefly described. Then the proposed driving
scheme is demonstrated.
Fig. 3. Configuration of the proposed driving scheme.
amplifier with the zero compensation technique. The zero,
is given by
(1)
is the load capacitance and
is the compensation
where
resistor. The value of the zero should be located to the left of the
unit-gain frequency to obtain stability. According to the analysis
by Itakura [1], the damping factor, , of the closed-loop secondi.e.,
order system is proportional to the value of
(2)
and
Here the phase margin is more than 70 degrees for
, the phase margin PM is
the amplifier is stable. For
approximately given by using [12]:
(3)
For the case of
expressed as
A. Review of Dominant Pole and Zero Compensation
Techniques
The open-loop frequency characteristic of the amplifier with
the dominant pole and zero compensation techniques are shown
in Fig. 1, where the solid line shows the frequency characteristic before compensation, the dotted line shows the frequency
characteristic after the dominant pole compensation with a large
output capacitive load, and the dashed line shows the frequency
characteristic after the zero compensation with a compensation resistor. For the dominant pole compensation, the dominant
pole, , is moved toward to the origin by increasing the load
capacitance. The larger value of the load capacitance gives a
larger value of the phase margin. However, the circuit may be
unstable for a small load capacitance. Hence, this scheme is not
suitable for a small-size LCD. For the zero compensation, a zero
is introduced to achieve an adequate value of phase margin. The
zero is formed by the load capacitance and the phase compensation resistor connected between the output of the amplifier and
the capacitive load. Fig. 2 shows the configuration of a buffer
,
, the output step response can be
(4)
where
(5)
is the natural frequency. Equation (4) shows that the
and
. From this analysis,
second term decays exponentially by
it can be seen that the value of should be large enough to
obtain an adequate value of phase margin and a small value
cannot be
of small-signal settling time. Thus, the value of
too small. However, the compensation resistor, which is connected between the output of the amplifier and the capacitive
load, limits the charge and discharge current. Hence, although
increases the phase margin and decreases
a larger value of
the small-signal settling time, it limits the large-signal slew rate.
Therefore, there is a tradeoff between the small-signal settling
time and the large-signal slew rate.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
Fig. 4. Equivalent circuit of the proposed two-stage amplifier.
B. Configuration of the Proposed High-Speed Driving Scheme
The proposed driving scheme, which is shown in Fig. 3, consists of one differential amplifier, A1, two output driving stages,
. The compenA21 and A22, and the compensation resistor,
sation resistor, which is used for stability for a small value of
load capacitance, is connected between the outputs of the two
output driving stages. As an output buffer, the output of A21
is connected to the inverting input of the differential amplifier,
while the output of A22 is applied to the capacitive load. The
slew rate is improved by the charge/discharge of A22. Hence,
this configuration can be used to drive a wide range of capacitive load.
is much larger than
omitted for simplicity. The value of
those of
,
, and
. The load capacitance is also much
larger than the parasitic capacitance. The approximation has
been made for this analysis.
As a buffer, “out1” is connected to the inverting input and the
input signal is applied to the noninverting terminal. The closed, is obtained as follows:
loop transfer function,
(11)
C. Analysis of Small-Signal Settling Time
For a large-signal step response, the settling time is the
summation of the slew-rate limiting settling time and the
small-signal settling time [1]. This subsection analyzes the
small-signal settling time of the proposed driving scheme. The
large-signal slew rate will be described in the next subsection.
The equivalent circuit of the proposed driving scheme is shown
in Fig. 4 where
,
and
are the transconductances
of the differential amplifier, A1, and the two output driving
,
and
are the output conducstages, A21 and A22;
tances of the differential amplifier and the two output driving
,
and
are the parasitic capacitances at
stages; and
output nodes of the differential amplifier and the two output
driving stages, respectively. The open-loop transfer function,
, can be obtained from Fig. 4. That is,
The load is connected to “out”, so we should obtain the transfer
function between the output and input. The relationship between
“out1” and “out” can be obtained from Fig. 4, and is given by
(12)
Then the closed-loop transfer function,
as follows:
, can be expressed
(13)
(6)
The above transfer function contains a large value of zero, which
is far away from other poles. Hence, it is neglected for simplicity. Then
is approximated by
where
(7)
(8)
(14)
(9)
where
(15)
(10)
The equivalent circuit contains three poles. However, the third
pole is far away from the other poles and zero, so it has been
(16)
LU: DRIVING SCHEME AND COMPACT RAIL-TO-RAIL CLASS-B BUFFER AMPLIFIER FOR LCD APPLICATIONS
where
is much greater than
be simplified as
1941
. Equation (16) can
(17)
The value of depends on the values of the load capacitance,
, and the compensation resistor,
. The larger values of
and
are, the larger value of is. The value of can be
to obtain an adequate
increased by increasing the value of
phase margin for a small load capacitance. Depending on the
value of , this system can be categorized in three cases [1], as
follows.
1) Underdamping (
): The step response can be
expressed as
(18)
Fig. 5. Large-signal equivalent circuits of the output stages for the rising (a)
and falling (b) edges, respectively.
In this case, the small-signal settling time is limited by
, and is inversely proportional to
. From (17) and (22),
can be expressed as
the term
where
(19)
Equation (18) shows that the small-signal settling time is in. From (7)–(9), (15), and (17),
versely proportional to
can be expressed as
(20)
,
, and
This equation reveals that larger values of
give a smaller value of small-signal settling time in the underdamping case.
): The step response can be ex2) Critical Damping (
pressed as
(21)
where
(22)
In this case, the above two equations show that the small-signal
settling time is independent of the value of
and it will be
large for a large load capacitance. However, increasing the
transconductances of the input and output stages will reduce
the small-signal settling time.
): The step response can be ex3) Overdamping (
pressed as
(23)
where
(25)
This equation shows that the added output stage, A22, will improve the small-signal settling time. Also, a larger value of
will obtain a smaller value of small-signal settling time.
The proposed high-speed driving scheme can also be used in
a three-stage amplifier. The analytic results are similar to those
of the two-stage amplifier. The damping factor is proportional
. Adjusting the value of
can obtain the required
to
phase margin.
D. Analysis of Slew Rate
With a realistic amplifier, the step response of the circuit begins to deviate from (18), (21), and (23) as the input amplitude increases. In CMOS operational amplifier design practice,
a push-pull stage is often used as an output stage. The push-pull
stage consists of two complementary common-source transistors, PMOS and NMOS [13], [14]. If the input experiences a
large signal, one of the output transistors will be in the triode region and the other one will be in the cut-off region. The PMOS
transistors of the output stages will be in the triode region but
their counterparts, the NMOS transistors, will be cut off for the
rising edge and vise versa for the falling edge. Fig. 5(a) and (b)
shows the large-signal equivalent circuits of the output stages
and
are
for the rising and falling edges, respectively.
the PMOS and NMOS channel resistances of the output transisand
are those of
tors of the output stage, A21, but
A22. With a rising edge of the input, the output response can be
expressed by
(26)
where
and
are the initial and final values of the output
voltage, respectively, and
(24)
(27)
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Fig. 6.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
Schematic of the proposed three-stage compact high-speed low-power rail-to-rail class-B buffer amplifier.
The positive slew rate can be expressed as
III. SCHEMATIC OF THE PROPOSED BUFFER AMPLIFIER
(28)
Similarly, the output response of the falling edge can be expressed by
(29)
where
(30)
The negative slew rate can be expressed as
(31)
From the small-signal analysis of the previous subsection, increasing the value of
can increase the phase margin. Howwill limit the charge/discharge of the corresponding
ever,
output stage. Fortunately, from (27) (28) and (30) (31), the
slew rates are improved by the second output stage A22. From
the small- and large- signal analysis, we can make a summary
for the design consideration of the proposed driving scheme:
can be chosen to be larger to obtain an adeThe value of
quate phase margin and a small value of small-signal settling
will not alleviate the slew rate betime. The large value of
cause of the second output stage. In order to obtain a small value
of settling time, the transconductances of the all stages can be
increased. For the consideration of the low-power design, only
the transconductances of the output stages are needed to be large
to achieve a small value of settling time.
Based on the above high-speed driving scheme, a three-stage
compact high-speed low-power rail-to-rail class-B buffer amplifier, as shown in Fig. 6, for LCD application is proposed. As a
buffer, “out1” is connected to the inverting input (
) and the
input signal is applied to the noninverting terminal (
). The
capacitive load is connected to the output, “out”. This buffer
consists of a bias stage (
), a rail-to-rail folded-cascode
differential amplifier (
), two comparators (
), the first rail-to-rail push-pull output stage (
),
the second output stage (
), and a compensation
resistor ( ). The rail-to-rail folded-cascode differential stage
amplifies the input signal difference and supplies the bias voltages for the next stage. The differential pairs
and
, which are biased by the constant current sources
and
, are actively loaded by the cascode current mirror
formed by
. The cascode current mirror is also used
as the summing circuit, which sums the currents of the differential pairs. The differential pairs are designed to have the same
bias current. Hence, the ratio between the aspect ratio of
to
that of
should be equal to the ratio between the
of
to that of
. The folded-cascode current mirror is used as the
active load of the rail-to-rail differential pair to obtain a large
gain and offer the bias voltages for the comparators. The comparators are used to amplify the voltage difference of two inputs.
Then the output of the comparators turn on/off the transistors of
the two output stages. The aspect ratios of
,
,
, and
are chosen to be the same as those of
,
,
, and
, respectively. However, the
of
is chosen to be
slightly smaller than that of
, and
to be slightly larger
than
, but the aspect ratio of
is a little bit larger than
that of
, and
is a little bit smaller than
.
In the stable state, the output voltage is equal to the input
voltage. The currents flowing in all transistors of the differential
pairs are
where
is the current in the bias stage. The
LU: DRIVING SCHEME AND COMPACT RAIL-TO-RAIL CLASS-B BUFFER AMPLIFIER FOR LCD APPLICATIONS
Fig. 7.
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Depiction of the operation of M19 and M20.
currents flowing in
and
have the
is equal to that of
same value. Hence, the drain voltage of
, and the drain voltage of
is equal to that of
. The
and
are given as
currents in
(32)
where
is the drain current of
. Since the gate voltages of
and
are equal to those of
and
, respectively,
and
are mirrored to
and
.
the currents in
is designed to be smaller than
Also, the aspect ratio of
and the
of
is larger than that of
,
that of
this causes
to be in the saturation region but
to go
out of the saturation region and be in the triode region. The curve, as shown in Fig. 7, depicts the operation of
and
, where the intersection of the two solid lines indicates the
drain-to-source voltage of
in the stable state. Neglecting
and
the channel length modulation, the current flowing in
can be expressed as
or increasing the
of
. Similarly, since the aspect
is larger than that of
and the
of
ratio of
is smaller than that of
, this causes
to be in the satto be in the triode region. As a result,
uration region but
the gate voltages of
and
are forced to a near
.
and
then stay off. That is,
and
The transistors
are cut off from the output nodes and consume no power
and
are in
in the stable state. In order to insure that
the cut-off region, the source-to-gate voltages of
and
should be smaller than the threshold voltage,
, i.e.,
(36)
where
(37)
(33)
Since
is in the triode region, the drain-to-source voltage of
can be approximately expressed as
(34)
where
(35)
is the electron mobility in the n channel, and
is
and
the threshold voltage of the NMOS transistor. In order to reduce the static power consumption, the transistors of the two
output stages are designed to be in the cut-off region. Therefore,
and
should be smaller
the gate-to-source voltages of
. That is: (34) should be smaller
than the threshold voltage,
. This can be achieved by decreasing the aspect ratio of
than
and
is the hole mobility in the p channel. The values of
and
can be reduced by increasing the aspect
or decreasing the
of
.
ratio of
When the input voltage,
, is reduced, the currents in M6
and M9 will be increased, but the currents in M7 and M8 will be
will be increased
decreased. The gate voltages of M12 and
will be decreased. As a
and the gate voltages of
result,
will go into the triode region and
will go into
the saturation region. The dashed lines of the - curves shown
and
. The
in Fig. 7 show the transient operation of
intersection of the lines is moved from P1 to P2. This shows
will increase to turn on
and
that the drain voltage of
. Then
and
start to discharge the output node.
and
are still in the cut-off region. When
However,
the output voltage reaches the level that the voltage difference
and
stop
between the input and output is almost zero,
and
discharging the output node. Since the gate voltages of
can reach a value of
,
and
can be turned to
fully “on” to discharge the output at a maximal speed. Similarly,
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
TABLE I
THE DEVICE SIZES USED IN THE BUFFER AMPLIFIER
Fig. 9. Simulated settling time versus different load capacitances under a
voltage swing of 3.3 V.
Fig. 8. Simulated slew rates versus different load capacitances under a voltage
swing of 3.3 V.
when the input voltage,
, is increased,
and
are still
and
cut off from the output, but the gate voltages of
are reduced and
and
start to charge the output load
until the output voltage almost equal to the input voltage. The
and
can be pulled down to very low
gate voltages of
and
can charge the output load at a maximal
levels, so
will limit the charge/disspeed. The compensation resistor
charge current of
/
, but it will not affect the charge/dis/
. In order to demonstrate the perforcharge ability of
mance of the two output stages, the slew rate and settling time
of the proposed output buffer were simulated by HSPICE. The
circuit, which is connected as a unit-gain buffer amplifier, was
simulated using the 0.35- m CMOS parameters with a power
supply of 3.3 V. The device sizes used in the proposed amplifier are shown in Table I. The bias currents of the differential
pair are selected to 2 times of the reference bias current, .
of
is chosen to be slightly smaller than that of
The
m
m, and
to be slightly larger than
M12 by
by
m
m. Also the aspect ratio of
is a little bit larger
than that of M12 by
m
m, and
is a little bit smaller
by
m
m. The selection of the ratio sizes for
than
the proposed buffer is not very critical. However, in order to obtain a compact area, the sizes of the devices are chosen to be
small. Fig. 8 shows the slew rates, which are simulated on the
proposed circuit but with and without the second output stage,
respectively, versus different load capacitances under a voltage
swing of 3.3 V. It can be seen that the slew rates of the circuit
Fig. 10. Die photograph of the proposed class-B buffer amplifier.
with the second output stage have been greatly improved. Fig. 9
shows the settling time versus different load capacitances under
a large voltage swing of 3.3 V. The settling time, which is the
time for the output to settle down within 5 mV, is also greatly
improved by the second output stage. Hence, the added second
output stage can improve the slew rate and the settling time.
IV. EXPERIMENTAL RESULTS
The proposed output buffer amplifier was fabricated using a
0.35- m CMOS technology. The die photograph is shown in
Fig. 10. Since the proposed circuit is rather neat, the active area
of the buffer is only 46.5 57 m . A quiescent current consumption of 7 A is measured at a power supply of 3.3 V. Since
) are off in the stable state,
the output transistors (
the quiescent current includes only the dc bias currents of the
bias stage, differential stage, and comparators. In the proposed
circuit, the compensation capacitor is at the output node. Hence,
the dc bias current can be designed to a very low value without
any degradation of the slew rate. Fig. 11 shows the measured
dc transfer characteristic of the unit-gain buffer amplifier. This
figure shows that the proposed circuit is a rail-to-rail buffer amplifier. The offset voltage versus different common-mode input
voltages is shown in Fig. 12, where the maximum offset voltage
LU: DRIVING SCHEME AND COMPACT RAIL-TO-RAIL CLASS-B BUFFER AMPLIFIER FOR LCD APPLICATIONS
Fig. 11.
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Measured dc transfer characteristic of the unit-gain buffer amplifier.
Fig. 14. Step response of the buffer loaded with a capacitance of 30 pF with
a 50-kHz square wave, where the input voltage swing is 20 mV and the upper
trace is the input waveform and the lower one is the measured output waveform.
Fig. 12. Measured offset voltage versus different common-mode input
voltages.
Fig. 15. Step response of the buffer loaded with a capacitance of 30 pF with a
50-kHz square wave, where the input voltage swing is 3.3 V and the upper trace
is the input waveform and the lower one is the measured output waveform.
Fig. 13. Measured results of the output with the input of a large dynamic range
(0 3:3 V) of a 20-kHz triangular wave of the proposed buffer amplifier loaded
with a large size capacitor of 600 pF (not including parasitic capacitances of the
pad and the test equipment).
is 12.2 mV and the mean is 5.7 mV for an input range of 3.3 V.
Since the open loop gain of the amplifier is very high, the offset
voltage is mainly caused by the fabrication process variation.
Fig. 13 shows the measured results of the output with the input
V) of a 20-kHz triangular
of a large dynamic range (
wave of the proposed buffer amplifier loaded with a large size
capacitor of 600 pF (not including parasitic capacitances of the
pad and the test equipment). The upper trace is the input waveform and the lower one is the measured output waveform. It
can be seen that the output basically follows the input for a
full swing. The step responses of the same buffer loaded with
a capacitance of 30 pF with the voltage swings of 20 mV and
3.3 V are shown in Figs. 14 and 15, respectively, where the upper
traces are the input waveforms and the lower ones are the measured output waveforms. They can be seen that the buffer can
be stable even the load capacitance is down to a small value of
30 pF. In order to show the performance of the buffer amplifier, Fig. 16 shows the same measurement but for a large load
capacitance of 600 pF. The slew rates are 4.52 V s and 4.22
V s for the rising and falling edges, respectively, and the settling times for the output to settle to within 5 mV of the final
voltage are only 2.7 and 2.9 s for the rising and falling edges,
respectively. Fig. 17 shows the measured slew rates compared
with the simulations for different load capacitances. Due to the
parasitic capacitances of the pad and the test equipment, there
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
TABLE II
PERFORMANCE SUMMARY OF THE PROPOSED BUFFER.
Fig. 18. The simulated and measured settling times for different values of the
load capacitances under a voltage swing of 3.3 V.
Fig. 16. Step response of the buffer loaded with a capacitance of 600 pF with a
50-kHz square wave, where the input voltage swing is 3.3 V and the upper trace
is the input waveform and the lower one is the measured output waveform.
shows the measured settling times compared with the simulations under a voltage swing of 3.3 V. The settling time is only
4.1 s even the load capacitance is up to a value of 1000 pF.
For a UXGA (1600 1200) display, the pixel clock frequency
is 162 MHz and its horizontal scanning time is 9.877 s. Hence,
this circuit can be used for a UXGA LCD. The performance of
the proposed buffer is summarized and compared with other circuits in Table II. Among the conventional buffers, Itakura’s circuit is a two-stage buffer with the zero compensation technique
but without the second stage [1]. Compared with the previous
buffers, the proposed circuit is superior in input/output voltage
range, area, quiescent power consumption, slew rate and settling
time.
V. CONCLUSION
Fig. 17. The simulated and measured slew rates for different values of the load
capacitances.
is a little bit of deviation between the simulated and measured
results for the small values of the load capacitances. Fig. 18
In this work, a high-speed driving scheme and a compact
high-speed low-power rail-to-rail class-B buffer amplifier,
which are suitable for small- and large-size LCD applications,
are proposed. The zero compensation technique is used for the
stability but the slew rate and the settling time are improved
by the second output stage. The value of the compensation
LU: DRIVING SCHEME AND COMPACT RAIL-TO-RAIL CLASS-B BUFFER AMPLIFIER FOR LCD APPLICATIONS
resistor can be chosen to be larger to obtain an adequate phase
margin and a small value of the small-signal settling time,
but it will not alleviate the slew rate because of the second
output stage. In order to obtain a small value of settling time,
the transconductances of the output stages can be increased.
The buffer draws little current while static but has a large
driving capability while transient. An experimental prototype
output buffer implemented in a 0.35- m CMOS technology
demonstrates that the circuit draws only 7- A static current
and exhibits the settling times of 2.7 s for rising and 2.9 s
for falling edges for a voltage swing of 3.3 V under a 600-pF
capacitance load with a power supply of 3.3 V. The active
area of this buffer is only 46.5 57 m . Compared with the
previous buffers, the performance of the proposed circuit is
superior in input/output voltage range, area, quiescent power
consumption, slew rate and settling time. The measured data
do show that the proposed output buffer circuit is very suitable
for small- and large- size LCD.
ACKNOWLEDGMENT
1947
[5] J.-S. Kim, D.-K. Jeong, and G. Kim, “A multi-level multi-phase
charge-recycling method for low-power AMLCD column drivers,”
IEEE J. Solid-State Circuits, vol. 35, pp. 74–84, Jan. 2000.
[6] T. Itakura, “A high slew rate operational amplifier for an LCD driver
IC,” IEICE Trans. Fundamentals, vol. E78-A, no. 2, pp. 191–195, Feb.
1995.
[7] C.-W. Lu, “Low-power high-speed class-AB buffer amplifiers for liquidcrystal display signal driver application,” J. Circuits, Syst. Comput., vol.
11, no. 4, pp. 427–444, Aug. 2002.
[8] TFT-LCD source drivers NT39360, NT3982, and NT3994. Novatek.
[Online]. Available: http://www.novatek.com.tw/
[9] C.-W. Lu and C. L. Lee, “A low power high speed class-AB buffer amplifier for flat panel display application,” IEEE Trans. VLSI Syst., vol.
10, pp. 163–168, Apr. 2002.
[10] M.-C. Weng and J.-C. Wu, “A compact low-power rail-to-rail class-B
buffer for LCD column driver,” IEICE Trans. Electron., vol. E85-C, no.
8, pp. 1659–1663, Aug. 2002.
[11] T. Itakura and H. Minamizaki, “A two-gain-stage amplifier without an
on-chip miller capacitor in an LCD driver IC,” IEICE Trans. Fundamentals, vol. E85-A, no. 8, pp. 1913–1920, Aug. 2002.
[12] G. F. Franklin, J. D. Powell, and A. Emami-Naeini, Feedback Control of
Dynamic Systems. Reading, MA: Addison Wesley, 1987, pp. 253–258.
[13] R. Gregorian, Introduction to CMOS OP-Amps and Comparators. New York: Wiley-Interscience, 1999, p. 149.
[14] C. -W. Lu and M. -L. Sheu, “High-speed class AB buffer amplifiers with
accurate quiescent current control,” in Proc. IEEE Asia-Pacific Conf.
ASIC, Taipei, Taiwan, Aug. 2002, pp. 157–160.
The author would like to thank the Chip Implementation
Center of National Science Council for their support in chip
fabrication.
REFERENCES
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Chih-Wen Lu (M’01) was born in Tainan, Taiwan,
R.O.C., on October 11, 1965. He received the B.S.
degree in electronic engineering from the National
Twiwan Institute of Technology, Taipei, in 1991, the
M.S. degree in electro-optics from National Chiao
Tung University, Hsinchu, Taiwan, in 1994, and the
Ph.D. degree in electronic engineering from National
Chiao Tung University.
During 1999–2001, he was an Assistant Professor
of the Department of Electrical Engineering, Da-yeh
University. He joined the National Chi Nan University, Puli, Nan-Tou, Taiwan, in 2001, and is currently an Assistant Professor in
the Department of Electrical Engineering. His research interests include lowpower analog design, LCD driver design, and analog/mixed-mode IC design.