144 ILEL JOURNAL OF SOLID-STATL CIRCUITS, VOL 24, NO 3, JUNE 1989 Special Correspondence A Very-High-Slew-Rate CMOS Operational Amplifier DYNAMIC STATIC R. KLINKE, MEMBER. IEEE. B. J. HOSTICKA. SENIOR MEMBER, IEEE. AND H:J. PFLEIDERER, SENIOR MEMBER, IEEE Abstruct -In this contribution we present a very-high-slew-rate CMOS operational amplifier. It uses a circuit to inject an extra bias current into a conventional source-coupled CMOS differential input stage in the presence of large differential input signals. This measure substantially increases the slew rate of an operational amplifier for a given quiescent current. We compare the performance of this operational amplifier to a conventional operational amplifier when used in a sample-and-hold circuit. The maximum operating clock frequency of the sample-and-hold increases from 290 kHz to 1 MHz with a hold capacitor of 1 nF. The amplifier has been fabricated in a 5-pm CMOS process and dissipates a static power of 7.5 mW. \I I INM I Fig. 1. Principle of the very-high-slew-rate operational amplifier I. INTRODUCTION The settling time of an operational amplifier is one of its key parameters. Although it is difficult to be determined analytically, it can be stated that the settling time is a composite parameter, which is affected by the slew rate and the frequency response [I], [2]. For a specified capacitive load, input voltage step, and power dissipation, there always appears to be a physical limit to the settling time in a given technology. Above all, this is true for the part determined by the frequency response, which is usually the final part of the step response before the amplifier completely settles and where the small-signal behavior prevails [3]. The initial part of the step response behavior is, however, governed by the large-signal properties of the amplifier: the amplifier slews after a differential step has been applied to its input. The slewing rate is given by the maximum available current to charge up all the capacitances (including load and compensation capacitors): S,=-. La, (1) cm Thus, for a given capacitance, the power consumption imposes a definite limit to the slew rate. A possible solution to circumvent this limit is to use some kind of class-B input stage [4], controlled input stage [ 5 ] , adaptive biasing [6], or dynamic biasing [7]. 11. CIRCUITDESCRIPTION The solution presented here uses a circuit that monitors the signals at the input of the amplifier (see Fig. 1). If a large differential signal has been detected, the bias current is temporarily increased in order to enhance the slew rate. This technique necessarily requires some extra circuitry, and this circuitry must fulfill the following requirements: 1) small chip area, 2) low power dissipation, and 3) no degradation of the electrical characteristics of the underlying operational amplifier (noise, input Manuscript received September 20. 1988: revised February 16, 1989 R. Klinke and B. J. Hosticka are with the Fraunhofer Institute for M i c r e electronic Circuits and Systems, Duisburg, West Germany. H.-J. Pfleiderer is with the Central Research and Development Department. Siemens AG, Munich. West Germany. IEEE Log Number 8927703. impedance, offset, etc.). It is the last requirement that is especially hard to meet [SI (e.g., a class-B input stage usually worsens the input offset and the noise voltage). The solution illustrated in Fig. 1 avoids most of the disadvantages associated with such schemes [9]. The static-biasing circuit supplies the current during the small-signal operation and thus determines the small-signal properties of the operational amplifier (the dynamic bias is OFF). Only large differential signals at the input can turn the dynamic bias ON. Hence, the small-signal characteristics remain unaffected except for the input capacitance, which is slightly increased owing to the additional input differential stage. As it will be seen later, the load of this stage is a low impedance when the dynamic bias is OFF, and thus there is no Miller effect. The actual realization of the very-high-slew-rate operational amplifier can be found in Fig. 2(a). The operational amplifier consists of the static bias circuit ( M l - M4), the single-stage core amplifier (M10- M13, M15, M17- M20), and the additional differential input stage ( M 6 - M 8 ) with the transistors M5 and M9 acting as load devices. The latter can turn on the transistors M14 or M16 to inject more bias current into the differential input stage of the core amplifier if a sufficiently large differential input voltage has appeared at the input. The ratio of M 3 and M4 warrants equal effective gate-source voltages at M5, M 7 , and M9. Since M5, M 7 , and M9 have all been designed as current sources, M5 and M9 must enter the linear region if the factor a (the ratio of W5,9/L5,9to W , / L , normalized to the ratio of W,/L, to W , / L , ) is greater than 0.5. The current of the transistors M5, M 7 , and M9 in strong inversion without an input signal is The drain-source voltages of M5 and M 9 can be calculated from 0018-9200/89/0600-0744$01.00 01989 IEEE IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 24, NO. 3 , JUNE 1989 145 VDD vss CORE AMPLIFIER DYNAMIC BIAS STATIC BIAS I INP 1 I I 1 1 - I (b) Fig. 2. (a) Very-high-slew-rate operational amplifier. (b) Core amplifier higher slew rate. The maximum voltage of the drain-source voltage of M 5 and M9 is given by the open-loop voltage gain of the input stage and the input voltage: VDS5.9max - gn16.8 gds6~U+ g d s 7 . 9 “IN. The amplifier shown in Fig. 2(b) is exactly the same as the core amplifier contained in Fig. 2(a). It was designed only to serve as a reference for comparison with the amplifier in Fig. 2(a), and it was not optimized for any particular application. Fig. 3. Chip photomicrograph and (3): Thus, we can choose the biasing and the size of the current sources M 5 , M 7 , and M9 so that the low drain-source voltages of M 5 and M9 guarantee turning off M14 and M16 when no input signal is at the input. With a differential voltage present at the input, the symmetry condition is not met anymore, and one of the current sources, M 5 or M9, can enter the saturation region subject to the applied voltage and dimension of the devices. A large tail bias current is added to that of M15 and gives rise to a 111. MEASUREMENTS The amplifiers shown in Fig. 2(a) and (b) have been integrated in CMOS silicon-gate technology with 40-nm gate oxide and 1.8 X 1014 cm33 p-substrate. The doping of the n-wells was 1.8 X 10l6 ~ m - The ~ . channel length of all devices was 5 pm. The threshold voltages were 1 V for NMOS and -1 V for PMOS devices. The power supply voltages were i5 V. The chip photomicrograph of the amplifiers is shown in Fig. 3. The chip area (without bonding pads) is 0.63 mm2 for the amplifier of Fig. 2(a) and 0.55 mm’ for the core amplifier of Fig. 2(b). The measured data of both amplifiers have been summarized in Table I. The superior performance of the amplifier of Fig. 2(a) is clearly visible. Interestingly enough, its settling time has been found almost constant for any combination of input voltage steps and capacitive loads: thus, for 1 V,, and 15 pF, the amplifier IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 146 1 I PARAMETER TABLE 1 HIGH-SLEU RATE OPERATIONAL AHPLIFIER OF Flg. 2a CORE OPERATIONAL AMPLIFIER OF Flg. 2b STATIC POUER DISSIPATION 7 U. 1 . 5 mU 54 dB 100 pF 5 MHz 1.611.6 Vusec-1 3000/2900 24, NO. 3, JUNE 1989 mally OFF. The measurements showed, however, that the noise slightly increased, e.g., the noise voltage density at 10 kHz rose from 70 to 85 nV/JHz. The total harmonic distortion increased from -69 to -68 dB for 0.5 V,, and 100 kHz sine wave. On the other hand, the power supply rejection ratio is 78 dB, and the common-mode rejection ratio is 64 dB for both amplifiers. Fig. 4 depicts the step response (1 V,,) of the high-slew-rate operational amplifier when loaded with an off-chip 1-nF capacitor. The slew rate still reaches about 6 V.ps-’, whereas the total current consumption peaks at 19.5 mA. This means a temporary increase of current by a factor of 26. The property of nearly constant settling time can be utilized in a simple sample-and-hold circuit. The maximum operating clock frequency of the circuit increases from 290 kHz with the core amplifier of Fig. 2(b) up to 1 MHz with the dynamic amplifier of Fig. 2(a) [lo]. Iv. SUMMARY We have presented a very-high-slew rate operational amplifier. It features an additional differential input stage that increases the bias current of the amplifier in order to enhance the slew rate. The small-signal behavior remains almost unchanged by this addition. The measurements of the integrated prototype have yielded slew rates up to 100 V.ps-’. nsec ACKNOWLEDGMENT C The authors wish to thank Dr. L. Lerach and Dr. R. Koch for their continuous encouragement and support. \ REFERENCES A B Fig. 4. Step response of the amplifier of Fig. 2(a) with load 1 n F (trace A: input voltage, trace B: amplifier response, trace C: total current of the amplifier at 68 CL). settled in 300 and 340 ns within 1-percent error band for positive and negative step, respectively (the corresponding slew rates are 41 and 44 V.ps-’). On the other hand, for 7 Vpp and 100 pF, the settling times were 300 and 270 ns, and the slew rates were 60 and 56 V . p s The small-signal properties of the high-slew rate operational amplifier had been expected to be the same as those of the core amplifier because the additional differential input stage is nor- ’. P. R. Gray and R. G. Meyer, “Recent advances in monolithic operational amplifier design,” IEEE Truns. Circuits Syst., vol. CAS-21. pp. 317-327, May 1974. J.-C. Lin and J. H. Nevin, “ A modified time domain model for nonlinear analysis of an operational amplifier,” IEEE J . Solid-Store Circuits, vol. SC-21, pp. 478-483, June 1986. K. Matsui, T. Matsuura, and K. Iwasahi, “2 pm CMOS switched capacitor circuits for analog video LSI.” in Proc. ISCAS, May 1982. pp. 241-244 P. R. Gray and R. G. Meyer, Anulysis and Design of Anulog Integruted Circuits. 2nd ed. New York: Wiley, 1984, pp. 755-756. J. N. Babanezhad and G . C. Temes, “A 20-V four-quadrant CMOS analog multiplier,” IEEE J . Solid-Store Circuits, vol. SC-20, pp. 1157-1168, Dec. 1985. M. G. Degrauwe, J. Rijmenants, E. A. Vittoz, and H. J. De Man. “Adaptive biasing CMOS amplifiers,” IEEE J . Solid-Stute Circuits. vol. SC-17, pp. 522-528, June 1982. B. J. Hosticka. “Dynamic CMOS amplifiers,” IEEE J . Solid-state Circuits, vol. SC-15, pp. 887-894, Oct. 1980. W. E. Hearn. “Fast slewing monolithic operational amplifier.” IEEE J . Solid-Stute Circuits. vol. SC-6, pp. 20-24, Feb. 1971. B. J. Hosticka, R. Klinke, and H. -J. Pfleiderer, “Differenzverstarker mit steuerbarer Leistungsaufnuhme,” Patent pending. J. Eichholz, “Entwicklung eines schnellen Abtast-Halte-Gliedes in CMOS-Technik,” Studienarbeit, Universitat-GesamthochschuleDuisburg. Feb. 1988.