a
Next Generation OP07
Ultralow Offset Voltage Operational Amplifier
OP77
FEATURES
Outstanding Gain Linearity
Ultrahigh Gain 5000 V/mV Min
Low VOS Over Temperature 60 ␮V Max
Excellent TCVos 0.3 ␮V/ⴗC Max
High PSRR 3 ␮V/V Max
Low Power Consumption 60 mW Max
Fits OP07, 725,108A/308A, 741 Sockets
Available in Die Form
PIN CONNECTIONS
Epoxy Mini-Dip (P-Suffix)
8-Pin Hermetic DIP
VOS TRIM 1
8
OP07
VOS TRIM
–IN 2
7 V+
+IN 3
6 OUT
V– 4
5 NC
NC = NO CONNECT
TO-99
(J-Suffix)
GENERAL DESCRIPTION
The OP77 significantly advances the state-of-the-art in precision
op amps. The OP77’s outstanding gain of 10,000,000 or more
is maintained over the full 10 V output range. This exceptional
gain-linearity eliminates incorrectable system nonlinearities
common in previous monolithic op amps, and provides superior
performance in high closed-loop gain applications. Low initial
VOS drift and rapid stabilization time, combined with only 50
mW power consumption, are significant improvements over
previous designs. These characteristics, plus the exceptional
TCVOS of 0.3 mV/∞C maximum and the low VOS of 25 mV maximum, eliminates the need for VOS adjustment and increases
system accuracy over temperature.
VOS TRIM
VOS TRIM 1
V+
OP07
OUT
–IN 2
NC
+IN 3
4V– (CASE)
NC = NO CONNECT
PSRR of 3 mV/V (110 dB) and CMRR of 1.0 mV/V maximum
virtually eliminate errors caused by power supply drifts and
common-mode signals. This combination of outstanding characteristics makes the OP77 ideally suited for high-resolution
instrumentation and other tight error budget systems.
V+
7
R2A (OPTIONAL
NULL)
8
1
R1A
NOTE:
R2A AND R2B ARE
ELECTRONICALLY
ADJUSTED ON CHIP
AT FACTORY.
Q7
INVERTING
INPUT
R1B
Q19
Q10
Q11
Q8
Q3
Q6
Q4
Q27
3 R3
C3
R9
Q12
Q17
C2
Q21
Q22
Q20
Q26
Q23
Q24
Q15
Q25
Q2
4
OUTPUT
6
R10
Q16
R5
Q1
2 R4
R7
C1
Q9
Q5
NONINVERTING
INPUT
R2B
Q18
Q14
Q13
R6
R8
V–
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
OP77–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = ⴞ15 V, T = 25ⴗC, unless otherwise noted.)
s
A
OP77A
Typ
Max
Unit
VOS
10
25
mV
VOLTAGE STABILITY1
DVOS/Time
0.2
mV/Mo
INPUT OFFSET CURRENT
IOS
0.3
nA
INPUT BIAS CURRENT
IB
Parameter
Symbol
INPUT OFFSET VOLTAGE
Conditions
Min
LONG-TERM INPUT OFFSET
–0.2
1.2
2.0
nA
enp-p
0.1 Hz to 10 Hz
0.35
0.6
mV p-p
en
fO = 10 Hz
fO = 100 Hz
fO = 1000 Hz
10.3
10.0
9.6
18.0
13.0
11.0
nV/÷Hz
inp-p
0.1 Hz to10 Hz
14
30
pA p-p
INPUT NOISE CURRENT DENSITY
in
fO = 10 Hz
fO = 100 Hz
fO = 1000 Hz
0.32
0.14
0.12
0.80
0.23
0.17
pA/÷Hz
INPUT RESISTANCE
Differential Mode3
Common Mode
RIN
RINCM
26
45
200
MV
GV
INPUT VOLTAGE RANGE
IVR
± 13
± 14
V
COMMON-MODE
REJECTION RATIO
CMRR
VCM = ± 13 V
0.1
1.0
mV/V
POWER SUPPLY
REJECTION RATIO
PSRR
VS = ± 3 V to ± 18 V
0.7
3
mV/V
LARGE-SIGNAL
VOLTAGE GAIN
AVO
RL ≥ 2 kW ≥ VO = ± 10V
5000
12000
V/mV
OUTPUT VOLTAGE SWING
VO
RL ≥ 10 kW
RL ≥ 2 kW
RL ≥ 1 kW
± 13.5
± 12.5
± 12.0
± 14.0
± 13.0
± 12.5
V
SR
RL ≥ 2 kW
0.1
0.3
V/ms
BW
AVCL = +1
0.4
0.6
MHz
60
W
2
INPUT NOISE VOLTAGE
2
INPUT NOISE VOLTAGE DENSITY
INPUT NOISE CURRENT2
2
SLEW RATE2
2
CLOSED-LOOP BANDWIDTH
OPEN-LOOP OUTPUT RESISTANCE RO
POWER CONSUMPTION
OFFSET ADJUSTMENT RANGE
Pd
VS = ± 15 V, No Load
VS = ± 3 V, No Load
50
3.5
RP = 20 kW
±3
60
4.5
mW
mV
NOTES
1
Long-Term Input Offset Voltage Stability refers to the averaged trend line of V OS vs. Time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in V OS during the first 30 operating days are typically 2.5 mV.
2
Sample tested.
3
Guaranteed by design.
–2–
REV. C
OP77
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = ⴞ15 V, –55ⴗC £ T £ 125ⴗC, unless otherwise noted.)
s
A
OP77A
Typ
Max
Unit
VOS
25
60
mV
AVERAGE INPUT OFFSET
VOLTAGE DRIFT1
TCVOS
0.1
0.3
mV/∞C
INPUT OFFSET CURRENT
IOS
0.5
2.2
nA
AVERAGE INPUT OFFSET
CURRENT DRIFT2
TCIOS
1.5
25
pA/∞C
INPUT BIAS CURRENT
IB
2.4
4
nA
AVERAGE INPUT BIAS
CURRENT DRIFT2
TCIB
8
25
pA/∞C
INPUT VOLTAGE RANGE
IVR
± 13.5
0.6
V
COMMON-MODE
REJECTION RATIO
CMRR
VCM = ± 13 V
0.1
1.0
mV/V
POWER SUPPLY
REJECTION RATIO
PSRR
VS = ± 3 V to ± 18 V
1
3
mV/V
LARGE-SIGNAL
VOLTAGE GAIN
AVO
RL ≥ 2 kW ≥ VO = ± 10 V
2000
6000
V/mV
OUTPUT VOLTAGE SWING
VO
RL ≥ 10 kW
± 12
± 13.0
V
POWER CONSUMPTION
Pd
VS = ± 15 V, No Load
Parameter
Symbol
INPUT OFFSET VOLTAGE
Conditions
–0.2
± 13
NOTES
1
OP77A: TCVCS is 100% tested.
2
Guaranteed by design.
REV. C
Min
–3–
60
75
mW
OP77–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = ⴞ15 V, T = 125ⴗC, unless otherwise noted.)
s
A
Conditions
Min
OP77E
Typ Max
Parameter
Symbol
INPUT OFFSET VOLTAGE
VOS
10
LONG-TERM
STABILITY1
VOS/Time
0.3
INPUT OFFSET CURRENT
IOS
INPUT BIAS CURRENT
IB
INPUT NOISE VOLTAGE2
enp-p
INPUT NOISE
VOLTAGE DENSITY
Min
25
OP77F
Typ Max
Unit
20
mV
60
mV/Mo
0.4
0.3
1.5
1.2
2.0
0.1 Hz to 10 Hz
0.35
en
fO = 10 Hz
fO = 100 Hz2
fO = 1000 Hz
INPUT NOISE CURRENT2
inp-p
INPUT NOISE
CURRENT DENSITY
in
INPUT RESISTANCE
Differential Mode3
Common Mode
RIN
RINCM
INPUT RESISTANCE
Common Mode
RINCM
INPUT VOLTAGE RANGE
IVR
COMMON-MODE
REJECTION RATIO
CMRR
VCM = ⫾13 V
0.1
1.0
0.1
1.6
mV/V
POWER SUPPLY
REJECTION RATIO
PSRR
VS = 3 V to 18 V
0.7
3.0
0.7
3.0
mV/V
LARGE-SIGNAL
VOLTAGE GAIN
AVO
RL ≥ 2 k⍀
5000
OUTPUT VOLTAGE
SWING
VO
RL ≥ 10 k⍀
RL ≥ 2 k⍀
RL ≥ 1 k⍀
⫾13.5 ⫾14.0
⫾12.5 ⫾13.0
⫾12.0 ⫾12.5
⫾13.5 ⫾14.0
⫾12.5 ⫾13.0
⫾12.0 ⫾12.5
V
SLEW RATE2
SR
RL ≥ 2 k⍀
0.1
0.3
0.1
0.3
V/ms
CLOSED-LOOP
BANDWIDTH2
BW
AVCL 1
0.4
0.6
0.4
0.6
MHz
OPEN-LOOP OUTPUT
RESISTANCE
RO
60
W
POWER CONSUMPTION
Pd
OFFSET ADJUSTMENT
RANGE
0.3
2.8
nA
1.2
2.8
nA
0.6
0.38
0.65
mVp-p
10.3
10.0
9.6
18.0
13.0
11.0
10.5
10.2
9.8
20.0
13.5
11.5
nV/÷Hz
0.1 Hz to 10 Hz
14
30
15
35
pAp-p
fO = 10 Hz
fO = 100 Hz2
fO = 1000 Hz
0.32
0.14
0.12
0.80
0.23
0.17
0.35
0.15
0.13
0.90
0.27
0.18
pA÷Hz
–0.2
26
45
200
–0.2
18.5
200
⫾13
⫾14
⫾13
12000
2000
60
VS = ⫾15 V, No Load
VS = ⫾3 V, No Load
50
3.5
Rp = 20 kn
⫾3
60
4.5
45
200
MW
GW
200
GW
⫾14
V
6000
50
3.5
⫾3
V/mV
60
4.5
mW
mV
NOTES
1
Long-Term Input Offset Voltage Stability refers to the averaged trend line of V OS vs. Time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in V OS during the first 30 operating days are typically 2.5 mV.
2
Sample tested.
3
Guaranteed by design.
–4–
REV. C
OP77
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = ⴞ15 V, –25ⴗC £ T £ +85ⴗC for OP77E/FJ and OP77E/FZ, unless otherwise noted.)
s
A
Min
OP77E
Typ Max
Symbol
Conditions
INPUT OFFSET VOLTAGE
V
J. Z Packages
10
10
45
55
20
20
100
100
mV
AVERAGE INPUT OFFSET
VOLTAGE DRIFT1
TVCOS
J. Z Packages
0.1
03
0.3
0.6
0.2
0.4
0.6
1.0
mV/∞C
INPUT OFFSET CURRENT
IOS
0.5
2.2
0.5
4.5
nA
AVERAGE INPUT OFFSET
CURRENT DRIFT2
TCIOS
1.5
4.0
1.5
85
pA/⬚C
INPUT BIAS CURRENT
IB
2.4
4.0
2.4
6.0
nA
AVERAGE INPUT BIAS
CURRENT DRIFT2
TCIB
8
40
15
60
pA/∞C
INPUT VOLTAGE RANGE
IVR
COMMON-MODE
REJECTION RATIO
CMRR
VCM = ⫾13 V
0.1
1.0
0.1
3.0
pVlV
POWER SUPPLY
REJECTION RATIO
PSRR
VS = ⫾3 V to ⫾18 V
1.0
3.0
1.0
5.0
mV/V
LARGE-SIGNAL
VOLTAGE GAIN
AVO
RL ≥ 2 kW
VO = ⫾10 V
2000
6000
OUTPUT VOLTAGE SWING
VO
RL ≥ 2 kW
⫾12
⫾13.0
POWER CONSUMPTION
Pd
VS = ⫾15 V, No Load
E, F
-0.2
⫾13.0 ⫾13.5
NOTES
1
OP77E: TCVOS is 100% tested on J and Z packages.
2
Guaranteed by end-point limits.
REV. C
–5–
60
Min
OP77F
Typ Max
Parameter
-0.2
⫾13.0 ⫾13.5
75
1000
4000
⫾12
⫾13.0
60
Unit
V
V/mV
V
75
mW
OP77–SPECIFICATIONS
WAFER TEST LIMITS (@ V = ⴞ15 V, T = 25ⴗC, for OP77N devices, unless otherwise noted.)
s
A
Parameter
Symbol
Conditions
OP77N
Limit
Unit
INPUT OFFSET VOLTAGE
VOS
40
mV Max
INPUT OFFSET CURRENT
IOS
2.0
nA Max
INPUT BIAS CURRENT
IB
±2
nA Max
INPUT RESISTANCE
Differential Mode
RIN
26
MW Min
INPUT VOLTAGE RANGE
IVR
± 13
V Min
COMMON-MODE REJECTION RATIO
CMRR
VCM = ± 13 V
1
mV/V Max
POWER SUPPLY REJECTION RATIO
PSRR
VS = ± 3 V to ± 18 V
3
mV/VMax
OUTPUT VOLTAGE SWING
VO
RL = 10 kW
RL = 2 kW
RL = 1 kW
± 13.5
± 12.5
± 12.0
V Min
LARGE-SIGNAL VOLTAGE GAIN
AVO
RL = 2 kW
VO = ± 10 V
2000
V/mV Min
± 30
V Max
Pd
VOUT = 0 V
60
mW Max
DIFFERENTIAL INPUT VOLTAGE
POWER CONSUMPTION
NOTES
1
Guaranteed by design.
2
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS (@ V = ⴞ15 V, T = 25ⴗC, unless otherwise noted.)
s
A
Parameter
Symbol
Conditions
OP77N
Limit
Unit
AVERAGE INPUT OFFSET VOLTAGE DRIFT
TCVOS
RS = 50 W
0.1
mV/OC
NULLED INPUT OFFSET VOLTAGE DRIFT
TCVOSn
RS = 50 W, RP = 20 kW
0.1
mV/∞C
AVERAGE INPUT OFFSET CURRENT DRIFT
TCIOS
0.5
pA/∞C
SLEW RATE
SR
RL ≥ 2 kW
0.3
V/ms
BANDWIDTH
BW
AVCL + 1
0.6
MHz
–6–
REV. C
OP77
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 30 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
J and Z Packages . . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
OP77A . . . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C
OP77E, OPP77F (J, Z) . . . . . . . . . . . . . . . . –25∞C to +85∞C
Junction Temperature (Tj) . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 60 sec.) . . . . . . . . . . . . . 300∞C
NOTES
1
Absolute Maximum Ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than ± 22 V, the absolute maximum input voltage is
equal to the supply voltage.
Package Type
␪jAⴱ
␪jC
Unit
TO-99 (J)
8-Lead Hermetic DIP (Z)
150
148
18
16
∞C/W
∞C/W
NOTE
ⴱ
␪jA is specified for worst-case mounting conditions, i.e., ␪jA is specified for
device in socket for TO, CERDIP, P-DIP, and PLCC packages; ␪jA is specified
for device soldered to printed circuit board for SO package.
BONDING DIAGRAM
1. BALANCE
2. INVERTING INPUT
3. NONINVERTING INPUT
4. V6. OUTPUT
7. V+
8. BALANCE
DIE SIZE 0.093 ⴛ 0.057 inch, 5301 sq. mm
(2.36 ⴛ 1.45 mm, 3.42 sq. mm)
ORDERING GUIDE
Package Options
CERDIP*
TO-99
8-Lead
OP77EJ
OP77FJ
ⴱ
OP77AZ
OP77EZ
OP77FZ
Operating
Temperature
Range
MIL
IND
IND
Not for new designs; obsolete April 2002.
For Military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
SMD Part Number
ADI Equivalent
5962-87738012A
5962-8773802GA
5962-8773802PA
OP77BRCMDA
OP77AJMDA
OP77AZMDA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP77 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. C
–7–
WARNING!
ESD SENSITIVE DEVICE
OP77–Typical Performance Characteristics
2
16
25
VS = ⴞ15V
TA = 25ⴗC
–1
–2
–10
–5
0
5
OUTPUT VOLTAGE – V
OPEN-LOOP GAIN – V/␮V
0
15
10
5
0
–55 –35 –15
10
TPC 1. Gain Linearity (Input
Voltage vs. Output Voltage)
J, Z PACKAGES
+0.3␮V/ⴗC
20
MEAN
S.D.
10
0
–10
–20
–0.3␮V/ⴗC
–30
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE – ⴗC
OPEN-LOOP GAIN – dB
60
40
20
3
TA = 25ⴗC
2
1M
10M
TPC 7. Closed-Loop Response for
Various Gain Configurations
DEVICE IMMERSED IN
70ⴗC OIL BATH (20 UNITS)
20
1
15
0
–1
10
–2
–3
MAX
5
AVE
MIN
0
–4
0
VS = ⴞ15V
0
20
30 40
TIME – SEC
50
60
70
150
TA = 25ⴗC
TA = 25ⴗC
140
45
120
10
TPC 6. Offset Voltage Change
Due to Thermal Shock
100
130
120
90
80
110
60
135
40
100
90
20
1k
10k
10k
FREQUENCY – Hz
VS = ⴞ15V
25
0
–20
ⴞ20
30
140
TA = 25ⴗC
ⴞ5
ⴞ10
ⴞ15
POWER SUPPLY VOLTAGE – V
TPC 3. Open-Loop Gain vs.
Power Supply Voltage
VS = ⴞ15V
160
100
0
TPC 5. Warm-Up Drift
VS = ⴞ15V
CLOSED-LOOP GAIN – dB
0
0.5
1
1.5
2
2.5
3
3.5
0
TIME AFTER POWER SUPPLY TURN-ON – MINUTES
100
10
4
5
25 45 65 85 105 125
TEMPERATURE – ⴗC
4
TPC 4. Untrimmed Offset
Voltage vs. Temperature
80
8
TPC 2. Open-Loop Gain vs.
Temperature
CHANGE IN INPUT OFFSET VOLTAGE – ␮V
CHANGE IN OFFSET VOLTAGE – ␮V
30
RL = 2k⍀
12
ABSOLUTE CHANGE IN INPUT OFFSET
VOLTAGE – ␮V
RL = 10k⍀
CMMR –dB
1
TA = 25ⴗC
20
OPEN-LOOP GAIN – V/␮V
INPUT VOLTAGE – ␮V
(NULLED TO 0␮ @VOUT = 0V)
VS = ⴞ15V
0
0.01 0.1
1
180
10 100 1k 10k 100k 1M
FREQUENCY – Hz
TPC 8. Open-Loop Gain/Phase
Response
–8–
80
1
10
100
1k
FREQUENCY – Hz
10k
100k
TPC 9. CMRR vs. Frequency
REV. C
OP77
130
4
110
100
90
80
VS = ⴞ15V
INPUT OFFSET CURRENT – nA
INPUT BIAS CURRENT – nA
120
PSRR – dB
2.0
VS = ⴞ15V
TA = 25ⴗC
3
2
1
70
60
0.1
1.0
0.5
0
10
100
FREQUENCY – Hz
1k
0
–50
10k
0
50
TEMPERATURE – ⴗC
–50
100
TPC 11. Input Bias Current
vs. Temperature
10
1000
INPUT NOISE VOLTAGE – nV/ Hz
TA = 25ⴗC
1.0
100
32
RS1 = RS2 = 200kV
THERMAL NOISE OF SOURCE
RESISTORS INCLUDED
VS = ⴞ15V
0
50
TEMPERATURE – ⴗC
TPC 12. Input Offset Current
vs. Temperature
PEAK-TO-PEAK AMPLITUDE – V
1.0
TPC 10. PSRR vs. Frequency
RMS NOISE – mV
1.5
EXCLUDED
100
RS = 0
10
VS = ⴞ15V
VS = ⴞ15V
28
TA = 25ⴗC
24
20
16
12
8
4
TA = 25ⴗC
1
1k
10k
FREQUENCY – Hz
1
100k
TPC 13. Input Wideband Noise vs.
Bandwidth (0.1 Hz to Frequency
Indicated)
20
TA = 25ⴗC
VS = ⴞ15V
MAXIUM OUTPUT – VOLTS
TA = 25ⴗC
10
0
0
10
20
30
40
TOTAL SUPPLY VOLTAGE, V+ TO V – V
TPC 16. Power Consumption vs.
Power Supply
REV. C
15
VIN = ⴞ10mV
POSITIVE SWING
NEGATIVE SWING
10
5
0
100
0
1k
1k
TPC 14. Total Input Noise
Voltage vs. Frequency
100
POWER CONSUMPTION – mW
10
100
FREQUENCY – Hz
TPC 17. Maximum Output Voltage
vs. Load Resistance
–9–
1M
40
VS = ⴞ15V
TA = 25ⴗC
35
30
25
20
15
1k
10k
LOAD RESISTANCE TO GROUND – ⍀
10k
100k
FREQUENCY – Hz
TPC 15. Maximum Output Swing
vs. Frequency
OUTPUT SHORT-CIRCUIT CURRENT – mA
0.1
100
0
4
1
2
3
TIME FROM OUTPUT BEING SHORTED –
MINUTES
TPC 18. Output Short-Circuit
Current vs. Time
OP77
200k⍀
TYPICAL
PRECISION OP AMP
50⍀
10k⍀
VO
OP77
100k⍀
VY
1M⍀
VOS =
VO
4000
VIN = 10V
VX
VX
–10V
10⍀
Figure 1. Typical Offset Voltage Test Circuit
AVO ~ 650V/mV
V+
2
100⍀
3
7
OUTPUT
4.7␮F
4
(
V–
20k⍀
V+
INPUT +
3
3. CHECK THE OP AMP PERFORMANCE, ESPECIALLY AT TEMPERATURES.
Figure 5. Open-Loop Gain Linearity
Figure 2. Typical Low-Frequency Noise Test Circuit
1
8
7 6
OP77
RL = 2k⍀
10Hz FILTER)
VO
25,000
INPUT REFERRED NOISE =
2
NOTES
1. GAIN NOT CONSTANT. CAUSES NONLINEAR ERRORS.
2. AVO SPEC IS ONLY PART OF THE SOLUTION.
3.3k⍀
6
OP77
–
+10V
RL
2.5M⍀
100⍀
0V
OUTPUT
4
Actual open-loop voltage gain can vary greatly at various output
voltages. All automated testers use endpoint testing and therefore
only show the average gain. This causes errors in high closedloop gain circuits. Since this is so difficult for manufacturers to
test, users should make their own evaluation. This simple test
circuit makes it easy. An ideal op amp would show a horizontal
scope trace.
V–
Figure 3. Optional Offset Nulling Circuit
VY
100k⍀
+18V
+
10␮F
*
10⍀
–10V
0V
+10V
0.1␮F
10k⍀
2
7
3
OP77
10k⍀
6
4
10⍀
10␮F *
VX
0.1␮F
AVO ~ 650V/mV
+
RL = 2k⍀
–18V
* 1 PER BOARD
Figure 4. Burn-In Circuit
Figure 6. Output Gain Linearity Trace
This is the output gain linearity trace for the new OP77. The
output trace is virtually horizontal at all points, assuring extremely
high gain accuracy. The average open-loop gain is truly impressive—approximately 10,000,000.
–10–
REV. C
OP77
APPLICATIONS INFORMATION
Bilateral Current Source
R3
R2
1k⍀
1M⍀
+15V
0.1␮F
VIN
R1
2
100k⍀
R2
R1
2
1k⍀
7
6
IOUT < 15mA
100k⍀
OP77E
R3
OP77
3
R5
10⍀
6
3
4
1k⍀
R4
0.1␮F
990⍀
R4
1M⍀
Figure 9. Basic Current Source
–15V
R3
+15V
Figure 7. Precision High-Gain Differential Amplifier
VIN
The high gain, gain linearity, CMRR, and low TCVos of the
OP77 make it possible to obtain performance not previously
available in single-stage very high-gain amplifier applications.
R1
R2
2
2N2222
OP77
6
3
2N2907
R5
R4
For best CMR,
R1
R3
must equal
. In this example,
R2
R4
TYPE
AMOUNT
COMMON-MODE VOLTAGE
GAIN LINEARITY, WORST CASE
TCVOS
TCI OS
0.01%/V
0.02%
0.003%/∞C
0.008%/∞C
Figure 10. 100 mA Current Source
Ê R4
ˆ
R5 Á
+ 1˜
Ë R2
¯
Note that ZO =
R5 + R 4 R3
R2
R1
and that for ZO to be infinite,
RF
+15V
0.1␮F
7
6
OP77
100⍀
OUTPUT
3
4
0.1␮F
CLOAD
–15V
Figure 8. Isolating Large Capacitive Loads
This circuit reduces maximum slew-rate but allows driving
capacitive loads of any size without instability. Because the boon
resistor is inside the feedback loop, its effect on output impedance is reduced to insignificance by the high open-loop gain
of the OP77.
REV. C
)
GIVEN R3 = R4 ⴙ R5, R1 = R2
10pF
2
(
R3
R1 – R5
These current sources will supply both positive and negative
current into a grounded load.
Table I. Maximum Errors
RS
IOUT < 100mA
IOUT = VIN
with a 10 mV differential signal, the maximum errors are as listed
in Table I.
INPUT
–15V
–11–
OP77
In these circuits, OP77’s high gain, high CMRR, and low TCVOS
ensure high accuracy.
R5 + R 4
R3
must =
R1
R2
Precision Current Sinks
R1
2mA
V+
1.8k⍀
15V
RL
IO
VIN
OP77
IO =
3
VIN
R1
VIN > OV
200⍀
IRF520
2
7
OP77
6
4
1N4579A
6.4V ⴞ5%
ⴞ5ppm/ⴗC
FULL SCALE OF 1V,
IO = 1A/V
EO = 10V
R2
3.6k⍀
D1
AVCL 1.6
R3
6.4k⍀
R1
1⍀
1W
Figure 13. High Stability Voltage Reference
Figure 11. Positive Current Sink
This simple bootstrapped voltage reference provides a precise 10 V
virtually independent of changes in power supply voltage, ambient temperature and output loading. Correct Zener operating
current of exactly 2 mA is maintained by R1, a selected 5 ppm/∞C
resistor, connected to the regulated output. Accuracy is primarily determined by three factors: the 5 ppm/∞C temperature
coefficient of D1, 1 ppm/∞C ratio tracking of R2 and R3, and
operational amplifier VOS errors.
R1
200⍀
IRF520
OP77
VIN
IO
RL
IO =
VIN
VOs errors, amplified by 1.6 (AVCL), appear at the output and
can be significant with most monolithic amplifiers. For example,
an ordinary amplifier with TCVOS of 5 mV/∞C contributes 0.8 ppm/
∞C of output error while the OP77, with TCVOS of 0.3 mV/∞C,
contributes but 0.05 ppm/∞C of output error, thus effectively
eliminating TCVOS as an error consideration.
R1
VIN > OV
V–
Figure 12. Positive Current Source
The high gain and low TCVOS assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always
These simple high-current sinks require the load to float between
the power supply and the sink.
1k⍀
1k⍀
+15V
+15V
0.1␮F
C1
30pF
0.1␮F
D1
1N4148
2
2
7
D2
OP77E
6
VIN
3
OP77E
7
6
4
0.1␮F
2N4393
4
VOUT
0 < VOUT < 10V
3
R3
2k⍀
0.1␮F
–15V
–15V
Figure 14. Precision Absolute Value Amplifier
The high gain and low TCVOS assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always
appears as a common-mode signal to the op amps. The OP77E
CMRR of 1 ␮V/V assures errors of less than 2 ppm.
–12–
REV. C
OP77
15V
+
10␮F
2
2
2
REF-01
REF-01
VO 6
4
REF-01
VO 6
VO 6
OP77
100⍀
4
4
VOUT
100⍀
100⍀
0.1␮F
Figure 15. Low Noise Precision Reference
This circuit relies upon OP77’s low TCVOS and noise combined
with very high CMRR to provide precision buffering of the
averaged REF01 voltage outputs.
CH must be of polystyrene, Teflon*, or polyethylene to minimize
dielectric absorption and leakage. The droop rate is determined
by the size of CH and the bias current of the AD820.
*Teflon is a registered trademark of the Dupont Company
1k⍀
15V
0.1␮F
1N4148
15V
0.1␮F
2
VIN
1k⍀
7
6
3 OP77
4
0.1␮F
2N930
2
1k⍀
3
7
AD820
6
4 0.1␮F
CH
–15V
RESET
–15V
Figure 16. Precision Positive Peak Detector
REV. C
–13–
VOUT
OP77
+15V
CC
0.1␮F
RF
100k⍀
2
+15V
VIN
VO
0.1␮F
VTH
RS
TRIM 5
2
7
1k⍀
OP77
R1
VIN
2k⍀
6
D1
1N4148
RC
RA
6
50k⍀
REF-02
VOUT
3
TEMP
4
1.5k⍀
3
Rb1 OP77
0.1␮F
GND
0.1␮F
VOUT
4
Rbp
–15V
–15V
Figure 17. Precision Threshold Detector/Amplifier
When VIN < VTH, amplifier output swings negative, reverse
biasing diode D1. VOUT = VTH if RL= • when VIN > VTH, the
loop closes,
VOUT = VTH + (VIN
Ê
R ˆ
– VTH ) Á1 + F ˜
RS ¯
Ë
CC is selected to smooth the response of the loop.
Figure 18. Precision Temperature Sensor
Table II. Resistor Values
TCVOUT SLOPE (S)
10 mV/∞C
100 mV/∞C 10 mV/∞F
TEMPERATURE
RANGE
–55∞C to
+125∞C
–55∞C to
+125∞C
–67∞F to
+257∞C
OUTPUT VOLTAGE
RANGE
–0.55 V to
+1.25 V
–5.5 V to
+12.5V
–0.67 V to
+2.57V
ZERO-SCALE
0 V @ 0∞C 0 V @ 0∞C
0 V @ 0⬚F
Ra (± 1% Resistor)
9.09 kW
15 kW
7.5 kW
Rb1 (± 1% Resistor)
1.5 kW
1.82 kW
1.21 kW
Rbp (Potentiometer)
200 W
500 W
200 W
Rc (± 1% Resistor)
5.11 kW
84.5 kW
8.25 kW
–14–
REV. C
OP77
OUTLINE DIMENSIONS
8-Lead Ceramic Dip – Glass Hermetic Seal [CERDIP]
8-Lead Metal Can [TO-99]
(Q-8)
(H-08)
Dimensions shown in inches and (millimeters)
Dimensions shown in inches and (millimeters)
0.005 (0.13)
MIN
8
0.055 (1.40)
MAX
REFERENCE PLANE
0.1850 (4.70)
0.1650 (4.19)
5
0.310 (7.87)
0.220 (5.59)
PIN 1
0.023 (0.58)
0.014 (0.36)
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.150 (3.81)
MIN
SEATING
0.070 (1.78) PLANE
0.030 (0.76)
0.0400 (1.02) MAX
15
0
0.0400 (1.02)
0.0100 (0.25)
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCH; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. C
0.1600 (4.06)
0.1400 (3.56)
5
0.405 (10.29) MAX
0.200 (5.08)
0.125 (3.18)
0.1000 (2.54) BSC
4
0.100 (2.54) BSC
0.200 (5.08)
MAX
0.2500 (6.35) MIN
0.0500 (1.27) MAX
0.3700 (9.40)
0.3350 (8.51)
0.3350 (8.51)
0.3050 (7.75)
1
0.5000 (12.70)
MIN
6
4
0.2000
(5.08)
BSC
3
7
2
0.0190 (0.48)
0.0160 (0.41)
0.1000
(2.54)
BSC
0.0210 (0.53)
0.0160 (0.41)
0.0450 (1.14)
0.0270 (0.69)
8
1
0.0340 (0.86)
0.0280 (0.71)
45 BSC
BASE & SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-002AK
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–15–
Revision History
Location
Page
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2 Caption Changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3 Caption Changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edits to Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/02—Data Sheet changed from REV. A to REV. B.
PRINTED IN U.S.A.
Remove 8-Lead SO PIN CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Remove OP77B column from SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Remove OP77B column from ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Remove OP77G column from WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Remove OP77G column from TYPICAL ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
C00320–0–10/02(C)
10/02—Data Sheet changed from REV. B to REV. C.
–16–