DATASHEET
9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Description
Features/Benefits
The 9DBV0841 is an 8-output very low power buffer for
100MHz PCIe Gen1, Gen2 and Gen3 applications with
integrated output terminations providing Zo=100. It can
also be used for 50M or 125M Ethernet Applications via
software frequency selection. The device has 8 output
enables for clock management, and 3 selectable SMBus
addresses.
• Integrated terminations provide 100 differential Zo;
•
•
•
•
Recommended Application
PCIe Gen1-2-3 Buffer
•
Output Features
•
• 8 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF
pairs w/ZO=100
Key Specifications
•
•
•
•
•
•
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Very low additive phase jitter in bypass mode
•
•
•
•
•
•
reduced component count and board space
1.8V operation; minimal power consumption
Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
LP-HCSL differential clock outputs; reduced power and
board space
Programmable Slew rate for each output; allows tuning
for various line lengths
Programmable output amplitude; allows tuning for
various application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system
start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Block Diagram
OE(7:0)#
8
CLK_IN
CLK_IN#
DIF(7:0)
ZDB PLL
SADR_tri
HIBW_BYPM_LOBW#
CKPWRGD_PD#
CONTROL
LOGIC
SDATA_3.3
SCLK_3.3
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
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9DBV0841
REV C 081214
9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
vOE5#
VDD1.8
VDDIO
GND
DIF6
DIF6#
vOE6#
DIF7
DIF7#
vOE7#
VDDIO
^CKPWRGD_PD#
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSADR_tri
^vHIBW_BYPM_LOBW#
FB_DNC
FB_DNC#
VDDR1.8
CLK_IN
CLK_IN#
GNDR
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
9DBV0841
DIF5#
DIF5
vOE4#
DIF4#
DIF4
VDDIO
VDDA1.8
GNDA
vOE3#
DIF3#
DIF3
vOE2#
DIF2#
DIF2
GND
VDDIO
VDD1.8
DIF1#
DIF1
vOE1#
DIF0#
DIF0
vOE0#
VDDIO
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+
Read/Write bit
x
x
x
Power Management Table
SMBus
DIFx
OEx# Pin
True O/P
Comp. O/P
OEx bit
0
X
X
X
Low
Low
1
Running
0
X
Low
Low
1
Running
1
0
Running
Running
1
Running
1
1
Low
Low
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
CKPWRGD_PD#
Power Connections
Pin Number
VDD
VDDIO
GND
13, 21, 31,
39, 47
Description
9
Input
receiver
analog
Digital Power
22, 29, 40
DIF outputs
29
PLL Analog
8
12
30
Off
On1
On1
On1
Frequency Select Table
5
20, 31, 38
PLL
CLK_IN
FSEL
Byte3 [4:3]
00 (Default)
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
2
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
9DBV0841
Byte1 [4:3]
Control
00
01
11
REV C 081214
9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Pin Descriptions
PIN #
1
2
3
4
5
PIN NAME
TYPE
DESCRIPTION
LATCHED
vSADR_tri
Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
^vHIBW_BYPM_LOBW#
IN
See PLL Operating Mode Table for Details.
True clock of differential feedback. The feedback output and feedback input are
FB_DNC
DNC
connected internally on this pin. Do not connect anything to this pin.
Complement clock of differential feedback. The feedback output and feedback
FB_DNC#
DNC
input are connected internally on this pin. Do not connect anything to this pin.
VDDR1.8
PWR
6
7
8
9
10
11
12
13
CLK_IN
CLK_IN#
GNDR
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
VDDIO
IN
IN
GND
GND
IN
I/O
PWR
PWR
14
vOE0#
IN
15
16
DIF0
DIF0#
OUT
OUT
17
vOE1#
IN
18
19
20
21
22
23
24
DIF1
DIF1#
VDD1.8
VDDIO
GND
DIF2
DIF2#
OUT
OUT
PWR
PWR
GND
OUT
OUT
25
vOE2#
IN
26
27
DIF3
DIF3#
OUT
OUT
28
vOE3#
IN
29
30
31
32
33
GNDA
VDDA1.8
VDDIO
DIF4
DIF4#
34
vOE4#
IN
35
36
DIF5
DIF5#
OUT
OUT
37
vOE5#
IN
38
VDD1.8
PWR
GND
PWR
PWR
OUT
OUT
1.8V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
1.8V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominal 1.8V
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
1.8V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 1.8V
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
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9DBV0841
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9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Pin Descriptions (cont.)
39
40
41
42
VDDIO
GND
DIF6
DIF6#
PWR
GND
OUT
OUT
43
vOE6#
IN
44
45
DIF7
DIF7#
OUT
OUT
46
vOE7#
IN
47
VDDIO
PWR
48
^CKPWRGD_PD#
IN
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
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9DBV0841
REV C 081214
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8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100ohm
2pF
Rs
2pF
Device
Driving LVDS
3.3V
Driving LVDS
Cc
R7a
R7b
R8a
R8b
Rs
Zo
Cc
Rs
Device
LVDS Clock
input
Driving LVDS inputs with the 9DBV0841
Value
Receiver has Receiver does not
Component
termination
have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
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9DBV0841
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9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0841. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
1.8V Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
VDDxx
VIN
VIHSMB
Ts
Tj
ESD prot
Applies to VDD, VDDA and VDDIO
MIN
-0.5
-0.5
TYP
SMBus clock and data pins
-65
Human Body Model
MAX
2.5
VDD+0.5V
3.6V
150
125
2000
UNITS NOTES
V
V
V
°C
°C
V
1,2
1, 3
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
Electrical Characteristics–Clock Input Parameters
TA = TCOM or TIND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
Input High Voltage - DIF_IN
VIHDIF
Input Low Voltage - DIF_IN
VILDIF
Input Common Mode
Voltage - DIF_IN
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
CONDITIONS
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
MIN
TYP
MAX
UNITS NOTES
600
800
1150
mV
1
VSS - 300
0
300
mV
1,3
VCOM
Common Mode Input Voltage
300
725
mV
1
VSWING
dv/dt
IIN
dtin
J DIFIn
Peak to Peak value (VIHDIF - VILDIF)
Measured differentially
VIN = VDD , VIN = GND
Measurement from differential wavefrom
Differential Measurement
300
0.4
-5
45
0
1450
mV
V/ns
uA
%
ps
1
1,2
1
1
1
0.01
5
55
150
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
3
The device can be driven from a single ended clock by driving the true clock and biasing the complement clock input to the VBIAS, where VBIAS
is (VIHHIGH - VIHLOW)/2
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
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9DBV0841
REV C 081214
9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TCOM or TIND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
1.8V Supply Voltage
VDD
IO Supply Voltage
Ambient Operating
Temperature
Input High Voltage
Input Mid Voltage
Input Low Voltage
Schmitt Trigger Postive
Going Threshold Voltage
Schmitt Trigger Negative
Going Threshold Voltage
Hysteresis Voltage
Output High Voltage
Outputt Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
1.7
1.8
1.9
V
1
VDDIO
TCOM
TIND
VIH
VIM
VIL
Supply voltage for core, analog and LVCMOS
outputs
Supply voltage for differential Low Power Outputs
Commmercial range
Industrial range
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
0.9975
0
-40
0.75 VDD
0.4 VDD
-0.3
1.05
25
25
1.9
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
V
°C
°C
V
V
V
1
1
1
1
1
1
VT+
Single-ended inputs, where indicated
0.4 VDD
0.7 VDD
V
1
VT-
Single-ended inputs, where indicated
0.1 VDD
0.4 VDD
V
1
VH
VIH
VIL
I IN
VT+ - VTSingle-ended outputs, except SMBus. I OH = -2mA
Single-ended outputs, except SMBus. IOL = -2mA
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Bypass mode
100MHz PLL mode
125MHz PLL mode
156.25MHz PLL mode
0.1 VDD
VDD-0.45
0.4 VDD
1
1
1
1
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
1.5
1.5
I INP
Fibyp
Fipll100
Fipll125
Fipll156
Lpin
CIN
CINDIF_IN
COUT
Clk Stabilization
TSTAB
Input SS Modulation
Frequency
fMODIN
OE# Latency
tLATOE#
Tdrive_PD#
t DRVPD
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
t RSMB
tFSMB
f MAXSMB
-5
0.45
5
V
V
V
uA
-200
200
uA
1
200
110
137.5
171.875
7
5
2.7
6
MHz
MHz
MHz
MHz
nH
pF
pF
pF
2
2
2
2
1
1
1,6
1
0.600
1
ms
1,2
31.500
33
kHz
1
3
clocks
1,3
300
us
1,3
5
5
0.8
3.6
0.4
1,2
1,2
1,4
1,5
1
1
1
1
1
1,7
1
60
75
93.75
30
1
100.00
125.00
156.25
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
3.6
1000
300
ns
ns
V
V
V
mA
V
ns
ns
Maximum SMBus operating frequency
400
kHz
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
2.1
4
1.7
4
For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB
For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB
6
DIF_IN input
5
7
The differential input clock must be running for the SMBus to be active
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
7
9DBV0841
REV C 081214
9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
TA = TCOM or TIND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
Slew rate
Trf
Slew rate matching
ΔTrf
Voltage High
VHIGH
CONDITIONS
MIN
TYP
Scope averaging on 3.0V/ns setting
Scope averaging on 2.0V/ns setting
Slew rate matching, Scope averaging on
1.1
1.9
2
3
7
3
4
20
660
774
850
Voltage Low
VLOW
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Vcross_abs
Δ-Vcross
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
Scope averaging off
MAX UNITS NOTES
V/ns
V/ns
%
1, 2, 3
1, 2, 3
1, 2, 4
1,7
mV
-150
18
150
821
-15
1536
414
13
1150
-300
300
250
550
140
1,7
1
1
1,2,7
1,5,7
1, 6
mV
mV
mV
mV
1
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform
2
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.
7
At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TCOM or TIND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Operating Supply Current
Powerdown Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
I DDAOP
VDDA+VDDR, PLL Mode, @100MHz
11
15
mA
1
IDDOP
VDD1.8, All outputs active @100MHz
8
10
mA
1
IDDIOOP
VDDIO, All outputs active @100MHz
28
35
mA
1
I DDAPD
VDDA+VDDR, PLL Mode, @100MHz
0.7
1
mA
1,2
IDDPD
VDD1.8, Outputs Low/Low
VDDIO,Outputs Low/Low
1.2
0.005
2
0.01
mA
mA
1, 2
1, 2
I DDIODZ
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input clock stopped.
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
8
9DBV0841
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9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL
Characterisitics
TA = TCOM or TIND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
2
1
45
2.7
1.4
1.2
50.1
4
2
2
55
MHz
MHz
dB
%
1,5
1,5
1
1
PLL Bandwidth
BW
PLL Jitter Peaking
Duty Cycle
tJPEAK
tDC
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
Measured differentially, PLL Mode
Duty Cycle Distortion
tDCD
Measured differentially, Bypass Mode @100MHz
-1
0
1
%
1,3
Jitter, Cycle to cycle
tjcyc-cyc
Bypass Mode, VT = 50%
PLL Mode VT = 50%
VT = 50%
PLL mode
Additive Jitter in Bypass Mode
3000
0
Skew, Output to Output
tpdBYP
t pdPLL
t sk3
3600
92
28
16
0.1
4500
200
50
50
25
ps
ps
ps
ps
ps
1
1,4
1,4
1,2
1,2
Skew, Input to Output
1
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform
3
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4
All outputs at default slew rate
5
The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
2
Electrical Characteristics–Phase Jitter Parameters
TA = TCOM or TIND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
tjphPCIeG1
tjphPCIeG2
Phase Jitter, PLL Mode
tjphPCIeG3
tjphSGMII
tjphPCIeG1
Additive Phase Jitter,
Bypass Mode
tjphPCIeG2
tjphPCIeG3
tjphSGMII
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
125MHz, 1.5MHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
MIN
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
INDUSTRY
LIMIT
UNITS Notes
86
ps (p-p) 1,2,3
ps
3
1,2
(rms)
ps
3.1
1,2
(rms)
ps
1
1,2,4
(rms)
ps
NA
1,6
(rms)
TYP
34
MAX
52
0.9
1.4
2.2
2.5
0.5
0.6
1.9
2
0.6
5
N/A
0.1
0.3
N/A
0.05
0.1
N/A
0.05
0.1
N/A
0.15
0.3
N/A
ps (p-p) 1,2,3
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
1,2,5
1,2,5
1,2,4,
5
1,6
1
Applies to all outputs, with device driven by 9FG432AKLF or equivalent.
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Subject to final radification by PCI SIG.
5
For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
6
Applies to all differential outputs
2
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
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General SMBus Serial Interface Information
How to Write
How to Read
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
IDT (Slave/Receiver)
starT bit
Slave Address
WRite
ACK
WR
WRite
ACK
Beginning Byte = N
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
RT
Slave Address
Beginning Byte N
ACK
X Byte
O
O
O
Repeat starT
RD
ReaD
ACK
O
Data Byte Count=X
O
O
ACK
ACK
ACK
Beginning Byte N
Byte N + X - 1
stoP bit
O
O
O
O
O
Note: SMBus Address is Latched on SADR pin.
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
O
X Byte
P
Byte N + X - 1
N
Not acknowledge
P
stoP bit
10
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SMBus Table: Output Enable Register 1
Byte 0
Name
Control Function
Type
0
DIF OE7
Output Enable
RW
Low/Low
Bit 7
DIF OE6
Output Enable
RW
Low/Low
Bit 6
DIF OE5
Output Enable
RW
Low/Low
Bit 5
DIF OE4
Output Enable
RW
Low/Low
Bit 4
DIF OE3
Output Enable
RW
Low/Low
Bit 3
DIF OE2
Output Enable
RW
Low/Low
Bit 2
DIF OE1
Output Enable
RW
Low/Low
Bit 1
DIF OE0
Output Enable
RW
Low/Low
Bit 0
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Name
Control Function
Type
PLLMODERB1
PLL Mode Readback Bit 1
Bit 7
R
PLLMODERB0
PLL Mode Readback Bit 0
Bit 6
R
Bit 5
PLLMODE_SWCNTRL
Enable SW control of PLL Mode RW
PLLMODE1
PLL Mode Control Bit 1
Bit 4
PLLMODE0
PLL Mode Control Bit 0
Bit 3
Reserved
Bit 2
AMPLITUDE 1
Bit 1
Controls Output Amplitude
AMPLITUDE 0
Bit 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
SLEWRATESEL DIF7
Adjust Slew Rate of DIF7
Bit 7
SLEWRATESEL DIF6
Adjust Slew Rate of DIF6
Bit 6
SLEWRATESEL DIF5
Adjust Slew Rate of DIF5
Bit 5
SLEWRATESEL DIF4
Adjust Slew Rate of DIF4
Bit 4
SLEWRATESEL DIF3
Adjust Slew Rate of DIF3
Bit 3
SLEWRATESEL DIF2
Adjust Slew Rate of DIF2
Bit 2
SLEWRATESEL DIF1
Adjust Slew Rate of DIF1
Bit 1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF0
Bit 0
SMBus Table: Frequency Select Control Register
Byte 3
Name
Control Function
Reserved
Bit 7
Reserved
Bit 6
Enable SW selection of
FREQ_SEL_EN
Bit 5
frequency
FSEL1
Freq. Select Bit 1
Bit 4
FSEL0
Freq. Select Bit 0
Bit 3
Reserved
Bit 2
Reserved
Bit 1
SLEWRATESEL FB
Adjust Slew Rate of FB
Bit 0
1. B3[5] must be set to a 1 for these bits to have any effect on the part.
0
1
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Default
1
1
1
1
1
1
1
1
1
Default
Latch
Latch
See PLL Operating Mode Table
Values in B1[7:6]
set PLL Mode
Values in B1[4:3]
set PLL Mode
0
RW 1
RW 1
See PLL Operating Mode Table
RW
RW
00 = 0.6V
10= 0.8V
01 = 0.7V
11 = 0.9V
0
0
1
1
0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
2.0V/ns
2.0V/ns
2.0V/ns
2.0V/ns
2.0V/ns
2.0V/ns
2.0V/ns
2.0V/ns
1
3.0V/ns
3.0V/ns
3.0V/ns
3.0V/ns
3.0V/ns
3.0V/ns
3.0V/ns
3.0V/ns
Default
1
1
1
1
1
1
1
1
Type
0
1
Default
1
1
RW
SW frequency
change disabled
SW frequency
change enabled
RW 1
RW 1
RW
See Frequency Select Table
2.0V/ns
3.0V/ns
0
0
0
1
1
1
Byte 4 is Reserved and reads back 'hFF
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
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SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
RID3
Bit 7
RID2
Bit 6
Revision ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Device Type/Device ID
Byte 6
Name
Device Type1
Bit 7
Device Type0
Bit 6
Device ID5
Bit 5
Device ID4
Bit 4
Device ID3
Bit 3
Device ID2
Bit 2
Device ID1
Bit 1
Device ID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Device Type
Device ID
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Type
RW
RW
RW
RW
RW
0
1
A rev = 0000
0001 = IDT
0
1
00 = FGV, 01 = DBV,
10 = DMV, 11= Reserved
001000 binary or 08 hex
0
Default
0
0
0
0
0
0
0
1
Default
0
1
0
0
1
0
0
0
Default
0
0
0
0
Writing to this register will configure how
1
0
many bytes will be read back, default is
0
= 8 bytes.
0
12
1
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Marking Diagrams
ICS
DBV0841AL
YYWW
COO
LOT
ICS
BV0841AIL
YYWW
COO
LOT
Notes:
1. “LOT” is the lot sequence number.
2. “COO” denotes country of origin.
3. YYWW is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number
5. “L” denotes RoHS compliant package.
6. “I” denotes industrial temperature range device.
Thermal Characteristics
PARAMETER
SYMBOL
CONDITIONS
Thermal Resistance
θJC
θJb
θJA0θ
θJA1
θJA3
θJA5
Junction to Case
Junction to Base
Junction to Air, still air
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
PKG
NDG48
TYP
VALUE
33
2.1
37
30
27
26
UNITS
NOTES
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
1
1
ePad soldered to board
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
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Package Outline and Package Dimensions (NDG48)
Seating Plane
A1
Index Area
N
1
2
(Ref)
ND & NE
Even
(ND-1)x e
(Ref)
L
A3
e
N
Anvil
Singulation
1
(Typ)
If ND & NE
2
are Even
2
E
-- or -Top View
E2
Sawn
Singulation
A
D
0.08 C
E2
(NE-1)x e
(Ref)
2
(Ref)
ND & NE
Odd
C
Symbol
Millimeters
Min
Max
A
A1
A3
b
e
D x E BASIC
D2 MIN./MAX.
E2 MIN./MAX.
L MIN./MAX.
ND
NE
0.8
1.0
0
0.05
0.20 Reference
0.18
0.3
0.40 BASIC
6.00 x 6.00
3.95
4.25
3.95
4.25
0.30
0.50
12
12
b
e
Thermal Base
D2
2
D2
Ordering Information
Part / Order Number Shipping Packaging
9DBV0841AKLF
Trays
9DBV0841AKLFT
Tape and Reel
9DBV0841AKILF
Trays
9DBV0841AKILFT
Tape and Reel
Package
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History
Rev.
Initiator Issue Date Description
A
RDW
B
RDW
C
RDW
Page #
1. Removed "Differential" from DS title and Recommended Application,
corrected typo's in Description. Updated block diagram to show
integrated terminations.
2. Removed references to 60KOhm pulldown under pinout.
3. Updated "Phase Jitter Parameters" table by adding "Industry Limit"
column and updated all Electrical Tables with characterization data.
1,2,68/13/2012 4. Updated Byte3[0] to be consistent with Byte 2. Updated Byte6[7:6]
9,11,13,14
definition.
5. Updated Mark spec with correct part revision (A) and added thermal
data to page 13.
6. Added NDG48 to "Package Outline and Package Dimensions" on page
14 and updated Ordering information to correct part revision (A rev).
7. Move to final
1. Changed VIH min. from 0.65*VDD to 0.75*VDD
2. Changed VIL max. from 0.35*VDD to 0.25*VDD
7
2/18/2013
3. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to
0.6*VDD.
8/12/2014 Changed package designator from "MLF" to "VFQFPN"
Various
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