®
PCM1725
PCM
172
5
Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
16 Bits, 96kHz Sampling
TM
FEATURES
DESCRIPTION
● COMPLETE STEREO DAC: Includes Digital
Filter and Output Amp
The PCM1725 is a complete low cost stereo audio
digital-to-analog converter (DAC), operating off of a
256fS or 384fS system clock. The DAC contains a 3rdorder ∆Σ modulator, a digital interpolation filter, and
an analog output amplifier. The PCM1725 accepts
16-bit input data in either normal or I2S formats.
● DYNAMIC RANGE: 95dB
● MULTIPLE SAMPLING FREQUENCIES:
16kHz to 96kHz
● 8X OVERSAMPLING DIGITAL FILTER
● SYSTEM CLOCK: 256fS / 384fS
● NORMAL OR I2S DATA INPUT FORMATS
● SMALL 14-PIN SOIC PACKAGE
The digital filter performs an 8X interpolation function
and includes de-emphasis at 44.1kHz. The PCM1725
can accept digital audio sampling frequencies from
16kHz to 96kHz, always at 8X oversampling.
The PCM1725 is ideal for low-cost, CD-quality consumer audio applications.
Multi-level
Delta-Sigma
Modulator
BCKIN
LRCIN
DIN
Serial
Input
I/F
Low-pass
Filter
8X Oversampling
Digital Filter
VOUTL
CAP
Multi-level
Delta-Sigma
Modulator
FORMAT
DAC
DAC
Low-pass
Filter
VOUTR
Mode
Control
I/F
DM
Power Supply
256fS/384fS
VCC AGND VDD DGND
SCKI
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1997 Burr-Brown Corporation
PDS-1373A
Printed in U.S.A. April, 1997
SPECIFICATIONS
All specifications at +25°C, +VCC = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted.
PCM1725
PARAMETER
CONDITIONS
RESOLUTION
DATA FORMAT
Audio Data Format
Data Bit Length
Sampling Frequency (fS)
Internal System Clock Frequency
THD+N at FS (0dB)
THD+N at –60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Output Voltage
Center Voltage
Load Impedance
16
MAX
UNITS
16
Bits
96
kHz
0.8
±0.8
VDC
VDC
µA
256fS /384fS
TTL
2.0
f = 991kHz
A-weighted
A-weighted
90
90
88
VOUT = VCC/2 at BPZ
Full Scale (0dB)
AC Load
–83
–32
95
97
95
–78
dB
dB
dB
dB
dB
±1.0
±1.0
±20
±5.0
±5.0
±50
% of FSR
% of FSR
mV
Vp-p
VDC
kΩ
0.62 x VCC
VCC/2
10
DIGITAL FILTER PERFORMANCE
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
INTERNAL ANALOG FILTER
–3dB Bandwidth
Passband Response
TYP
Standard /I2S
16
DIGITAL INPUT/OUTPUT
Logic Level
Input Logic Level
VIH(1)
VIL(1)
Input Logic Current: IIN(1)
DYNAMIC PERFORMANCE(2)
MIN
0.445
11.125/fS
fS
fS
dB
dB
sec
100
–0.16
kHz
dB
0.555
±0.17
–35
f = 20kHz
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current
Power Dissipation
4.5
TEMPERATURE RANGE
Operation
Storage
–25
–55
5
13
65
5.5
18
90
VDC
mA
mW
+85
+100
°C
°C
NOTES: (1) Pins 1, 2, 3, 12, 13: LRCIN, DIN, BCKIN, DM, FORMAT (Schmitt Trigger Input); Pin 14: SCKI. (2) Dynamic performance specs are tested with 20kHz
low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
PCM1725
2
PIN CONFIGURATION
PIN ASSIGNMENTS
TOP VIEW
SOIC
PIN
NAME
I/O
FUNCTION
1(1)
LRCIN
IN
Sample Rate Clock Input
2(1)
DIN
IN
Audio Data Input
3(1)
BCKIN
IN
Bit Clock Input for Audio Data.
LRCIN
1
14
SCKI
4
NC
—
No Connection
DIN
2
13
FORMAT
5
CAP
—
Common Pin of Analog Output Amp
BCKIN
3
12
DM
6
VOUTR
OUT
7
GND
—
Ground
Power Supply
NC
4
CAP
Right-Channel Analog Output
11
NC
8
VCC
—
5
10
NC
9
VOUTL
OUT
VOUTR
6
9
VOUTL
10
NC
—
GND
7
8
VCC
11
NC
—
No Connection
12(2)
DM
IN
De-emphasis Control
HIGH: De-emphasis ON
LOW: De-emphasis OFF
13(2) FORMAT
—
Audio Data Format Select
HIGH: I2S Data Format
LOW: Standard Data Format
14
IN
System Clock Input (256fS or 384fS)
PCM1725
PACKAGE INFORMATION
PRODUCT
PACKAGE
PACKAGE DRAWING
NUMBER(1)
PCM1725U
14 Pin SOIC
235
SCKI
Left-Channel Analog Output
No Connection
NOTES: (1) Schmitt Trigger input. (2) Schmitt Trigger input with internal
pull-up.
ELECTROSTATIC
DISCHARGE SENSITIVITY
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ....................................................................... +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V)
Power Dissipation .......................................................................... 300mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) .................................................. +260°C
Thermal Resistance, θJA .............................................................. +70°C/W
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
®
3
PCM1725
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VCC = +5V, fS = 44.1kHz, SYSCLK = 256f S, unless otherwise noted.
DYNAMIC PERFORMANCE
SNR, DYNAMIC RANGE vs TEMPERATURE
3.1
3.0
2.9
0.006
2.8
0.005
2.7
–60dB
0.003
2.6
0.002
2.5
0.001
2.4
0
25
50
75
85
97
97
96
96
95
95
94
93
–25
2.3
0
–25
100
93
0
25
75
85
100
SNR, DYNAMIC RANGE vs POWER SUPPLY
0.009
3.2
0.008
3.1
99
99
0.006
2.9
0.005
2.8
0.004
2.7
0.003
2.6
0.002
2.5
–60dB
SNR (dB)
3.0
0dB
THD+N at –60dB (%)
98
97
97
96
96
95
95
Dynamic Range
94
0.001
98
SNR
94
2.4
0
2.3
4.5
4.75
5.0
5.25
93
5.5
93
4.5
4.75
5.0
VCC (V)
SNR, DYNAMIC RANGE vs SAMPLING RATE
THD+N vs SAMPLING RATE
98
5.2
98
97
0.012
4.2
3.7
0dB
0.008
3.2
0.006
2.7
–60dB
0.004
88.2
96
95
95
94
94
93
93
Dynamic Range
92
91
90
90
89
89
88
48
88.2
Sampling Rate (kHz)
®
4
92
91
44.1
96
Sampling Rate (kHz)
PCM1725
97
SNR
96
88
2.2
48
SNR (dB)
4.7
THD+N AT –60dB (%)
0.014
44.1
5.5
VCC (V)
0.016
0.01
5.25
96
Dynamic Range (dB)
THD+N at 0dB (%)
50
Temperature (°C)
THD+N vs POWER SUPPLY
THD+N at 0dB (%)
94
Dynamic Range
Temperature (°C)
0.007
98
SNR
Dynamic Range (dB)
0.004
99
98
SNR (dB)
0dB
0.007
THD+N at –60dB (%)
0.008
THD+N at 0dB (%)
99
3.2
Dynamic Range (dB)
THD+N vs TEMPERATURE
0.009
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted.
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTIC
PASSBAND RIPPLE CHARACTERISTIC
0
–20
–0.2
–40
–0.4
dB
dB
0
–60
–0.6
–80
–0.8
–100
–1
0 0.4536fS
1.3605fS
2.2675fS
3.1745fS
4.0815fS
0
0.1134fS
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
0.3402fS
0.4535fS
DE-EMPHASIS FREQUENCY ERROR (44.1kHz)
0
0.6
–2
0.4
–4
0.2
Error (dB)
Level (dB)
0.2268fS
Frequency (Hz)
Frequency (Hz)
–6
0.0
–8
–0.2
–10
–0.4
–12
–0.6
0
5
10
15
20
25
0
Frequency (kHz)
4999.8375
9999.675
14999.5125
19999.35
Frequency (kHz)
®
5
PCM1725
1/fs
L_ch
R_ch
LRCIN (pin 4)
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5)
14 15 16
1
2
3
MSB
14
15 16
1
2
LSB
3
MSB
14
15 16
LSB
FIGURE 1. “Normal” Data Input Timing.
1/fs
L_ch
LRCIN (pin 4)
R_ch
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5)
1
2
14
3
MSB
15 16
1
2
LSB
3
MSB
14
1
15 16
2
LSB
FIGURE 2. “I2S” Data Input Timing.
LRCKIN
1.4V
tBCH
tBCL
tLB
BCKIN
1.4V
tBL
tBCY
1.4V
DIN
tDS
tDH
BCKIN Pulse Cycle Time
: tBCY
: 100ns (min)
BCKIN Pulse Width High
: tBCH
: 50ns (min)
BCKIN Pulse Width Low
: tBCL
: 50ns (min)
BCKIN Rising Edge to LRCIN Edge : tBL
: 30ns (min)
LRCIN Edge to BCKIN Rising Edge : tLB
: 30ns (min)
DIN Set-up Time
: tDS
: 30ns (min)
DIN Hold Time
: tDH
: 30ns (min)
FIGURE 3. Audio Data Input Timing.
SYSTEM CLOCK
The system clock for PCM1725 must be either 256fS or
384fS, where fS is the audio sampling frequency (LRCIN),
typically 32kHz, 44.1kHz or 48kHz. The system clock is
used to operate the digital filter and the noise shaper. The
system clock input (SCKI) is at pin 2. Timing conditions for
SCKI are shown in Figure 4.
tSCKIH
2.0V
SCKI
0.8V
tSCKIL
System Clock Pulse Width High
System Clock Pulse Width Low
tSCKIH
tSCKIL
13ns (min)
13ns (min)
FIGURE 4. System Clock Timing Requirements.
®
PCM1725
6
PCM1725 has a system clock detection circuit which automatically detects the frequency, either 256fS or 384fS. The
system clock should be synchronized with LRCIN (pin 3),
but PCM1725 can compensate for phase differences. If the
phase difference between LRCIN and system clock is greater
than ±6 bit clocks (BCKIN), the synchronization is performed automatically. The analog outputs are forced to a
bipolar zero state (VCC/2) during the synchronization function. Table I shows the typical system clock frequency
inputs for the PCM1725.
FORMAT
0
1
TABLE II. Input Format Selection.
RESET
PCM1725 has an internal power-on reset circuit. The internal
power-on reset initializes (resets) when the supply voltage
VCC > 2.2V (typ). The power-on reset has an initialization
period equal to 1024 system clock periods after VCC > 2.2V.
During the initialization period, the outputs of the DAC are
invalid, and the analog outputs are forced to VCC/2. Figure 6
illustrates the power-on reset and reset-pin reset timing.
SYSTEM CLOCK
FREQUENCY (MHz)
SAMPLING
RATE (LRCIN)
32kHz
44.1kHz
48kHz
256fS
384fS
8.192
11.2896
12.288
12.288
16.9340
18.432
Normal Format (MSB-first, right-justified)
I2S Format (Philips serial data protocol)
DE-EMPHASIS CONTROL
Pin 12 (DM) enables PCM1725’s de-emphasis function. Deemphasis operates only at 44.1kHz.
TABLE I. System Clock Frequencies vs Sampling Rate.
TYPICAL CONNECTION DIAGRAM
DM
0
1
Figure 5 illustrates the typical connection diagram for
PCM1725 used in a stand-alone application.
De-emphasis ON (44.1kHz)
De-emphasis OFF
TABLE III. De-emphasis Control Selection.
INPUT DATA FORMAT
PCM1725 can accept input data in either normal (MSB-first,
right-justified) or I2S formats. When pin 13 (FORMAT) is
LOW, normal data format is selected; a HIGH on pin 13
selects I2S format.
+5V Analog
2
3
PCM
Audio Data
Processor
1
7
8
GND
VCC
DIN
VOUTL
BCKIN
CAP
5
+
LRCIN
PCM1725
14
9
SCKI
256fS/384fS CLK
VOUTR
FORMAT
DM
6
Post
LPF
Lch Analog Out
Post
LPF
Rch Analog Out
10µF
13
12
Mode Control
FIGURE 5. Typical Connection Diagram.
VCC
2.6V
2.2V
1.8V
Reset
Reset Removal
Internal Reset
1024 system (= XTI) clocks
XTI Clock
FIGURE 6. Internal Power-On Reset Timing.
®
7
PCM1725
APPLICATION
CONSIDERATIONS
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
DELAY TIME
1.0
There is a finite delay time in delta-sigma converters. In A/D
converters, this is commonly referred to as latency. For a
delta-sigma D/A converter, delay time is determined by the
order number of the FIR filter stage, and the chosen sampling
rate. The following equation expresses the delay time of
PCM1725:
dB
0.5
0
TD = 11.125 x 1/fS
–0.5
For fS = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs
Applications using data from a disc or tape source, such as
CD audio, CD-Interactive, Video CD, DAT, Minidisc,
etc., generally are not affected by delay time. For some
professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms.
–1.0
20
100
1k
Frequency (Hz)
10k
24k
FIGURE 7. Low Pass Filter Frequency Response.
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1725 using a 20kHz low pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low pass filter removes out of band
noise. Although it is not audible, it may affect dynamic
specification numbers.
dB
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
The performance of the internal low pass filter from DC to
24kHz is shown in Figure 7. The higher frequency rolloff of
the filter is shown in Figure 8. If the user’s application has
the PCM1725 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 9. For some applications, a
passive RC filter or 2nd-order filter may be adequate.
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
BYPASSING POWER SUPPLIES
The power supplies should be bypassed as close as possible
to the unit. It is also recommended to include a 0.1µF ceramic
capacitor in parallel with the 10µF tantalum bypass capacitor.
FIGURE 8. Low Pass Filter Wideband Frequency Response.
GAIN vs FREQUENCY
6
90
+
10kΩ
VSIN
10kΩ
680pF
OPA134
10kΩ
–14
0
–34
–90
–54
–180
Phase
100pF
–
–74
–270
–94
–360
100
FIGURE 9. 3rd-Order LPF.
®
PCM1725
8
1k
10k
Frequency (Hz)
100k
1M
Phase (°)
1500pF
Gain (dB)
Gain
+
In
+
8fS
18-Bit
+
Z–1
+
+
–
+
Z–1
Z–1
–
+
+
5-level Quantizer
+
4
3
Out
48fS (384fS)
64fS (256fS)
2
1
0
FIGURE 10. 5-Level ∆Σ Modulator Block Diagram.
THEORY OF OPERATION
3rd-ORDER ∆Σ MODULATOR
The delta-sigma section of PCM1725 is based on a 5-level
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level deltasigma format. A block diagram of the 5-level delta-sigma
modulator is shown in Figure 10. This 5-level delta-sigma
modulator has the advantage of stability and clock jitter over
the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8X interpolation filter is 96fS for a
384fS system clock, and 64fS for a 256fS system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 11.
20
0
Gain (–dB)
–20
–40
–60
–80
–100
–120
–140
–160
0
5
10
15
20
25
Frequency (kHz)
FIGURE 11. Quantization Noise Spectrum.
®
9
PCM1725