IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 5, MAY 1999
489
Modeling of CMOS Digital-to-Analog
Converters for Telecommunication
J. Jacob Wikner and Nianxiong Tan, Senior Member, IEEE
Abstract— This paper gives an overview of some of the
effects caused by circuit mismatch and parasitics in binary
weighted digital-to-analog (DAC) converters, and, as a special
case, a current-steering CMOS converter. Matlab is used as a
behavior-level simulator. In telecommunications applications, the
frequency-domain parameters are of the greatest importance.
Therefore, the characterization of the device and its performance
is determined by frequency parameters such as the signalto-noise ratio, spurious-free dynamic range, multitone power
ratio, etc. In this paper, we show how these frequency-domain
parameters are affected when mismatch errors and finite output
impedance are applied to a current-steering CMOS DAC. We
discuss how static performance is affected when changing the
size of the errors and fundamental circuit parameters. The
impact of dynamic errors such as glitches, slewing, and bit skew
is discussed. Measurement results from 14-bit DAC’s are also
shown to illustrate the correlation with the modeling.
Index Terms— CMOS, current-steering, digital-to-analog converters, dynamic and static errors, frequency-domain measures,
measurement results, modeling, simulation.
I. INTRODUCTION
I
N HIGH-performance telecommunications applications,
good linearity and low noise are very important. The
digital-to-analog converter (DAC) is a crucial building block,
since it puts the information on the line. A wide frequency
band and high resolution are needed to meet the requirements
on high speed and high accuracy.
The time-domain aspects are very important, but most of
the characterization is done in the frequency domain [1].
We are using parameters such as the spurios-free dynamic
range (SFDR), intermodulation distortion (IMD), signal-tonoise ratio (SNR), multitone power ratio (MTPR), and the
signal-to-noise-and-distortion ratio (SNDR) to characterize the
device.
The characterization can also be divided into static and dynamic properties [1], [2]. The static properties are given by the
settled output values, and are often too optimistic to determine
the true performance of the converter. Dynamic properties are
given by the transition between two states, hence the slewing,
glitches, time skew, etc. In telecommunications applications, it
is mostly the dynamic performance that determines the quality
of the converter. Ad hoc, we can say that the static properties
set the best-case performance. With this modeling, we want to
Manuscript received January 26, 1998; revised December 31, 1998. This
paper was recommended by Associate Editor E. Soenen.
J. J. Wikner is with Microelectronics Research Center (MERC), Ericsson
Components, Link pings Universitet, S-581 83 Link ping, Sweden.
N. Tan is with Globespan Semiconductor, Red Bank, NJ 07701 USA.
Publisher Item Identifier S 1057-7130(99)03797-0.
show the frequency-domain aspects of errors in static values.
Similar discussions have been reported [3]–[5], but none of
them have discussed the true impact of different linearity errors
on the frequency-domain parameters. We also briefly discuss
the impact of dynamic errors.
In this paper, we focus on binary-weighted, current-steering
DAC’s, as presented in Section II. This type of converter uses
a number of weighted current sources, which are switched and
summed at a terminating output resistance. Process variations
and other parasitics will influence the matching between the
current sources. Output impedance is dependent on choice of
transistor sizes, etc.
In Section III, we show how the linearity of the converter is
affected when assuming a finite-output impedance and especially a signal-dependent output impedance of the converter.
The mismatch due to process variations of the individual
current sources is discussed in Section IV. It is shown that
the mismatch errors affect the linearity, and we show how the
SFDR is changing with different sizes of mismatch, since it
is commonly known that a raw binary structure has a limited
performance due to the matching errors.
In Section V, we discuss the dynamic errors, such as nonlinear slewing, bit skew, and glitches. Modeling issues similar
to those presented in Sections III and IV are presented. In
Section VI, we also show measurement results to illustrate the
correlation between the calculated, simulated, and measured
results.
Previous related work has also been published in [6] and
[7]. In [7], a discussion over circuit noise is also given. In this
paper, we show some extensions to these theories as well as
measurement results.
II. CURRENT-STEERING DAC
The use of switched current sources is a straightforward
approach in high-speed CMOS DAC’s, since currents are easy
to weight, sum, and switch. The structure that is studied in this
paper is a binary weighted converter as shown in Fig. 1 and
discussed in [6]–[13].
The switches, , in Fig. 1, are controlled by the digital bits,
, where
is the number of bits. The digital input
,
,
, ,
with
as
number is
the least significant bit
the most significant bit (MSB) and
is high, switch
is closed and the current
(LSB). When
is switched to the output. Binary weighting implies that the
current source controlled by , i.e., the th LSB current source,
is formed by connecting unit current sources in parallel. The
1057–7130/99$10.00  1999 IEEE
490
Fig. 1. An
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 5, MAY 1999
N -bit binary weighted DAC.
Fig. 2. Generalized view of a current source with a nonzero output conductance.
current associated with this bit position will be denoted
(1)
is the output current of a single-unit current source.
where
When considering the static behavior, we only look at time
points where the output signal of the DAC has settled to its
where
is the
final value. At a certain time point
sample time period, and the code at the input is given by
with the corresponding bits
. The output
current is given by
(2)
This notation is simplified by writing
on the input, it will give rise to a signal-dependent gain, i.e.,
distortion. Using (5) and assuming a signal-dependent output
, the current delivered to
conductance of the DAC
the load is
(6)
indicates the DAC’s digital input given by (3) and
is the load resistance. The output conductance
is determined by studying the DAC structure shown in Fig. 1,
and is related to the number of parallel-unit current sources
that are currently switched to the output (determined by the
digital input). The output conductance associated with oneand
unit current source is assumed to be
with the th LSB, we have the corresponding conductance
. The total output conductance
of
the converter is given by
where
(3)
(7)
Combining (2) and (3), we have the simple description
(4)
where is given by (3). We will refer to the product between
the unit output conductance and the load resistance as the
conductance ratio, and denote it as
III. OUTPUT-RESISTANCE VARIATIONS
(8)
The output impedance and the parasitic impedance of interconnections and switches in the converter will strongly
determine the performance [4]. Any nonideal current source
has a finite output resistance and can be modeled as in Fig. 2.
When the different current sources are switched to the output,
the total output impedance is changed. When only static values
is
are considered, the current through the load
We will also use the resistance ratio
given by
(9)
Combining (2) and (6)–(8), we have that the load current can
be written as
(10)
(5)
is the nominal output current from the DAC given
where
is the output conductance,
is
by (2),
is the supply
the signal-independent load resistance, and
voltage. The influence of reactive parts, which influence the
dynamic performance, are neglected in this first discussion.
From (5), it is seen that if the output conductance of the
DAC were constant, there would only be a loss of gain and
an additional offset current in the output signal, which would
not degrade linearity. If the output conductance is dependent
A. SNDR versus Output Resistance
is the difference between the
The error current
discrete-time current (4) and the degraded current (10), i.e.,
(11)
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491
Fig. 3. View of the wanted continuous-time current and the piecewise linear
output current with mismatch error I X , at code X .
1( )
In Fig. 3, we show the situation at code ; the expression in
(11) is compared to the ideal wanted continuous-time current,
given by
(12)
The total error power introduced due to the finite output
resistance may be described by
Fig. 4. Simulated and calculated SNDR versus resistance ratio for 10-, 12-,
and 14-bit DAC’s. To illustrate the similarity with the calculated, a piece of
the curve has been magnified.
Now we can find the SNDR as a function of the output
impedance, hence
SNDR
(19)
(13)
From (13), we identify the quantization noise power
(14)
and the time-averaged power of the error current introduced
by the degraded converter
(15)
Let the input signal be given by sinusoid
(16)
is the dc level of the signal,
is the amplitude
where
is the normalized frequency, and is a
of the sinusoid,
quantization error which is assumed to be white for converters
with a larger number of bits. The ac power of the sinusoid at
the output is given by
(17)
The code-average
average value of
is found by approximating (11) using the
from (16), i.e.,
(18)
In Fig. 4, we show the simulated SNDR of 10-, 12-, and 14. The
bit DAC’s when changing the resistance ratio
SNDR results are compared with the calculated result from
(19), and the formula is well verified. In the simulation, we
,
V, and
A. All
use
signals fed to the converters are full-scale sinusoids.
B. SFDR versus Output Resistance
We want to examine how the errors are distributed in the
frequency domain. The expression within parenthesis in (10)
using (16) as input signal is rewritten as a converging Taylor
series [6], and the SFDR is found to be
SFDR
(20)
is the output resistance for a
where
single-unit current source. For the case with equal amplitude
and dc level, i.e.,
(21)
we have
SFDR
(22)
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 5, MAY 1999
Fig. 5. Output spectrum when applying a full-scale sinusoid on a 14-bit
1:0 1 5:106 .
DAC. The resistance ratio is Rratio
=
When
is large, in dB this is approximately
SFDR
dB
Fig. 6. Simulated and calculated SFDR versus output over load resistance
ratio for 10-, 12-, and 14-bit DAC’s. The curves are saturated since the spurs
are hidden below the quantization noise at high resistance ratios.
derivations in [6], the distortion with respect to the third
harmonic can be found to be
(23)
SFDR
of the signal, we
We see that by decreasing the ac level
get an improvement of the linearity of the circuit. In the special
case with a full-scale sinusoid, i.e.,
(27)
(24)
we get
(25)
SFDR
the SFDR given by (27) will be much
If
larger than the one given in (20). This can be used to relax the
design effort on the sources’ output impedance, if the DAC
should be designed for a fully differential application.
C. Influence of Parasitic Resistance
The result found in (25) is based on the knowledge that the
second harmonic is dominating the distortion [6]. To illustrate
this, we show in Fig. 5 the simulated output spectrum from
a 14-bit DAC when applying a full-scale sinusoid and having
. If
is large,
a resistance ratio of
(25) can be approximated with
SFDR
(26)
From (26), we realize that with a doubling of the load
resistance, the SFDR is decreased by 6 dB. With a maintained
resistance ratio, the linearity will also deteriorate with an
increased nominal number of bits.
In Fig. 6, we show the simulated and calculated SFDR
versus resistance ratio for a 10-, 12-, and 14-bit DAC. At high
ratios, the simulated values are saturated since the spuriouses
are hidden in the noise floor (compare Fig. 4). It is seen that
simulated SFDR follows the mathematical result well.
When using differential signals, the second harmonic will
be cancelled and the third harmonic dominates. Using the
The modeling in the previous sections is rather coarse and
the resistance of internal wires and switches has not been
considered. However, these may be incorporated as well (see
the modified current source in Fig. 7). For bit-position , we
which is associated
also include the parasitic resistance
with the interconnection wires from current sources to the
output and the on resistance of the switches. Using Norton’s
theorem, we may transform the circuit to be similar to the
current source as illustrated in Fig. 2. Using that schematic
view, we will for the th bit have a current source with the
value
(28)
The output conductance
for same bit is given by
(29)
To find the total output current and conductance for the
converter, we have to sum all the contributions from (28) and
WIKNER AND TAN: MODELING OF CMOS DAC’S FOR TELECOMMUNICATION
493
Fig. 8. Mismatch modeling with mismatch error current sources,
1I .
i
IV. CURRENT-SOURCE MISMATCH
Fig. 7. Model of the current source at bit position i with parasitic resistance
Rpar; i from switches and internal wires.
(29)
and
(30)
respectively. Now, we can use (30) with (5) to find the current
delivered to the load
(31)
Due to the sums in (30), this is a rather complex expression.
We will, however, assume that the parasitic resistance roughly
. By expanding the
is equal for all bits, hence
terms in (30) to a Taylor series and assuming that
, we may further approximate the expressions in (30)
with
A current-source mismatch error can be modeled as an
additional current source in parallel with the nominal current
source, as shown in Fig. 8. All individual error sources can be
summed and modeled as one error-current source connected
to the output of the DAC. The ideal output-current signal is
given by (2). Suppose there is an error in the current sources.
(Now, we assume an infinite output impedance of the current
sources). The distorted output current delivered to the \rm load
can be written as the sum of the nominal output
and the error current
current
(36)
is the digital number given by (3). Suppose that in
where
. Then
the th current source there is an error current
the output current is
(37)
where
is given by
(38)
is the relative error current in the th LSB. In the
where
for all different inputs .
static case, we assume that
The total output current can be rewritten as
and
(39)
(32)
Using the approximations in (32) we may rewrite (31) as
(33)
And we may identify a new conductance ratio
(34)
or the resistance ratio
(35)
This new ratio (35) can be used in (19), (20), and (27) to find
the SNDR and SFDR. This will further be discussed in Section
VI, where measurement results are presented.
In reality, mismatch of transistors due to process variations
- or
-mismatch for a
are of stochastic nature. The
CMOS current source can be characterized by its distribution,
transistor sizes, and physical distance [14], [15]. The mismatch
may also depend on other aspects such as, for example, the
gradient of the oxide thickness over the array of current
sources [5], or voltage drops over bias or supply wires [4],
[16]. For a unit current source, we associate the relative error
. Its mean value is
and the standard deviation
. A nonzero mean value will only give rise to a dc gain
is
error in the output and can be neglected in these calculations.
First in this discussion, we assume that the current sources
are uncorrelated. This is a very coarse assumption, and in
reality, transistors close to each other will have highly correlated errors. For the th LSB current source we have a relative
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 5, MAY 1999
error current, , with a mean value
and a standard
, since
unit current sources are
deviation
connected in parallel. With (39), the expectation value of the
output current—with respect to the mismatch error—becomes
(40)
for all . This also implies that the
since
matching error cannot directly be found by using, for example
differential nonlinearity (DNL) or integral nonlinearity (INL),
and we have to find other ways to characterize our device.
A. SNDR Versus Mismatch
Since the mismatch errors are assumed to be uncorrelated,
the expectation value of the squared load current is
Fig. 9. Calculated and simulated SNDR versus mismatch for a 10-, 12-, and
14-bit DAC.
In dB, we have that
(41)
For the mismatch error, we have
(42)
Since
we get
, we have that
. Using (42) in (41),
SNDR
(48)
In Fig. 9, we show the simulated and calculated SNDR versus
mismatch for a 10-, 12-, and 14-bit DAC. The results are
found by taking the average value of 1024 simulations for each
mismatch value. The simulated values match the calculated
ones well.
B. SFDR versus Mismatch
(43)
We can now find the code-averaged squared value for the
expression in (43) (also compare with Fig. 3) and we have
that
We will now examine how the mismatch error power
is distributed in the frequency domain. The Fourier series
for bit
are
coefficients
(49)
(44)
is the average value of the input code, i.e.,
where
the dc value. We have the error power given by
is the period in number of samples. The coefficients
where
, are given by using (39) and (49)
for the total error current
(45)
and we see that by reducing the dc value of the signal, we
also reduce the error power. By using (14), (17), (19), and
(45), we may form the SNDR as
(50)
The power of each tone from (50) is given by
(51)
SNDR
Since all mismatch errors are uncorrelated, we have that the
expectation value of the power of the th tone is
(46)
(52)
With a full-scale sinusoid, we have from (24) that the SNDR
(46) becomes
For a full-scale single-tone sinusoid, the ac power is
SNDR
(47)
(53)
WIKNER AND TAN: MODELING OF CMOS DAC’S FOR TELECOMMUNICATION
495
The harmonic distortion with respect to the th harmonic is
roughly
(54)
For each bit, we have the error given by a pulse wave, and the
Fourier-series coefficients determine the position and power
of harmonics. Now if we assume that the matching error
dominates in the MSB’s, we will principally have pulse-shaped
error signals. The Fourier series coefficients for these squared
waves are given by
if is even
(55)
if is odd
is the period. In the static case,
is larger than
where
We can use the approximation in (55) to rewrite (54) as
Fig. 10. Calculated and simulated SFDR versus mismatch for a 10-, 12-,
and 14-bit DAC.
.
(56)
In dB, we find that
(57)
Thereby, we also find the SFDR for the full-scale signal to be
), i.e.
given by the minimum value of (57) (
SFDR
(58)
In Fig. 10, we show the average simulated and calculated
SFDR for a 10-, 12-, and 14-bit DAC. The value is found by
taking the average from 1024 simulations for each mismatch
value. In Fig. 11, we show the typical output spectrum of
a 14-bit DAC when applying matching errors with standard
%. The SFDR is approximately 83 dBc
deviation
for a full-scale sinusoid input.
C. Impact of Correlated Matching Errors
The weighted current sources are constructed by using a
number of unit current sources in parallel. If all the matching
errors for these unit sources are uncorrelated, we will for
the th bit have a relative matching error with a zero mean
. In reality, the
value and a standard deviation
matching errors of the unit sources are correlated if they are
densely placed close to each other [5], [14]. The mismatch
error for the th unit source associated with the th bit is
. The expectation value of the squared output
denoted
current for bit is
Fig. 11. Output spectrum for a 14-bit DAC with mismatch size approximately 1.5%.
We denote the covariance or correlation between two unit
current sources as
and
(60)
where also can be interpreted as the physical distance. Using
(60) in (59), we get
(61)
where
(59)
. Equation (61) is rewritten as
(62)
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Fig. 12.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 5, MAY 1999
Current source with output conductance and capacitance.
Fig. 13. Typical behavior of glitches and slewing in the output current at a
code transition at the input.
Since
, we have that
at the input will give rise to a glitch and
a step function at the output, where the glitch energy and the
rise time are dependent on the codes. The first-order model
gives the output current through the load [6] to
(63)
and we may identify the standard deviation for relative matching error in the th bit as
(64)
, are positive, the standard deviaIf the correlation factors
may become larger than the one used in the previous
tion
modeling. Naturally, there is a correlation of the matching
error between different bits as well. The correlation is strongly
dependent on the layout style and should be kept as low as
possible to achieve a good linearity [8].
V. DYNAMIC PROPERTIES
We have discussed how the output current is dependent
on variations of static values, hence the value given by the
settled signal after a code transition. Basically, this implies
that the formulae are only valid at low frequencies (and
high oversampling ratios). For higher frequencies, we have
to consider the dynamic properties such as, for example,
glitching, nonlinear slewing, bit skew, etc. We present some
ideas to model these affects in a similar way as was used
for static values. We discuss nonlinear slewing and glitches
associated with bit skew.
(65)
.
where
is the current through the load at the beginning of the codeis the end value,
is the
transition,
is the code-dependent time constant.
sample period, and
We may slightly inaccurately assume that the start and end
values are approximately given by (30), and the time constant
is given by [6]
(66)
If the converter is well designed with respect to the output
impedance, (66) can be approximated with
(67)
The output error in the specific time interval is given by
(68)
The minimum error is found at
, and we have
(69)
Using (33) in (69), we have that
A. Nonlinear Slewing
In general, the output impedance of the current-steering
DAC is varying with the signal. With each unit current source,
a certain output resistance is associated. In the same way, we
. Hence, for the th current source,
include a capacitance,
, and similar to
we will have a capacitance
we have a total output capacitance of
(7), at the code
. In Fig. 12, we show this situation,
where we have included a parasitic capacitance and resistance
and
. As illustrated in Fig. 13, a code transition
(70)
is assumed to be small. From (70), we find that
where
the size of the error is determined by the difference in code
transitions, in some sense the derivative of the signal. We now
see that with a higher clock frequency, is reduced and
is increased. With a lower oversampling ratio, the derivative
is increased.
of the input signal is becoming larger, and
WIKNER AND TAN: MODELING OF CMOS DAC’S FOR TELECOMMUNICATION
497
Simulation of these errors can be fulfilled by simply adding
the minimum error from (70) to the output current. The
similarity between (70) and (33) implies that for a sinusoid
input signal, there will be the same impact on the distribution
as on the error power. Hence, the second harmonic will
dominate [9].
Fig. 14. Modeling of the timing error. The mismatch between the ideal
switching signal (- -) and the actual signal (-) is given by the t(k )’s.
B. Bit Skew and Glitches
As indicated in the previous section, the slewing will distort
the output signal. However, the occurrence of glitches will
further influence the result. The glitches occur due to clock
feedthrough and bit skew, i.e., all bits do not switch exactly at
the sampling point, and hence it is important to have a proper
digital delay for all bits [4], [17], [18]. For example, if the
MSB switches faster than all other bits at the code transition
11
100
00, we may for a short period of time
011
11 at the output, giving a glitch (Fig. 13).
have the code 111
The common way to guarantee a good design is to guarantee
that the glitch energy is kept as low as possible [2], by for
example using segmentation and proper switching schemes
[18].
The slewing is dependent on the change of the input code,
but the glitches are more dependent on the bits changing. A
large glitch will also result in a longer settling time. In Fig. 14,
we show how this skew can be characterized for the th bit.
The errors of switching time are given by the timing errors
. The switching activity of bit is determined by
(71)
Fig. 15. Measured output spectrum for a 14-bit DAC. Sample frequency is
25 MHz and signal frequency 670 kHz. The input signal is 15 dBFS.
In the time domain, the error current caused by time skew
for the th bit is approximately (the rise and fall times
are neglected)
for all bits and a full segmentation, we will have the glitch
current
0
(75)
(72)
where
otherwise.
(73)
Hence, for the th bit, we will have a pulse-shaped error current
(as shaded in Fig. 14). Using (72), the total skew error current
is
Hence, the glitch current will be dependent on the code change,
similar to the slewing discussion. In simulation models, the
result from, for example, (74) and (75) can be used to modify
the initial value as used in (65), and the minimum error (70) is
thereby changed, further reducing linearity. If the time skew
no longer is much smaller than the sample period, the signal
will not settle fast enough, and further degrading the result, as
discussed in the previous sections.
VI. MEASUREMENT RESULTS
(74)
For a full segmentation of the data, the switching activity
would be determined by the signal change or derivative. Now
the situation is more complex, since the bits are determining
the size of the glitches. The time skew may be in the same
order for all bits, but the MSB’s will dominate the result due to
their amplitude. If we assume approximately equal time skew
The chip used in the measurements is a 5-V 14-bit CMOS
DAC. The four most significant bits are segmented. The layout
of the converters is a straightforward structure using an array
of current sources, as reported in [9]–[11] and [13]. All unit
current sources are placed symmetrically to drive their output
current in the same physical direction.
In Fig. 15, we show the output spectrum of a single-ended
output of the converter. The sample frequency is 25 MHz and
the signal frequency 670 kHz. The input signal amplitude is
15 dBFS
. The distortion with respect
to the second harmonic HD is approximately 59 dBc, and for
the third harmonic HD we have 57 dBc. In measurements,
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 5, MAY 1999
Fig. 16. Measured distortion with respect to the second and third harmonic
versus signal power for a 14-bit DAC. The dc value is held constant and the
ac value is varied.
we have also found a HD
65 dBc and HD
74 dBc
at clock frequencies around 5 MHz [9] and signal amplitudes
of 6 dBFS. These results also indicate the impact of the
dynamic properties, which degrades the performance with
higher frequencies.
As a function of the signal amplitude, the measured distortion with respect to the second and third harmonic is also
shown in Fig. 16. When varying the ac value of the signal
and keeping the dc value constant, it is seen that HD is
approximately constant and HD is decreasing by 6 dB for
each doubling of the signal’s amplitude. This follows the result
found in (20). We see from the equation that if the dc value
value, the SFDR should be
is small compared to the
decreasing by 6 dB with a 6 dB increase of the signal. The
same measurements can be made for a varying dc value and
constant ac value [9]. It can be seen that the distortion is
increased with a higher dc value as predicted in (46). (Note
that the whole impact of the matching error is not represented
by the third harmonic only).
From circuit-level simulators (spectreS), we have a parasitic
from switches and wires.
resistance of approximately 400
Using (35) in (23) and the 5-MHz measurement results, we
identify the output resistance of a unit current source to be
approximately
Fig. 17. Simulated output spectrum for a 14-bit DAC.
introduce a higher
than the actual one given by the
processing.
In Fig. 17 we show the simulated output spectrum of a
single-ended 14-bit converter, where the output impedance of
each unit current source is 2.9 G , the load resistance is 25
, parasitic resistance is approximately 375 , the capacitance
associated with each current source is approximately 4 fF, and
the parasitic capacitance 40 pF. The sampling frequency is
25 MHz and the signal frequency is 670 kHz, and the ac
signal is 15 dBFS. Compare with the measured spectrum in
Fig. 15. The performance of the converter may be predicted
using Matlab simulations.
VII. CONCLUSION
The influence of circuit imperfections on the important
frequency-domain performance parameters has been modeled.
Behavior-level models have been derived and used in Matlab
simulations. The modeling is used to predict the performance
of an implementation and to help the designer in his construction. We have seen that the calculated models can be
verified by simulations and measurements. Matlab simulations
are much more time effective than circuit-level simulations.
The freedom of varying circuit parameters is large as well.
ACKNOWLEDGMENT
G
(76)
Using the 25-MHz measurement results, the output impedance
would be approximately 250 M . Circuit-level simulations
show a dc output impedance of over 20 G . This implies that
the dynamic properties still affect the result at frequencies as
low as 5 MHz.
To find the size of the matching error (58) is used, and for
the 5 MHz measurements we have approximately
. This is a rather high value, and we realize that the
dynamic properties are influencing, as well as the correlation
of the unit current sources. Hence, the correlation factors
The authors would like to thank M. Gustavsson, Globespan Semiconductor, L. Wanhammar, Department of Electrical
Engineering, Link pings Universitet, for valuable discussion
and hints. They would also like to thank P. Pettersson, Ericsson Radio Systems, and J.-E. Eklund, Ericsson Components,
Stockholm, Sweden, for help with measurements.
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J. Jacob Wikner was born in Borgholm, Sweden,
on July 13, 1973. He received the M.Sc. degree in
computer science and engineering in 1996, and the
Lic.Eng. degree in September 1998, both from Link
pings Universitet, Sweden, where he is currently
working toward the Ph.D. degree in electronic engineering.
During the academic year 1994–1995, he studied telecommunication theory and high-speed electronics at the Technical University in Darmstadt,
Germany. He is currently with Microelectronics
Research Center (MERC), Ericsson Components, Link pings Universitet. His
main research interests include analog and mixed-signal integrated circuits, especially current-mode and switched-capacitor techniques, as well as converter
circuits for digital subscriber line applications. Modeling and behavior-level
simulation techniques for converters and analog circuits are also within his
field of research.
499
Nianxiong Tan (S’91–M’95–SM’98) was born in
Sichuan, China, on March 31, 1966. He received the
B.Eng. and M.Eng. degrees in electronic engineering from the Department of Electronic Engineering, Tsinghua University, Beijing, China, in 1988
and 1991, respectively, and the Lic.Eng. degree
and Ph.D. degree in applied electronics from the
Department of Electrical Engineering, Link pings
Universitet, Sweden, in 1993 and 1994, respectively.
From 1987 to 1991, he was with the Department
of Electronic Engineering, Tsinghua University, Beijing, China. His research
involved analysis and design of bipolar circuits, CMOS operational amplifier
design, switched-capacitor network analysis and design, and digital ASIC
design. From 1991 to 1994, he was with the Department of Electrical
Engineering, Links pings Universitet, Sweden, working on oversampling data
converters, current-mode techniques, and low-power design of DSP circuits .
From 1995 to 1998, he was with Microelectronics Research Center of Ericsson
Components AB, Sweden, responsible for developing analog and mixed-signal
circuits for telecommunication. He managed, coordinated, and participated in
various projects, while also holding the position of Adjunct Professor parttime at the Department of Electrical Engineering, Link pings Universitet,
leading the Analog Design Group and supervising Ph.D. students. Since April
1998, he has a Manager with GlobeSpan Semiconductor, Inc., Red Bank, NJ,
leading a group developing analog front ends for high-speed internet modems.
His research interests include mixed-analog and digital design methodology,
high-speed analog circuits, data converters, and low-power design. His recent
focus is analog front ends for high-speed internet modems. He has published
more than 60 journal and conference papers, and holds 15 patents granted or
pending. He has authored one book and has given many presentations and
lectures for industries and research institutes on analog design.
Dr. Tan was Session Chair for the 1995 and 1997 IEEE International
Symposium on Circuits and Systems. He is currently coeditor for IEEE
Circuits and Devices Magazine.