DIFFERENTIAL AMPLIFIER
The advent of the integrated circuit led to the development of circuit configurations
complementing the strengths of the technology and bypassing weaknesses. The high
degree to which the characteristics of like components on the same substrate can be matched
led to extensive use of symmetry as a filtering mechanism. The differential amplifier circuit
configuration in particular has assumed considerable prominence in this respect.
Physical and Electrical Symmetry
The 'Differential Amplifier' is associated closely with integrated circuit technology; this technology
provided both incentives for use of the circuit configuration as well as the means to construct effective
circuits of this type. The differential amplifier is used extensively in modern monolithic electronic circuitry.
The figure below illustrates the general character of a differential device. The circuit, a specific circuit
configuration need not be specified for the present purpose, is assumed to be a linear circuit and to have
physical mirror symmetry. The half-circuits on either side of the mirror symmetry line correspond both in
topology and also in the properties of respective corresponding circuit elements. The currents IA and IB
represent corresponding currents flowing within their respective half-circuits. VA and VB are
corresponding voltages (relative to a common ground) in the respective half-circuits. On the other hand Ia
and Ib are currents flowing out of one respective half-circuits, and into the other.
The application of symmetry to circuit behavior is based on a philosophical assumption that nature is not
maliciously perverse, and so similar circuit elements operated under similar conditions will behave
similarly.
Two special cases illustrate certain properties of the sort of symmetrical arrangement illustrated that are of
special interest. Suppose input signals S1 and S2 are provided to the circuit. (The actual signal might be
S1-S2 , i.e., applied between the input terminals, but it is convenient here to reference each separately to a
common ground point). Two cases of particular interest correspond to the inputs having certain general
symmetry properties. In the one case, the 'common-mode' case, both signals are the same, i.e., S1=S 2. In
the other case, the 'differential-mode' case, the signals are electrically antisymmetrical, i.e., S1= -S 2.
Consider the common-mode case first. Because of the physical symmetry of the two half-circuits and the
electrical symmetry of the input signals corresponding voltages and currents in each half circuit will be
equal. Thus, for example, Ia = Ib, and KCL requires Ia + I b = 0, i.e., both currents must be zero. A general
conclusion is that there is no common-mode current flowing between the two halves even if there are
physical connections between them.
From similar reasoning the common-mode voltage difference between corresponding points in each halfcircuit must be zero, i.e., VA =VB = 0.
ECE 414
1
M H Miller
For the differential-mode case corresponding voltages and currents have equal magnitudes but opposite
signs. Hence Ia = -Ib and there can be a differential-mode current flow between the circuit halves.
Similarly VA-VB = 2VA = 2VB, and is not necessarily zero.
To suggest a general import of these symmetry-based conclusions suppose that S1 and S2 are general
signals, i.e., they have no special relationship to one another. One can write (the expressions will be
recognized as identities),
where SC = (S 1+S 2)/2 is the even (common mode) part, and SD = (S 1-S2)/2 is the odd (differential
mode) part, of the two signals. Any two voltages may be expressed as the sum of an even (common-mode)
part and an odd (differential-mode) part. The (linear) circuit performance of S1 and S2 can be studied by
considering the response to SC and SD separately, and then superimposing the two results.
Suppose the output is taken between the two circuit halves, e.g., the voltage between corresponding points
in the two halves. Then the output for SC will be zero; the circuit symmetry discriminates against the
common-mode part of the output difference. However what is discrimination for the even part becomes
reinforcement for the odd part; the differential mode signal component is not suppressed. One interesting
application of this discrimination is in reducing the introduction of extraneous noise into electronic circuits.
If the amplifier input leads are physically close to each other the induction of noise voltage tends to be the
same on both inputs, i.e., it has a common-mode character and is discriminated against in favor of an
intended input signal provided in differential mode form.
Differential Amplifier
The figure below illustrates an basic differential BJT amplifier configuration; the insert indicates how the
single physical emitter resistance can be apportioned symmetrically as two physically symmetrical halfcircuits. Assume, at least for the time being, that corresponding resistors and transistors are precisely
matched.
Assume further that the signal voltages V1 and V2 have been partitioned into their common and differential
mode components as described before, and consider each component separately.
Only a common-mode current flows through RE; this is twice (i.e., the sum of the currents in each of the
fictional 2RE resistors) the common mode current through either emitter. The differential-mode emitter
current flows entirely from one emitter to the other; application of KCL indicates there is no differential
mode current through RE.
ECE 414
2
M H Miller
Since there is no common-mode current flow between the
circuit halves the two halves act independently (identically
theoretically) in response to the common mode inputs; the
figure to the left shows the left half-circuit. The incremental
voltage gain of this circuit is reduced by the emitter feedback
resistor, and is approximately -RC/(2RE).
On the other hand, since there is no differential mode current
through RE, the emitter voltage is effectively a virtual ground
as far as differential incremental voltage changes are
concerned. The emitter resistance is electrically absent and
thus causes no decrease in differential mode gain. Thus
there is a built-in discrimination against common-mode
signals and in favor of differential-mode signals.
One particular advantage of this configuration, in fact the one initially motivating the use of this
configuration in integrated circuits, is associated with temperature and related bias effects tending to be
common mode effects, e.g., the symmetrical circuit halves ordinarily would be in the same general thermal
environment and each half have similar thermal variations. Hence there is no need to use a bypass capacitor
across RE to discriminate between differential signal current changes and current variations caused by
slower thermal changes; the intrinsic common mode-differential mode discrimination provides the filtering.
Bypass capacitors are a relatively expensive component to produce in integrated circuit form and their
avoidance by itself was and remains a strong motivation for the use of differential circuit configurations.
But in addition many extraneous 'noise' signals tend to be induced symmetrically on the amplifier inputs,
and there is then an intrinsic discrimination against such signals as well.
The discrimination against common mode signals is greater the larger the size of RE. However for a given
quiescent emitter current in each transistor the greater RE the greater the common mode DC voltage drop
across it and so, for example, the larger the bias power supplies required in general. What is desirable is an
emitter 'resistor' which can carry the necessary DC bias current but with a small (ideally zero) DC voltage
drop; this implies a low resistance for DC currents. On the other hand this 'resistor' also should have a
large resistance for AC changes to provide effective common-mode gain discrimination. A good
approximation to such a nonlinear resistor is provided by a BJT biased to operate in the forward active
region, so that its collector current supports the differential emitter currents. A relatively small collectoremitter voltage can support a large DC collector current, but there is a relatively large collector resistance for
incremental-signal AC changes about the quiescent point.
A differential amplifier circuit using a BJT as a
current source (approximately) is shown to the right.
A simplified but quite informative analysis of this
circuit configuration may be made by assuming the
BJT providing the DC emitter current is effectively a
perfect current source (although in fact the 'source'
has an internal incremental resistance of several
kilohms corresponding to the slope of the collector
characteristics).
The pertinent circuit fragment involved and the steps
in the analysis are shown in the figure below; as
suggested for a simplified analysis the transistor is
replaced by a current source carrying a current I.
ECE 414
3
M H Miller
Equation 1 (in the figure) is a rewriting of the
idealized exponential expression for the emitter
current I of a BJT in forward active operation. Apply
this expression to both transistors (assume ß >> 1
and so emitter current ≈ collector current); the
difference of the two expressions is equation 2.
Equation 3 simply defines a convenient normalized
variable x. Note that x ≈ 1 for |V1-V2| ≈ 26
millivolts @ room temperature (300K). Equation 4 is
obtained from equation 2 by substituting the variable
x and taking the antilog. Equation 5 is the application
of KCL, assuming emitter and collector currents are
essentially equal.
Finally, Equation 6 provides expressions for both I1 and I2 in terms of the normalized voltage variable x.
Note that these expressions are anti-symmetrical, i.e., I1(x) = I2(-x). The expressions for the currents are
graphed below. The input voltage range for unsaturated operation is approximately x =±2, i.e., about ±0.5
millivolt emitter voltage change at room temperature.
The amplifier differential mode maximum collector transconductance gain occurs at x=0 and is (for I2)
with a similar expression for I1. This works out to about 10I amperes/volt at room temperature. The
voltage gain depends on the resistance of the collector resistor through which the current flows.
Note that the gain depends on the DC bias current, and this current can be used, for example, as a gain
control.
ECE 414
4
M H Miller
Differential Amplifier Transfer Characteristic Illustration
A discrete differential amplifier circuit representative of the
preceding discussion is drawn to the right. Q3 approximates a
current source emitter biasing. Although the amplifier is driven
from just the one input the signals Vi and 0 may be separated into
common mode (Vi/2, Vi/2) and differential mode (Vi/2,-Vi/2)
components. The common mode gain is quite small (about -25db),
and hence with respect to the differential output the signal is
effectively simply the differential mode component. (Actually there
will be a small influence of the common mode collector voltage on
the individual collector currents of Q1 and Q2, reflecting a modest
Early Effect.)
Compute the Q3 emitter bias current, and the incremental parameter
circuit.
The differential voltage gain is then
*Illustration #1
VI
1
0
DC
RB1 1
2
Q1
3
2
4
RC1 9
3
Q2
8
7
4
RC2 9
8
RB2 7
0
Q3
4
5
6
RE3 6
10
RB31 5
10
RB32 0
5
VCC 9
0
DC
VEE 10
0
DC
.DC VI
-0.5 0.5 1M
.LIB EVAL.LIB
.OP
.PROBE
.END
ECE 414
1
1K
Q2N3904
2.2K
Q2N3904
2.2K
1K
Q2N3904
1K
10K
47K
10
-10
5
M H Miller
Another Illustration
The collector resistors in the circuit used in the preceding illustration now are replaced by a current-mirror
arrangement, to combine the respective collector currents for a single-ended output. Transistors are
2N3904 and 2N3906.
It should be noted that in the simplified circuit as drawn Q3 and Q4 actually would not carry the same
emitter current because of an electrical asymmetry. The collector voltage of Q3 is about 9.3v while that of
Q4 is closer to zero. The Early Effect would lead to a Q3 current somewhat higher than that of Q4., and
this would cause a nonzero load current for Vi=0. A small resistor could have been added in the Q3 emitter
path to balance the currents, and make the load current zero for Vi = 0; see plot below.
*Illustration #2
VIN 1
0
DC
RB1 1
2
Q1
3
3
9
Q2
6
3
9
Q3
3
2
4
Q4
6
5
4
RB2 5
0
RL
6
0
Q5
4
7
8
RE3 8
10
RB31 7
10
RB32 0
7
VCC 9
0
DC
VEE 10
0
DC
.DC VIN
-0.3 0.3 1M
.LIB EVAL.LIB
.OP
.PROBE
.END
0
1K
Q2N3906
Q2N3906
Q2N3904
Q2N3904
1K
100
Q2N3904
1K
10K
22K
10
-10
The current into the collector of Q2 (-IC(Q2) ) and the current into the collector of Q4 (IC(Q4)) are plotted
in the figure following. The load current I(RL) = IC(Q2)+IC(Q4) also is plotted. Note that there is a
substantial current offset for absent an input signal, corresponding to the larger Q2 current magnitude.
ECE 414
6
M H Miller
A second computation is re-plotted below, this time with a 27Ω resistor in the Q3 emitter as suggested (but
not shown) before. (The adjustment would be an empirical one in practice, using a 'balancing
potentiometer.)
Yet Another Illustration
A simplified version of a differential amplifier circuit configuration
not unfamiliar in monolithic technology is shown. Q3 and Q4
provide a current mirror to combine the differential signal and provide
a single-ended output. The emitter bias resistor is 'stepped' over a
range of values to illustrate the influence of the emitter current on the
transconductance gain.
This simplified circuit also is not strictly symmetrical because of the
electrical asymmetry due to the Early Effect.
ECE 414
7
M H Miller
Consider the case where RE = 4.7K. The current in each emitter is approximately
Note that in so far as each half section is concerned the effective emitter resistor is 2(4.7) = 9.4KΩ. The
current in Q1 will be somewhat higher because of the Early Effect.
Estimate rbe ≈ 3.14KΩ, and so an incremental transconductance of 29M Siemans.(single-ended output),
*YAI
VIN
1 0
RB1
1 2
RB2
6 0
Q1
3 2
Q2
4 6
Q3
3 3
Q4
4 3
RI
4 0
RE
5 7
.PARAM RVAL=1
DC 0
1K
1K
5
Q2N3906
5
Q2N3906
8
Q2N3904
8
Q2N3904
100
{RVAL}
VCC
7 0
DC 10
VEE
8 0
DC -10
.LIB EVAL.LIB
.DC VIN -0.3 0.3 1M
.STEP PARAM RVAL
+ LIST 1K 2.2K 4.7K 8.2K
.PROBE
.OP
.END
Computed results for RE = 4.7KΩ are:
NAME
MODEL
IC
VBE
VCE
(1) 0.0000
(5) .6879
ECE 414
Q1
Q2N3906
-1.18E-03
-7.00E-01
-1.00E+01
Q2
Q2N3906
-7.89E-04
-7.00E-01
-7.56E-01
Q3
Q2N3904
1.16E-03
6.70E-01
6.70E-01
NODE VOLTAGE
(2) 0025
(3) -9.3448
(6) 0025
(7) 10.0000
8
Q4
Q2N3904
1.31E-03
6.70E-01
9.95E+00
(4) -.0299
(8) -10.0000
M H Miller
Elementary Operational Amplifier
For a final illustration several circuits previously discussed are combined to form the simplified
'operational' amplifier circuit drawn below. The bias current for the first stage differential amplifier is
provided through Q1, Q2. The difference current is converted to a single ended output at node 4 by a
current mirror to provide the input to a current amplifier Q8. Note the bias current for Q8 is provided by
the 'current source' formed by Q3. D1 and D2 provide crossover distortion correction for the Class AB
output stage. The bias 'potentiometer' is adjusted experimentally (i.e., by hindsight) to set the output
voltage to zero (approximately) for zero input voltage. Note incidentally that the differential input is
operated single-ended, corresponding to a differential mode input of VIN/2. Analysis of the circuit to
estimate the computed performance is left as an exercise.
A netlist corresponding to the circuit diagram follows; .DC, .AC, and .TRAN analyses are specified.
*OpAmp Illustration
Q1
7
7
11
Q2N3906
Q3
8
7
11
Q2N3906
RC1 7
0
4.7K
D1
8
9
D1N4004
Q2
6
7
11
Q2N3906
D2
9
10
D1N4004
V+
11
0
DC
10
Q8
10
4
13
Q2N3904
*VIN 1
0
DC
1
RE8 13
12
100
*VIN 1
0
AC
1
Q9
11
8
14
Q2N3904
VIN 1
0
SIN(0 1M 1K)
Q10 12
10
14
Q2N3906
RB4 1
2
1K
RL
14
0
4.7K
Q4
3
2
6
Q2N3906
.LIB EVAL.LIB
Q5
4
5
6
Q2N3906
.LIB DIODE.LIB
RB5 5
0
1K
*.DC VIN -5M 5M 20U
Q6
3
3
12
Q2N3904
*.AC DEC 20 10 1000K
Q7
4
3
12
Q2N3904
.TRAN 10U 2M
V12
0
DC
-10
.OP
RB81 11
4
33K
.PROBE
RB82 4
12
1.76K
.END
ECE 414
9
M H Miller
NODE VOLTAGES
(1) 0.0000
(2) .0053
(5) .0053
(6) .7100
(9) -.4432
(10) -1.0707
(13) -9.7098 (14) -.4181
(3) -9.3254
(4) -9.0186
(7) 9.2763 (8) .1844
(11) 10.0000 (12) -10.0000
NAME
MODEL
IC
VBE
VCE
Q1
Q2N3906
-1.94E-03
-7.24E-01
-7.24E-01
Q2
Q2N3906
-2.83E-03
-7.24E-01
-9.29E+00
Q4
Q2N3906
-1.42E-03
-7.05E-01
-1.00E+01
Q5
Q2N3906
-1.40E-03
-7.05E-01
-9.73E+00
Q6
Q2N3904
1.40E-03
6.75E-01
6.75E-01
NAME
MODEL
IC
VBE
VCE
Q7
Q2N3904
1.40E-03
6.75E-01
9.81E-01
Q3
Q2N3906
-2.88E-03
-7.24E-01
-9.82E+00
Q8
Q2N3904
2.88E-03
6.91E-01
8.64E+00
Q9
Q2N3904
9.96E-05
6.03E-01
1.04E+01
Q10
Q2N3906
-1.89E-04
6.53E-01
-9.58E+00
ECE 414
10
M H Miller
ECE 414
11
M H Miller
PROBLEMS
1)
Calculate the voltage gain Vo/Vi at a nominal
frequency of 1 kHz, and compare to the computed
value. Note that the single-ended source is
electrically equivalent to applying the double-sided
differential mode signals Vi/2 and -Vi/2. Also Q1
and Q2 are 2N3904.
2)
The signal source for the amplifier circuit of Problem 1) is changed to two sinusoidal sources as
described in the accompanying netlist. Two transient computations are performed, one for differentialmode signals and the other for common-mode signals. Measure the output between the Q1-Q2 collectors
Problem 2
VIN1 1
0
SIN(0 0.02 1K 0 0)
RB1 1
2
1K
Q1
3
2
4
Q2N3904
RC1 5
3
2.2K
Q2
6
7
4
Q2N3904
RC2 5
6
2.2K
RB2 7
12
1K
VIN2 12
0
SIN(0 {AMPL} 1K 0 0)
.PARAM AMPL=1M
Q3
4
8
9
Q2N3904
R3A 8
0
68K
R3B 8
10
22K
RE3 9
10
1K
VCC 5
0
DC
10
VEE 10
0
DC
-10
.OP
.PROBE
.LIB EVAL.LIB
.TRAN1U
3M
.STEP PARAM AMPL LIST -0.02 0.02
.END
3)
Estimate the incremental transconductance
gain neglecting Early Effect. Compare the estimate
with the computed value.
4)
Amplitude Modulator (Illustration)
The differential amplifier circuit is used to form an efficient amplitude modulator (Gilbert Cell). The
simplified circuit diagram shown is used to illustrate the general character of the modulation process. The
single-ended' carrier' sinusoidal signal VC is used to switch Q3 and Q4 alternately between cutoff and an
amplifying state in which the bias current is provided by Q5. That bias current, and so the differential gain
ECE 414
12
M H Miller
of the amplifier, is varied sinusoidally by the modulating signal VM. The differential output then is
proportional to a product of the two sinusoids, i.e., a sinusoid whose amplitude varies sinusoidally. A small
resistance is added in the Q2 emitter path to offset the Early Effect.
In the example that follows the modulating sinusoidal signal has a 3v amplitude and a frequency of 1KHz.
The carrier, a sinusoid with a 5v amplitude, has a frequency of 20 kHz. The higher frequency product
signal can be transmitted as a radio wave more efficiently than the modulating signal itself; the modulation
can be recovered by a rectification and filtering process. (In practice the carrier should have a much higher
frequency than the modulating signal; the choice made for this illustration shows the basic modulation
effect, and provides relative computational simplicity.)
* modulator
VC
1 0 SIN(0 5 20K)
RB1 1
2
1K
Q3
3
2
7
Q2N3904
Q1
3
3
4
Q2N3906
Q2
5
3
12
Q2N3906
RX
4
12
1.2
Q4
5
6
7
Q2N3904
RB2 6
0
1K
RL
5
0
100
Q5
7
8
10
Q2N3904
RA
8
9
47K
RB
8
11
10K
VM 9
0
SIN(0 3 1K)
RE
10
11
100
VCC 4
0
DC
10
VEE 11
0
DC
-10
.LIB EVAL.LIB
.PROBE
.TRAN 10U 2M
.END
ECE 414
13
M H Miller
EXPERIMENTS
This material was part of a laboratory experiment write-up; a portion of that experiment is
included below.
Experiment 12-1
The CA3096E contains an array of three NPN
transistors and two PNP transistors, and provides, for
what are effectively discrete devices, the intrinsic
component matching of monolithic fabrication.
Assemble the differential amplifier circuit shown in
the diagram below using just the NPN devices. Be
certain that the substrate connection (pin 16) is to the
lowest voltage point in the circuit; this assures that
diodes used internally to isolate components are
properly reverse-biased. Failure to do this is almost
certain to destroy the CA3096. A suggested
component arrangement for this experiment is
illustrated below. Refer to the manufacturer's
specifications for the pinouts.
Note in the circuit diagram that an input source actually is connected to only one input; the other input is
grounded. The 'two' input sources, one having the strength zero, may be partitioned into a common mode
voltage Vi/2 and a differential mode voltage Vi/2. The common mode voltage is discriminated against quite
strongly, and so the effective input consists of a differential input of ±Vi/2.
Adjust the bias current (with Vi = 0) so that the quiescent collector voltage Vo is 6 volts. (Measure
resistances so that currents can be calculated more accurately from voltage measurements.) Assuming
well-matched transistors both collector currents will be equal.
ECE 414
14
M H Miller
Obtain experimental data for a plot of collector
current vs. differential input voltage Vi, and compare
your measurements with the theoretical expectations
described before. In taking data bear in mind the
relatively small range of input voltages within which
the output does not saturate or cutoff. A DC voltage
source which may be used to provide Vi is indicated
to the right. It is a very good idea to plot your data as
you take it to assure adequate accurate data is taken.
Experiment 12-2
Use the same circuit as above for this experiment. Apply a small sinusoidal input voltage (make sure the
signal has zero DC offset), and determine the 'single-ended' voltage gain. According to the analysis given
before this gain should be proportional to the DC bias current. Measure gain vs. bias current (plot these
data) to verify the theoretical expectation. Determine the slope of the curve and compare to the theoretical
value expected for this slope.
Experiment 12-3
Modify the previous circuit to obtain the
configuration shown to the right. (This probably can
be done simply by removing the two 2.2 kΩ collector
resistors, and then connecting pin 12 to pin 6 and pin
15 to pin 3. However check the pinouts for your
device to be sure.) The change is in the collector
configuration; the resistors are replaced by a PNP
'current mirror', and the combined collector currents
are fed to a load. (Note: the 100 Ω load is close
enough to a short-circuit not to affect the circuit
operation significantly, and still allow a convenient
voltage measurement from which the load current can
be calculated. However you may prefer to replace the
100 Ω with an opamp transimpedance amplifier to
provide a virtual ground into which to 'sink' the
output current, and also to provide an amplified
output voltage proportional to the current.) Measure
and plot the load current vs. differential voltage Vi/2.;
compare the measured data to the theoretically
expected curve.
Experiment 12-4
Another differential amplifier configuration, a
simplification of one used in a number of integrated
circuit amplifiers, is drawn to the right. PNP CE
input drivers are used, with a NPN current mirror to
combine the collector currents. Assemble this circuit;
to do so requires prior disassembly of the previous
circuitry. Remember the absolute requirement that
the substrate, pin 16, be connected to the lowest
voltage point in the circuit.
Calculate the PNP emitter voltage and compare to the
measured value. Measure and plot the current in the
100 Ω load ( or use a transimpedance amplifier) vs.
the input voltage Vi, and compare to the theoretical
expectation.
ECE 414
15
M H Miller