Analog Switches in D-PHY MIPI® Dual
Camera/Dual Display Applications
Authors:
Graham LS Connolly – Principal Engineer, Fairchild Semiconductor
Tony Lee – Applications Engineer, Fairchild Semiconductor
The Mobile Industry Processor Interface Alliance (MIPI®) is becoming more prevalent in the mobile
device product industry. Mobile devices now commonly have dual display and/or dual camera
architectures, particularly in the mid and higher functionality end products. The MIPI standard was
originally defined as a point-to-point architecture, and consequently first generation processors, sensor
modules and displays had a single MIPI port.
This article describes how, with the use of Analog switches, the legacy processors can easily interface
with dual cameras or dual displays without impacting the current system architecture and can, in
actuality, enhance system performance by isolating the transmission line effects of the second camera
(or display) loading the MIPI bus. In addition, the use of analog switches, due to their bidirectional
capability, can also be used to multiplex co-processors to a single camera or display without impacting
the performance.
As the new concept phones move to three displays, even the newer processors with 2x MIPI ports will
benefit from an analog switch multiplexer device. Therefore, understanding the use of Analog switches
and their merits will enable the retrofit or upgraded feature set mobile devices to be designed with
legacy or next generation processors.
Before delving into the details of switch applications, we will briefly summarize some of the trends in
mobile devices that may facilitate the use of analog switches.
Consumers want access to information as quickly and efficiently as possible – whether it’s the status of
their cell phone battery; the weather; the time; stock quotes; e-mail; or text messages – and they prefer
not to have to open the flip or slider of their phone to get to this information. A smaller display
(AMOLED or E-ink perhaps) can provide that option when not actively using the main touch screen
display, which is often reserved for browsing, video conferencing, music and application controls. An
analog switch can support such multiplexing.
For dual camera applications, as a consumer we want to capture those spontaneous moments and put
them on “film” (or video), and we may have a high resolution 12MP camera and a 5MP camera available
in our phone. For social networking, you might want a video conference capability (webcam) utilizing 3G
technology as a part of the feature set in your future phone. An analog switch can support a more
robust electrical interface between the dual cameras by multiplexing and isolating the camera data
paths.
So how does the analog switch fit into the MIPI architecture? The analog switch can be viewed as either
A.) a media channel as part of the Transmission Line Interconnect Structure (TLIS) or B.) part of the MIPI
Transmitter (see Figure 1). In reality, they are one and the same, but from the perspective of
characterizing the analog switch for Interoperability, it is better to consider the switch as part of the TLIS
so that its S-parameter characteristics can be accurately determined. If considering it to be part of the
transmitter, then the Interoperability D-PHY Transmitter Conformance test suite would be run.
Transmission Line Interconnect Structure (TLIS)
MIPI Tx
Analog Switch
MIPI Rx
A) Analog Switch as part of the TLIS (a “Media Channel”)
MIPI Tx
Transmission Line Interconnect
Structure (TLIS)
MIPI Processor
MIPI Rx
Analog Switch
B) Analog Switch as part of the MIPI Tx
Figure 1.
The Analog Switch as Part of a MIPI System
System designers are often wary of inserting an analog switch in point-to-point bus architectures for
fear that the insertion loss introduced may cause a system or interoperability failure. This hesitation has
been greatly reduced in recent years by the tremendous utilization of analog switches in the USB
environment when multiplexing USB, UART or audio data onto the USB connector. The same migration
and confidence can be instilled in MIPI architectures.
It is true that the RC characteristics of the analog switch need to be considered, but a more important
factor is to have good PCB design to minimize discontinuities and match impedances. Additional factors
to good signal integrity using the analog switch include the processor characteristics (particularly IOH/IOL),
flex cable and connector design, additional filter/ESD devices, terminations and bus load.
Figure 2 shows a traditional, legacy “shared” parallel bus architecture for a dual camera (high and low
resolution) and its incident wave response. There are discontinuities in the waveform as the signal
travels between the processor and camera modules. Any discontinuities in the rising or falling edges will
result in failing the MIPI specifications for Interoperability.
Low Resolution Camera (VGA)
High Resolution Camera
(> 3Meg)
BBP
Incident Wave
Waveform due to reflections and discontinuities
Reflected Wave
Figure 2.
Dual Camera Architecture with Shared Bus
The dual camera environment of Figure 2 can be easily validated by driving 2 MIPI Receiver Termination
Boards (RTB) that are both powered and terminated. The reflections will result in degradation in the
edge rate as the system moves from Low Power (LP) to HS traffic mode. This degradation also occurs for
the amplitude and edge of the differential signals when in HS traffic mode, which then results in a
closing of the eye. If one of the RTBs is turned off or un-terminated, the degradation also gets worse,
further closing the eye.
So what is the solution?
The solution is to add an analog switch.
When inserting an analog switch, the key influencing factor is still the incident wave response, as the
switch can be seen as a discontinuity. The switch RC characteristics have to be optimized to facilitate
good “eye” performance by minimizing reflections and edge rate degradation. Initially, the extra
CON/COFF of the switch may be viewed as a detriment to the system performance, but in reality, removing
the discontinuity reflections outweighs the extra capacitance and series resistance incurred by inserting
the analog switch.
The MIPI specifications use a 0.3*UI for the criteria of Interoperability, so the faster you want to run
your system, the more critical the switch CON /COFF characteristics becomes, since that is the parameter
that will impact the edge rate and, therefore, the 0.3*UI criteria. Even if the 0.3*UI is not met, it does
not mean that the insertion of the switch will result in system failure or not passing Interoperability. The
switch RON impacts the voltage drop between transmitter and receiver, so receiver (Rx) Sensitivity
thresholds need to be met when inserting the analog switch. Typically, this is of less concern due to the
low current driven through the switch and is usually 10mV or less of a voltage drop (< 5% of voltage
swing).Figure 3: waveform 1 highlights the potential effects of too fast of an edge rate (<150psec);
waveform 2 is the optimum, where the edge rate is < 0.3*UI; and waveform 3 shows the effects of too
high a capacitance that can result in an edge rate outside of the MIPI specification. It should be noted,
however, that even though the waveform 3 edge rate may not meet the recommended numeric value
for MIPI Inter-operability with the D-PHY specification, the system can still fully function and meet the
“eye” diagram. This is where prototyping in the actual phone PCB design is the final interoperability
“compliance” test. Often times, the environment has a greater impact, therefore, good PCB design (via,
connectors and correct differential impedance), choice and placement of devices are paramount.
1
2
80%
3
trise1 < 150psec
trise2 > 150psec, ≤ 0.3*UI
trise3 ≥ 0.3*UI
20%
Incident Wave Response
trise1 trise2 trise3
Figure 3.
Incident Wave Characteristics for Inserting an Analog Switch Relative to MIPI Eye
So how do I convert the legacy parallel bus architecture of OR’ing the camera modules (see Figure 2)
into a more robust system with dual cameras (or LCD)? The first option is to insert a camera isolation
switch such as the FSA1211.
Figure 4 describes the incident wave response for SPST analog switch (FSA1211) parallel architecture in a
dual camera application, which results in improving the system performance by reducing the reflections
through the isolation of the stubs and discontinuities. In this example, the low resolution camera and its
capacitance are being isolated when the high speed, high resolution camera is transmitting. When the
low resolution camera is enabled via the SPST switches, the high resolution camera stubs have less of an
impact due to the processing speed of the low resolution module. As can be seen from the oscilloscope
trace, the waveform discontinuities and ringing have been almost removed when transmitting to the
high resolution camera.
Low Resolution Camera (VGA)
FSA1211 SPST Isolates
VGA Camera
High Resolution
Camera (> 3Meg)
BBP
Incident Wave
Ref lected Wave
Figure 4.
Dual Camera Application with SPST Isolation Switch
With the advent of the MIPI D-PHY a serial interface is now used to replace the parallel bus but the same
concept of using analog switches for isolation in a dual camera/display application applies.
A further, more optimal, improvement that ensures complete isolation between serial architecture
camera modules (see Figure 5 ) is to use SPDT analog switches (such as FSA642). This is particularly
recommended for dual high resolution camera applications. Whichever path of the analog switch is
enabled is determined by the camera module/processor software stack, which then uses a GPIO to
toggle the multiplexer. This analog switch is also specifically configured to multiplex a single MIPI port
processor Clock and 2-Data Lane architecture to dual cameras or LCD’s. For example, as the consumer
opens the flip or slider, the small external AMOLED display turns off and the main display is turned on to
display the application icons. It can also be used, being bidirectional in nature, to multiplex a single
camera or display to dual processors.
With the isolation of the non-transmitting camera path, there will be no degradation on the rising and
falling edges, due to reflections, when transitioning between LP and HS traffic mode and the eye
remains open. This architecture is also applicable to dual display applications.
Interoperability testing of the analog switches as both a media channel or as part of the D-PHY Tx has
proven performance at a minimum of 800Mbps.
CLK +/-
MIPI
Camera 1
DATA 0 +/DATA 1 +/-
CLK +/-
FSA642
CLK +/-
MIPI
Camera 2
DATA 0 +/-
BBP / AP
DATA 1 +/-
DATA 0 +/DATA 1 +/-
Figure 5.
Dual Camera Application with SPDT Multiplexing Switch
To further improve system performance, it is very important to pay attention to detail with respect to
the physical board and layout to minimize the impact on signal integrity.
PCB Design and Layout
In addition to the typical considerations of PCB trace-matching - such as minimizing stubs, maintaining
differential impedance of 100 Ω ± 20%, minimizing vias and avoiding 90º trace routing - there are other
recommendations that are a function of the PCB material and the number of signal layers.
Some key recommendations include:




Route primary differential signals first, and on an adjacent signal layer to the GND plane, with
lengths matching to within approximately 1.0 -1.5mm;
Maintain differential signal trace lengths to be less than 75mm (25mm preferred);
Avoid common-mode chokes on differential signal lines unless essential for EMI;
Utilize micro-strip and strip line guidelines, such as isolating differential serial lines with adjacent
grounds; and if a signal must cross the high speed differential signals, then ensure it is done in a
perpendicular manner
The MIPI analog switches discussed in this article, with rise/fall times of 150-450ps for HS traffic, should
be placed as close as possible to the MIPI controller or driver output. The VCC decoupling (0.1 μF and/or
1 μF) should also be placed as close to the switch pin as possible.
To conclude, system engineers should not be fearful that analog switches inserted between the D-PHY
transmitter and receiver will result in problems. On the contrary, analog switches optimized for MIPI DPHY system environments, in concert with good SI techniques and board design, enable designers and
product manufacturers to take advantage of rapid feature expansion through multiplexing relevant data
sources. With a correct understanding of the characteristics of optimized analog switches, and the
importance of each in a MIPI environment means that very robust designs can be created. The high
performance MIPI switches discussed in this article offer a portfolio of products (such as FSA642) that
match well for MIPI D-PHY signal paths in the ultra-portable and consumer products while maintaining
signal integrity and optimizing key consumer specifications.
For more information about Fairchild Analog switches for camera and MIPI applications, visit
www.fairchildsemi.com/cameraswitch.
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