AN-720
APPLICATION NOTE
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AD8099 Evaluation Boards
by John Ardizzoni
INTRODUCTION
The AD8099 evaluation boards are designed to help
customers quickly implement and evaluate new low
noise, low distortion op amp designs. Any of the circuit
configurations shown in the AD8099 data sheet can be
fabricated using the AD8099 evaluation boards. The
AD8099 evaluation boards have been designed for optimal performance and minimal layout parasitics.
There are two basic AD8099 evaluation board con figurations: inverting and noninverting. These two
configurations are offered for both package types,
LFCSP and SOIC. Part numbers for the evaluation boards
can be found in Table 7 of the AD8099 data sheet, or in
Table 1 of this document.
The evaluation board features edge mounted SMA connectors at the input and output for efficient connection
to other circuit boards or test equipment. The board is
a 2-layer PCB, with ground plane on both sides of the
board. The ground plane under the input pins has been
removed. Removing the ground plane from under the
input pins minimizes the stray capacitance at the input
of the op amp, which improves stability and reduces
peaking. The evaluation board components are SMTs
and range from 0603 to 1206 case size; the electrolytic
bypass capacitors, C1–C4, are 3528 case size.
Supply bypassing for the AD8099 is a key consideration
for optimal circuit performance, especially when distortion is of concern. The AD8099 uses a combination of
common-mode bypassing (a capacitor between the two
REV. A
power supplies) and shunt bypassing (from the power
supply pins of the amplifier to ground). The evaluation
board schematics show the bypassing schemes in detail,
in Figures 1, 4, 7, and 10.
Since the AD8099 is externally compensated and has
a large gain bandwidth product, the component values
and placement are critical. The AD8099 data sheet features a detailed section on the compensation networks
and component values. In low gain configurations (G =
+2), the compensation network consists of three components, a series-parallel combination of resistor and
capacitors to the negative supply. To minimize stray
capacitance, the evaluation board provides only one set
of mounting pads for the parallel components. Therefore,
the parallel combination of resistor and capacitor (R7 and
CP for the SOIC boards and RC, CP for the LFCSP boards)
must be soldered one on top of the other. Figure 13 illustrates the proper mounting configuration. The previously
mentioned reference designators correspond to RC and
C1, found in the AD8099 data sheet.
The AD8099 output does not drive significant values of
load capacitance (>5 pF); therefore the output connections should be kept short, direct, and terminated when
appropriate. Larger values of capacitance may be driven
by placing a series resistor (25 ⍀ to 50 ⍀) into the R5
position. This will help isolate the capacitive loading effects at the output of the AD8099. Minimizing the output
capacitance will help ensure stability while minimizing
peaking and ringing.
AN-720
+VS
GND1
DIS
GND2
GND3
C2**
0.1␮F
C1
10␮F
AGND
AGND
R4
*
R3
*
IN
R1
*
U1
FEEDBACK DISABLE 8
–IN
2
+VS 7
1
3
DEV
R2
*
AGND
C3
*
C4
10␮F
*USER DEFINED VALUE
**0508 CASE SIZE
R5
*
6
VOUT
CC 5
+IN
4 –V
S
AGND
OUT
R6
*
C6
10␮F
CP
AGND
R7
*
C5**
0.1␮F
AGND
–VS
Figure 1. Noninverting Schematic (SOIC)
C6
COMPONENT SIDE
CIRCUIT SIDE
Figure 2. Board Assembly Drawings (SOIC)
Figure 3. Board Layout Patterns (SOIC)
–2–
REV. A
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+VS
DIS
GND1
GND2
C2**
0.1␮F
C1
10␮F
AGND
AGND
R4
*
R3
*
IN
R1
*
AGND
AGND
U1
FEEDBACK DISABLE 8
–IN
2
+VS 7
1
3
4
+IN
–VS
VOUT
5
CC
DEV
R2
*
C3
*
C4
10␮F
*USER DEFINED VALUE
**0508 CASE SIZE
AGND
R5
*
6
R6
*
C6
10␮F
CP
OUT
AGND
R7
*
C5**
0.1␮F
AGND
–VS
Figure 4. Inverting Schematic (SOIC)
C6
COMPONENT SIDE
CIRCUIT SIDE
Figure 5. Board Assembly Drawings (SOIC)
Figure 6. Board Layout Patterns (SOIC)
REV. A
–3–
GND3
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+VS
GND1
GND2
GND3
GND4
C2**
0.1␮F
C1
10␮F
R3
*
DIS
2
3
IN
R1P
*
AGND
R2
*
R4
*
AGND
U1
1
R1
*
AGND
AGND
4
DISABLE
FEEDBACK
–IN
+VS 8
VOUT
7
CC 6
+IN
R5
*
CP
*
RC
*
–VS 5
OUT
R6
*
C3
10␮F
AGND
CC
*
AGND
C5**
0.1␮F
–VS
*USER DEFINED VALUE
**0508 CASE SIZE
C4
10␮F
AGND
AGND
Figure 7. Noninverting Schematic (CSP)
COMPONENT SIDE
CIRCUIT SIDE
Figure 8. Board Assembly Drawing (CSP)
Figure 9. Board Layout Patterns (CSP)
–4–
REV. A
AN-720
+VS
GND1
GND2
GND3
C2**
0.1␮F
C1
10␮F
R3
*
DIS
2
3
R1P
*
AGND
R2
*
AGND
U1
1
R1
*
IN
AGND
AGND
4
R4
*
DISABLE
FEEDBACK
–IN
+IN
+VS 8
VOUT
R5
*
CP
*
7
CC 6
RC
*
–VS 5
OUT
R6
*
C3
10␮F
AGND
CC
*
AGND
C5**
0.1␮F
C4
10␮F
*USER DEFINED VALUE
**0508 CASE SIZE
AGND
–VS
AGND
Figure 10. Inverting Schematic (CSP)
COMPONENT SIDE
CIRCUIT SIDE
Figure 11. Board Assembly Drawing (CSP)
Figure 12. Board Layout Patterns (CSP)
REV. A
–5–
GND4
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RC (R7)
CC
SOLDER TERMINATOR
SOLDER
SOLDER TERMINATOR
MOUNTING PADS
PCB
Figure 13. Soldering of Two Parallel Components
Table 1. Evaluation Board Selection Guide
Package Type
Board Configuration
CSP
SOIC
Inverting
Noninverting
EVAL-ADOPAMP-1CP-I
EVAL-ADOPAMP-1CP-N
EVAL-ADOPAMP-1R-IN
EVAL-ADOPAMP-1R-NI
–6–
REV. A
–7–
AN04805–0–7/04(A)
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