IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 51, NO. 6, DECEMBER 2004
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Packaging and Integration Technologies for Future
High-Frequency Power Supplies
Seán Cian Ó Mathúna, Patrick Byrne, Gerald Duffy, Weimin Chen, Matthias Ludwig, Member, IEEE,
Terence O’Donnell, Member, IEEE, Paul McCloskey, and Maeve Duffy, Member, IEEE
Abstract—This paper reviews data from the International Technology Roadmap for Semiconductors to establish where dc–dc
converters are headed in the first decade of the new millennium.
It focuses on the high performance computing (high current, fast
response, high power density) and portable/handheld (low profile)
sectors. Magnetics and power device packaging technologies
needed to allow power supplies to move to operating frequencies
in the 1–10 MHz region are discussed. It introduces the concept of
magnetic components fully embedded (windings and core) in PCB
and silicon offering low profile and low losses at high frequency. It
also reviews developments in wirebond-free power packaging such
as flip-chip assembly that offer low profile, reduced parasitics and
increased thermal performance. Finally, consideration is given to
the changes in the power electronics industry that may need to be
addressed to enable these new technologies to play a strategic role.
Index Terms—Integrated magnetics, power packaging, power
supplies, reviews, semiconductor device packaging.
NOMENCLATURE
CSP
FEM
MEMS
NMRC
NUI
PCB
SEM
TCE
Chip scale package.
Finite-element method.
Microelectromechanical systems.
National Mircoelectronics Research Centre.
National University of Ireland
Printed circuit board.
Scanning electron microscope.
Thermal coefficient of expansion.
I. INTRODUCTION
E
XCERPTS from the International Technology Roadmap
for Semiconductor predict that by 2007, high performance
processors will be operating at 0.7 V and dissipating 190 W [1].
This will result in a total current of over 270 A being delivered
to a silicon device of dimensions 17.6 mm on a side with operating speeds of up to 7 GHz. As an aside, it is worth noting the
equivalent data for 2016 are quoted as 0.4 V, 288 W, over 700
A, 17.6 mm, and 29 GHz. These specifications present a significant technical challenge to the power supply with much research
ongoing into the development of high-efficiency, fast response
voltage regulation modules that can be located as close as possible to the processor.
Manuscript received February 3, 2003; revised December 12, 2003. Abstract
published on the Internet September 10, 2004.
S. C. Ó Mathúna, P. Byrne, G. Duffy, W. Chen, M. Ludwig, T. O’Donnell,
and P. McCloskey are with the National Mircoelectronics Research Centre, University College, Cork, Ireland (e-mail: omathuna@nmrc.ie).
M. Duffy is with the National University of Ireland, Galway, Ireland.
Digital Object Identifier 10.1109/TIE.2004.837904
At the low power end of the scale, we are interested in the
handheld/portable sector where battery power, and, in the future, fuel cells, will require low cost, low profile, miniaturized
dc–dc converters (incorporating power management functions)
with both single and multivoltage outputs for a range of devices including low voltage processors, radio-frequency/wirebond-free transceiver circuits, and high voltage displays.
A number of recent studies have addressed the question of
the technological requirements that these trends will have on the
power supply of the future. Van Wyk and Lee stated that, while
power switching and power switching network technology had
reached a high level of maturity in the previous 25 years, there
was now a need for research and innovation to be focussed on
packaging, manufacturing, and electromagnetic component integration with conductive, interconnection, and power device
structures [2].
The Power Sources Manufacturers Association reiterated
these views in their 2000 Power Technology Roadmap study
and emphasized the increasing importance of a synergy between
electromechanical packaging and circuit design in achieving
improvements in product cost and reliability [3].
In a key paper in 2000 from the then Lucent Power Systems,
Huljak et al. presented a concise roadmap of performance/technology developments required in distributed/point-of-load
dc–dc converters over the ten-year period 1998 to 2008. The
study emphasized the strong need to reduce power converter
size by increasing converter frequency up to 10 MHz by 2008
[4]. Of the five areas listed as needing significant technological
developments, two, magnetics and packaging, are the subject
of this paper.
In this paper, the limitations of existing magnetics and power
packaging technologies will be discussed and compared with
the benefits of more advanced technologies to provide reduced
losses for both high current and high switching frequency converters. The integration of magnetic devices, using novel PCB
and silicon technologies with embedded windings and magnetic
layers, capable of operating in the range 1 to 10 MHz, will be
presented. Recent trends and associated benefits of wirebondfree power device assembly will also be introduced and some of
the key research challenges discussed. Finally, consideration is
given to the impact these new, and potentially strategic, enabling
technologies may have on the power electronics industry.
II. INTEGRATED MAGNETICS
To meet the requirements of future power supplies, magnetic
components have to decrease in footprint and profile. At the
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Fig. 1. Comparison of eddy-current losses for a thin film magnetic core and a
commercial ferrite core at a frequency of 10 MHz.
same time, a certain magnetic volume is needed to transfer
power or store energy at a given frequency.
Miniaturization of power supply magnetics can be achieved
by increasing the operating frequency to decrease the required
volume. Alternatively, the profile of the magnetics can be reduced through planar magnetics whereby the windings are embedded within the printed circuit board substrate. Taking this
concept further, one can “hide” or fully embed the magnetic
component (i.e., windings and core) within the underlying substrate or to functionally integrate it with one or more other components [5].
As power supply switching frequencies increase, losses in
magnetic materials increase significantly. A qualitative review
of commercial ferrite materials shows that they are limited to the
lower megahertz region and, while some performance and cost
improvements are expected in the coming years, no significant
breakthroughs are envisaged for high-frequency ferrites [3].
The disk storage industry has been depositing high-frequency, multilayer, thin films of soft magnetic alloys, such
as permalloy (Ni80Fe20), for many years using both sputtering and electrodeposition. The plot in Fig. 1 compares the
eddy-current losses for thin film and commercial ferrite cores
at a frequency of 10 MHz, based on commercial material data.
The eddy-current loss in the thin film depends on the thickness
of the film and, more specifically, on the ratio of the thickness
to the skin depth in the material at the frequency of interest.
Thus, for a thin film with a thickness of one skin depth, the loss
is less than that of a ferrite only for high flux density levels. For
a thin film with a thickness of half the skin depth, the loss is
considerably less than the ferrite for all flux density levels.
As an example, for permalloy (Ni80Fe20), the skin depth at
10 MHz is 2.25 m. If the magnetic cross-sectional area of a thin
film is insufficient to carry the required flux, multiple layers,
separated by insulating layers, can be deposited. Further reductions in high-frequency losses can be achieved through patterning of the core layers.
Based on the above processes, research at NMRC has focussed on the development of two complimentary magnetics
technologies whereby the windings and the magnetic core layers
are fully integrated in one case, within a PCB and, in the other
case, on the surface of an insulated silicon wafer [6].
Both PCB production and silicon fabrication are based on
high volume, semiautomated manufacturing capabilities, which
in the case of magnetics removes the need for labor-intensive assembly of wire wound components and offers the potential for
high yielding, low cost components. The associated processes of
photolithographic patterning, electroplating, and etching allow
the definition of high resolution features and ensure tight parameter tolerances and high levels of reproducibility. Flexibility in
the definition of the component structure is also provided, and
there are also a broad range of soft magnetic alloys that can be
plated to a specified thickness to provide application specific
magnetic properties.
Other benefits of PCB-integrated magnetics include enhanced reliability due to reduction in the number of solder
joints; the disappearance of the magnetics into the board; and
the resulting freeing up of board surface area allowing higher
density assembly of surface mount components. Silicon-integrated magnetics allow the opportunity for further integration
with power devices and control circuitry within a single silicon
die or in a multichip package.
III. PCB INTEGRATED MAGNETICS
In terms of embedding magnetic layers in printed circuit
boards, commercial magnetic foil layers have been used to
provide magnetic core regions for inductors and transformers.
Dezuari describes a three-layer transformer of which the outer
layers carry the printed coil patterns and the inner layer is a high
permeability ferromagnetic sheet core (Material “Vitrovac (R)
6025” by Vacuumschmelze, relative permeability 100 000) [7].
Using this technology, inductances of up to 30 H are achieved
in a footprint of 1 1 cm . Zhang and Sanders use a similar
technology to make a laminated (using 80 layers of permalloy)
toroidal core, which is embedded in a multilayer PCB [8].
Other methods of incorporating magnetic layers into PCB
technology include the screenprinting of a polymer-based
composite magnetic material and the burying of toroidal cores
in thick prepreg layers (the glass reinforced epoxy layers that
are used to form PCBs.) [9], [10]. Ferreira, one of the leading
experts in the field of functionally integrated magnetics, has
most recently reported on work undertaken within a German
consortium on the development of what they refer to as embedded passives integrated circuit. This project investigated the
state-of-the-art in embedding of passives (i.e., resistors, capacitors, and magnetics) in PCB for power converters. A 100 W
converter demonstrator contained embedded capacitive layers
but the magnetics were limited to standard planar magnetics
with embedded PCB windings and planar ferrite cores [11].
The structure in Fig. 2 illustrates the concept of the PCB integrated magnetics [12]. A plan view of the fabricated device
is shown in Fig. 3(a). The magnetic core structure consists of
two plates of electroplated permalloy (NiFe) above and below
multilayer windings, which are copper conductors formed using
conventional PCB technology. Plated permalloy through-holes
or vias at the center and outside of the windings are shorted to
the permalloy plates, thereby allowing the formation of closed
magnetic cores around the windings. The operating frequency of
the magnetic device can be increased through patterning of the
Ó MATHÚNA et al.: PACKAGING AND INTEGRATION TECHNOLOGIES FOR FUTURE HIGH-FREQUENCY POWER SUPPLIES
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Fig. 2. Schematic of structure of PCB-integrated magnetics.
Fig. 4. Efficiency measurement against load current for a 4.7 mH,
PCB-integrated inductor in a 1.5 W dc–dc converter.
Fig. 3. (a) Plan view of PCB-integrated magnetic. (b) 1.5 W dc–dc converter
assembled on embedded PCB integrated inductor.
permalloy plates, which reduces losses due to high-frequency
eddy currents within the highly conducting permalloy. Further
improvement is achieved through multilayer lamination of the
permalloy. For inductors carrying dc currents, PCB processing
allows very controlled gaps to be introduced into the magnetic
plates.
A key advantage of the process is that it can be integrated
seamlessly with traditional multilayer PCB manufacturing
without significant cost implications.
Both inductors and transformers have been fabricated on a
a dedicated pilot production line at NMRC. Fig. 3(b) shows
a technology demonstrator of a 1.5 W, 3.3 V output, buck
converter, operating at 1 MHz, using a commercially available
dc–dc converter integrated circuit (IC) [13]. The converter
incorporates a PCB integrated inductor of 4.7 H, with dc
current handling capability up to 500 mA.
The footprint of the entire converter measures 10 mm 10
mm with the discrete components assembled on top of the integrated inductor to achieve an ultraflat and compact converter
design. Efficiency measurements, taken at 1 MHz and plotted
in Fig. 4, show a nearly constant efficiency over a wide range
of load and measure approximately 70% efficiency for an input
voltage of 7.22 V and 80% for 5 V input.
The technology also compares well, in terms of size and performance, with the discrete solution using an equivalent 1210
sized surface mount inductor (3.2 mm 2.5 mm).
While further research is ongoing to enhance efficiency
through reducing core losses and to develop a lower profile
converter with bare power and control die, results to date suggest that this technology offers a viable option for low profile,
low cost converters in the portable/handheld sector for power
levels in the range 1–10 W. Research is also ongoing to develop
FEMs, and ultimately, analytical models for optimization of
laminated and patterned magnetic core layers in PCB.
Fig. 5. Silicon-integrated magnetics showing plated copper windings and
plated permalloy core layer.
IV. SILICON INTEGRATED MAGNETICS
The silicon integrated magnetics concept is based on a combination of traditional, thin film, semiconductor fabrication technologies and state-of-the-art microsystems technologies. Fig. 5
shows SEM images of the silicon magnetics being researched
at NMRC. The devices consist of electroplated copper coils, enclosed by an electroplated layer of soft magnetic material (i.e.,
permalloy) [14], [15].
The feasibility of using thin-film magnetics for power conversion has been demonstrated [16]. Mino et al. demonstrated a
thin-film transformer integrated with Schottky diodes [17], and
recently Katayama et al. [18] demonstrated a 1 W dc–dc converter with a thin-film inductor integrated on an IC with power
switches and control circuitry which achieved an overall power
density of 5.6 W/cm .
However, most of the thin-film magnetic components demonstrated to date have been restricted to low power conversion
(typically 2 W), and power densities for such microtransformers are typically less than 1 W/cm . Sullivan et al. [19]
did address the design of microtransformers for slightly higher
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resistivity, low coercivity, high saturation magnetization, and
the capability of being deposited in multilayers.
V. POWER PACKAGING
Fig. 6. High aspect ratio plated copper windings.
powers (3 W) and predicted power densities of 59 W/cm .
The use of microinductors for higher powers has also been
addressed by Mehas et al. [20], specifically in the context of
rapid response, microprocessor power delivery.
To obtain high-efficiency, high-frequency transformers, the
losses in the windings and the core need to be minimized. The
losses in the windings are directly related to the resistance of the
coils. By increasing the cross-sectional area of the coils using
thick electroplated copper, the winding resistance is reduced.
The core losses are due mainly to eddy currents opposing the
magnetizing flux. These eddy currents can be significantly reduced using high resistivity and/or multilayer magnetic materials, thereby also extending the frequency of operation of the
devices up to 10 MHz and beyond.
In the case of optimizing the power density, the footprint area
of the devices must be kept small. Therefore, using MEMS technology (e.g., electrodeposition of copper into thick photoresist
mold), high aspect ratio coils can be processed that ensure the
conduction losses at high frequency can be minimized without
increasing the footprint as shown in Fig. 6.
Measured results from the most recent batch of fabricated microtransformers yielded efficiencies of 50% for a power density of 10 W/cm at 5 MHz. These devices were mainly used
to develop a predictive analytical model that would allow the
optimization of future designs. Fig. 7 shows a plot of both measured and calculated open and short circuit inductance against
frequency for the microtransformer. It can be seen that the device, with a single layer of permalloy, operates up to 5 MHz
with the analytical model being accurate to within 20% of the
measured data. Using the validated model, it has been possible
to predict a performance of between 20 and 40 W/cm at efficiencies up to 83% for devices incorporating two layers of
permalloy. Fully optimized microtransformer structures are expected to yield power densities as high as 50 W/cm at efficiencies up to 95%.
These data suggest that microfabricated magnetics on silicon, as well as providing ultralow profile options for the
portable/handheld electronics sector, may also provide a technology compatible with future high performance processors.
To achieve this goal will require thin-film materials with high
As presented in the introduction, many recent studies have
identified the limitations of traditional power device packaging
(i.e., multiple, large diameter wire bonds attached to heat sink
leadframes) for future high density, high-efficiency, fast-response power supplies delivering hundreds of amps at output
voltages below 1 V. When one considers that up to half the
resistance (and most of the inductance) of a power MOSFET
in a traditional package is attributed to the wire bonds and
leadframe, it is clear that these specifications will be seriously
compromised by the package-level parasitics.
One recognized route to achieving this optimized power
package design is to replace the conventional chip-to-board interconnect, wire bonding, with solder interconnections, giving
what can be termed a “wirebond-free” interconnect scheme.
This technological shift has already been seen for low power
devices with the packaging evolution from wirebond SO-8 and
quad flat packages (QFPs) toward solder-bumped CSPs. (A chip
scale package is one where the ratio of package to chip footprint
is at a ratio between 1.0 and 1.2.) Wirebond-free CSPs for power
devices refer to the concept of replacing wire bond connections
with solder bump connections to the power semiconductor electrical contacts. This technology offers an attractive alternative
because it has lower resistance and inductance levels, allowing
higher efficiency and higher switching frequency with the further advantage of a lower package profile. Furthermore, without
the restrictions of wirebonds on the active face of the power die,
both sides of the die become available as thermal paths for improved heat dissipation.
Fig. 8 shows schematics of the various wirebond-free
technologies, both for low power and very high power, recently introduced into commercial power switch products
(IR, Fairchild, Flip Chip Technologies) or currently being researched (CPES, USA; NMRC, Ireland; INPG, France). These
include a variant of the traditional power device large area
solder pads, the conventional, VLSI-inspired flip-chip bump,
solder posts or stud bumps, stamped dimples on copper foil,
and solder bars [21]–[28].
The following sections introduce what are seen as the key
technical challenges in implementing these emerging assembly
processes.
A. Thermal Management
As power supplies are forced down a miniaturization route
and power densities increase, one can also expect increases in
thermal management requirements. As mentioned above, a significant advantage of this CSP technology without wirebonds is
that, without the physical constraints of wire bonds, both faces
of the die are available to provide low thermal resistance paths
for improved heat dissipation from the power die. A number
of techniques are in use or have been proposed, which include
a copper strap or lid soldered to the substrate, which provides
an electrical connection for the MOSFET drain while also providing an extra low thermal resistance path.
Ó MATHÚNA et al.: PACKAGING AND INTEGRATION TECHNOLOGIES FOR FUTURE HIGH-FREQUENCY POWER SUPPLIES
Fig. 7. Measured and calculated open and short circuit inductance against frequency for silicon integrated microtransformer.
Fig. 8. Examples of wirebond-free power packaging technlogies for both low power discrete devices and high power modules.
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B. TCE Mismatch
While significant research data is available from VLSI flipchip systems, the large-area solder bumps or pads needed for
high current power devices mean that TCE mismatch issues
need to be investigated separately to understand their impact on
solder joint lifetime.
The critical parameters that influence the fatigue lifetime of
the solder joints are chip size, chip pad size, solder joint geometry, underbump metallurgy (UBM) and thickness, substrate
material, and underfill. In terms of solder joint geometry for
power devices, large area solder bumps in an hourglass geometry with a large standoff have been shown to offer increased
life times [27]. A polymer-based underfill can also significantly
increase reliability by acting as a TCE matching buffer between
the power die and underlying substrate.
C. UBM
Because aluminum is not solderable, a pretreatment followed
by the deposition of a solderable layer called a UBM is required in advance of bump deposition. An increasingly popular
aluminum pretreatment for chip bumping processes is a zincate
treatment that involves immersion of the aluminum-coated
semiconductor substrate in an extremely low pH (i.e., highly
corrosive) sodium hydroxide-based solution containing zinc
ions. This process step removes the native aluminum oxide
and deposits a protective zinc layer. Upon immersion in an
electroless nickel plating solution, the zinc dissolves and is
replaced by nickel ions that initiate the autocatalytic deposition
of the nickel UBM directly at the aluminum surface.
Research at NMRC has focused on the development of a
novel, low cost activation and electroless UBM plating process
that reduces the number of processing steps while providing
a less corrosive, more environmentally friendly processing approach. Preliminary results have shown that this technology is
readily transferrable to power devices.
D. High Current Considerations
The phenomenon of electromigration has been the focus of
significant research in the microelectronics industry, where high
current densities now associated with submicrometer conductor
lines can induce failures, in the form of voids and hillocks,
which are also a function of temperature gradients and metal
conductor grain size [29].
The impact of high currents in future power supplies is only
beginning to attract attention where, by 2007, sub one volt, high
performance, microprocessor circuits are predicted to require
more than 270 amps flowing into the load. The potential for
associated high current densities, and resulting electromigration-induced failures at the power device, UBM, solder joint,
and substrate level will require careful consideration in the context of developing high density power supply solutions with high
long-term reliability.
VI. CONCLUSION
This paper has introduced a number of packaging and integration technologies that have the potential to address key issues in
power electronics circuits as a result of increasing switching frequencies, load currents, and power densities to meet the needs
of future high performance processors and low profile, low cost
portable/handheld electronics. The technologies described will
reduce losses in both the magnetic components and the power
device assemblies as the converter switching frequencies move
toward 10 MHz, with currents reaching almost 300 A.
However, in order to reap the benefits of these technologies,
the power electronics industry will need to consider how to implement the technologies in high volume to achieve low cost and
high reliability.
The vast majority of power supply manufacturing facilities are
set up for through-hole and surface mount assembly of passive
and active components, and sundry heat sinks, connectors, and
enclosures. PCB and silicon integrated magnetics will require
the establishment of external foundries with processes that are
variants of what currently is standard within the respective PCB
and silicon manufacturing industries. PCB manufacturers will
need to enhance their capabilities in order to be able to manufacture and supply embedded magnetic components. In the case of
silicon magnetics, dedicated foundries may become component
suppliers.Furthermore,theconceptoffunctionalandsubstrateintegration of magnetics presents a number of advantages that suggest these two technologies have the potential to play a key role in
the coming decade in providing a viable route to high-frequency
magnetics in a low profile, integrated construction.
On the power packaging side, the technologies described here
will introduce the need for familiarity with chip-scale packaging, flip-chip assembly where solder joints can no longer be
visually inspected, and handling, storage, and assembly of bare
and/or semibare power die. Many companies may have to consider the subcontract route as a serious alternative to establishing
new, in-house facilities and capabilities.
The whole area of packaging and integration will become
a key enabler and differentiator in the development of future
power converters. The packaging and integration technologies
presented here are mature technologies, established in the PCB,
microelectronics, and hard magnetic disk industries. They have
the potential to become strategic technologies in the future of
the power electronics industry.
ACKNOWLEDGMENT
The authors would like to acknowledge funding support from
Enterprise Ireland.
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Seán Cian Ó Mathúna received the B.E.,
M.Eng.Sc., and Ph.D. degrees from the National
University of Ireland, Galway, Ireland, in 1981,
1984, and 1994, respectively.
From 1982 to 1993, he was instrumental in establishing the Interconnection and Packaging Group
at the National Microelectronics Research Centre
(NMRC), University College, Cork, Ireland, where
he was Senior Research Scientist. In 1993, he joined
PEI Technologies, NMRC, as Technical/Commercial Director, where he was responsible for power
packaging, planar/integrated magnetics, and product qualification. In 1997,
he rejoined NMRC as Group Director with responsibility for microsystems.
In 1999, he became Assistant Director for NMRC with responsibility for
research in microelectronics integration in the areas of ambient electronic
systems, biomedical microsystems, and energy processing for information
and communications technologies. He is a coauthor of more than 25 journal
publications and 70 papers presented at international conferences.
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Patrick Byrne received the B.Sc. degree in materials
science and the Ph.D. degree from the University of
Limerick, Limerick, Ireland, in 1993 and 1998, respectively.
In his doctoral work, he studied high-temperature liquid metal interactions with silicon nitride
based ceramics and characterized the long-term
reliability implications of environmental exposure
to the ceramic matrix. He joined the National Microelectronics Research Centre (NMRC), University
College, Cork, Ireland, in 1996, as a Research
Scientist as part of the Power Electronics group. His responsibilities included
research in the areas of power packaging interconnect, reliability, and product
development research programs for indigenous Irish industry. Currently he is
working in the field of advanced high-density power packaging solutions within
the Power for Information and Communications Technologies group at NMRC.
Gerald Duffy received the B.Sc. degree in applied
physics and electronics from University College,
Galway, Ireland, in 1989 and the M.Eng.Sc degree
in microelectronics from University College, Cork,
Ireland.
He was a Lecturer for several years at Dundalk
and Cork Institute of Technology before joining PEI
Technologies, National Microelectronics Research
Centre, University College, Cork, Ireland, in 2000.
His main research interests are in power electronics
packaging.
Weimin Chen received the B.E. and M.E. degrees
from Zhejiang University, Hangzhou, China, and the
Ph.D. degree in 1997 from South China University of
Technology, Guangzhou, China.
He is currently conducting research in the National Microelectronics Research Centre, University
College, Cork, Ireland. His main research interests
are electronic packaging and reliability physics of
electronic components and devices.
Dr. Chen won a Best Poster Award at the 4th International Conference on Materials for Microelectronics and Nanoengineering held in Helsinki, Finland, in June 2002.
Matthias Ludwig (M’91) was born in Fulda,
Germany, in 1971. He received the M. Sc. degree
in electrical engineering from Darmstadt University
of Technology, Darmstadt Germany, in 1998. He
is currently working toward the Ph.D. degree in
microelectronics at the National Microelectronics
Research Centre (NMRC), University College, Cork,
Ireland.
His research interests are in the fields of design
and modeling of planar and integrated magnetics and
power switching converters.
Terence O’Donnell (M’96) received the B.E. degree
in electrical engineering from University College,
Dublin, Ireland, in 1990, and the Ph.D. degree from
the National University of Ireland, Galway, Ireland,
in 1996.
He is currently a Senior Research Officer with PEI
Technologies, National Microelectronics Research
Centre, University College, Cork, Ireland. His main
research area is in the design and modeling of planar
and integrated magnetics, for applications in power
conversion, datacomms, telecommunications, and
MEMS.
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 51, NO. 6, DECEMBER 2004
Paul McCloskey received the B.Sc. degree in chemical engineering from Queens University Belfast,
Belfast, U.K., in 1981, and the M.Sc. degree in
energy studies and the M.Sc. degree in microelectronics from the University of Ulster, Coleraine,
U.K., in 1984 and 1991, respectively.
He has worked for 14 years in electronics manufacturing and is currently the Centre Manager of PEI
Technologies, National Microelectronics Research
Centre, University College, Cork, Ireland.
Mr. McCloskey is a member of the Institute of
Metal Finishing.
Maeve Duffy (M’94) received the B.E. degree
(Hons.) in electronic engineering and the Ph.D. degree from the National University of Ireland, Galway
(NUIG), Ireland, in 1992 and 1997, respectively.
The title of her Ph.D. dissertation was “Modeling
and Analysis of Planar Magnetic Devices.” She was
a Research Officer with PEI Technologies, National
Microelectronics Research Centre, Cork, Ireland,
from 1997 to 2001. She is currently a Lecturer in the
Department of Electronic Engineering, NUIG. Her
main research interests are in modeling and design
of magnetic components, including planar magnetics and magnetic sensors.