SN65LVDS822RGZEVM Evaluation Module
User's Guide
Literature Number: SLLU184A
September 2013 – Revised September 2013
Contents
B
........................................................................................................................ 4
Hardware Overview ............................................................................................................. 5
2.1
SN65LVDS822 .............................................................................................................. 5
2.2
LVDS Connectors ........................................................................................................... 5
2.3
Power Supply ................................................................................................................ 5
2.4
CMOS Output Bus Connector ............................................................................................. 5
Hardware Set Up ................................................................................................................. 7
3.1
Configuration Jumpers ..................................................................................................... 7
3.1.1 CLKPOL (J14) ...................................................................................................... 7
3.1.2 SLEW (J13) ......................................................................................................... 7
3.1.3 MODE14 (J20) ..................................................................................................... 7
3.1.4 SHTDN (J33) ....................................................................................................... 7
3.1.5 SWAP (J12) ......................................................................................................... 7
EVM Installation .................................................................................................................. 8
SN65LVDS822RGZEVM Schematics ...................................................................................... 9
SN65LVDS822RGZEVM Bill of Materials ............................................................................... 13
2
Contents
1
2
3
4
A
Introduction
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List of Figures
1-1.
SN65LVDS822RGZEVM Top Layer Layout .............................................................................
4
A-1.
LVDS Inputs .................................................................................................................
9
A-2.
CMOS Output Bus
A-3.
Configuration Jumpers ....................................................................................................
11
A-4.
Power
.......................................................................................................................
12
........................................................................................................
10
List of Tables
2-1.
Bit Mapping and Terminal Assignments .................................................................................
4-1.
LVDS Inputs .................................................................................................................
B-1.
SN65LVDS822RGZEVM BOM
.........................................................................................
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List of Figures
6
8
13
3
Chapter 1
SLLU184A – September 2013 – Revised September 2013
Introduction
The TI SN65LVDS822RGZEVM is a functional board design of a single device that implements an LVDSto-CMOS deserializer. The EVM supports both 4:27 and 2:27 deserialization modes and output voltages
from 1.8 to 3.3 V. This EVM acts as a hardware reference design for any implementation of the
SN65LVDS822. Figure 1-1 shows the SN65LVDS822RGZEVM top layer layout.
Upon request, layout files for the EVM can be provided to illustrate techniques used to route the
differential pairs, split power planes, place filters, and show methods to achieve length matching of critical
signals.
Figure 1-1. SN65LVDS822RGZEVM Top Layer Layout
FlatLink is a trademark of Texas Instruments.
4
Introduction
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Chapter 2
SLLU184A – September 2013 – Revised September 2013
Hardware Overview
The four functional areas of the SN65LVDS822RGZEVM (EVM) board are explained in Section 2.1
through Section 2.4.
2.1
SN65LVDS822
The SN65LVDS822 on the EVM (U1 on the schematic) operates as an LVDS-to-CMOS deserializer. It has
several unique features including three selectable CMOS output slew rates, CMOS output voltage support
of 1.8 V to 3.3 V, a pinout swap option, integrated differential termination (configurable), and automatic
low-power mode. The SN65LVDS822RGZEVM implements five low-voltage differential signal (LVDS) line
receivers: four data lanes and one clock lane. The clock is internally multiplied by 7 or 14 (depending on
pin MODE14), and used for sampling LVDS data. Each input lane contains a shift register that converts
serial data to parallel. 27 total bits-per-clock period are deserialized and presented on the CMOS output
bus.
A clock frequency range of 4 MHz to 54 MHz is supported in the standard 7× mode, which is used with
LVDS data rates of 28 to 378 Mbps. The 14× mode supports 4 to 27 MHz, for LVDS data rates of 56 to
378 Mbps. The LVDS clock frequency always matches the CMOS output clock frequency. The device is
designed to support resolutions as low as one-sixteenth VGA (160x120), and as high as 1024x600, with
60 frames per second and 24-bit color.
2.2
LVDS Connectors
The EVM is equipped with 10 SMA connectors, J1-J10, for the five LVDS line receivers. The LVDS lines
are compatible with TI FlatLink™ transmitters such as the SN75LVDS83B, SN65LVDS93A, and the
standard industry LVDS transmitters that comply with TIA/EIA-644-A.
2.3
Power Supply
The EVM operates from the power provided by two banana jack connectors (P1 and P3) common ground.
The VDD terminal (P1) is connected to the main power supply to the SN65LVDS822 device and must be
3.3 V (±10%). The VDDIO terminal (P3) is connected to the power supply of the SN65LVDS822 CMOS
outputs and must be in the range of 1.8 to 3.3 V.
2.4
CMOS Output Bus Connector
The EVM is equipped with a 56-pin header (J11) for the CMOS output bus. The even pins in the J11
connector are tied to GND and the odd pins are connected to the CMOS outputs lines. Table 2-1 shows
the CMOS output and bit mapping and terminal assignments. Because some LCD panels require a
reversed order, the SN65LVDS822 device is capable of reversing the output bus and simplifying PCB
routing. When the pin is tied to high, the CMOS outputs are in normal order, otherwise the CMOS outputs
are in reverse order.
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Hardware Overview
5
CMOS Output Bus Connector
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Table 2-1. Bit Mapping and Terminal Assignments
6
Output signal
Signal
J11
D0
R0
1
D1
R1
3
D2
R2
5
D3
R3
7
D4
R4
9
D5
R5
11
D21
R6
13
D22
R7
15
D6
G0
17
D7
G1
19
D8
G2
21
D9
G3
23
D10
G4
25
D11
G5
27
D23
G6
29
D24
G7
31
D12
B0
33
D13
B1
35
D14
B2
37
D15
B3
39
D16
B4
41
D17
B5
43
D25
B6
45
D26
B7
47
D18
HS
49
D19
VS
51
D20
DE
53
CLK
CLK
55
Hardware Overview
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Chapter 3
SLLU184A – September 2013 – Revised September 2013
Hardware Set Up
This chapter describes the jumper connections on the EVM.
3.1
Configuration Jumpers
Configuration inputs are read while the EVM is powered-on and are always in effect. Please refer to
Appendix A for additional information about the EVM schematics. The switch definitions described in
Section 3.1.1 to Section 3.1.5.
3.1.1 CLKPOL (J14)
The SN65LVDS822RGZEVM has the CLKPOL terminal to determine the clock polarity. If the CLKPOL
jumper is set on the power-down position, a pull-down resistor is connected to the terminal to indicate that
D[26:0] is valid during the CLKOUT falling edge. If the CLKPOL jumper is set on the power-up position, a
pull-up resistor is connected to the terminal to indicate that D[26:0] is valid during the CLKOUT rising
edge. TI does not recommend leaving this jumper floating.
3.1.2 SLEW (J13)
The SN65LVDS822RGZEVM has a SLEW terminal to set the CMOS output slew rate. If the SLEW jumper
is set on the power-down position, a pull-down resistor is connected to the terminal to set the CMOS
outputs to the slowest rise and fall time. If the SLEW jumper is left floating, the terminal will be floating too,
setting the CMOS outputs to the medium rise and fall time. Finally, if the SLEW jumper is set on power-up
position, a pull-up resistor is connected to the terminal to set the CMOS outputs to the fastest rise and fall
time.
3.1.3 MODE14 (J20)
The SN65LVDS822RGZEVM has a MODE14 terminal to set the number of LVDS serial bits per lane per
clock period. If the MODE14 jumper is set in power-down position, a pull-down resistor is connected to the
terminal to indicate that all the data lanes (A0 – A3) are used (7 bits per lane per clock period). If the
MODE14 jumper is set in power-up position, a pull-up resistor is connected to the terminal to indicate that
only lanes A0 and A2 are used (14 bits per-lane per-clock period).
3.1.4 SHTDN (J33)
The SN65LVDS822RGZEVM enters in shutdown mode with a low voltage applied to the terminal SHTDN.
In this mode, all CMOS outputs are driven low. If the SHTDN jumper is set in power-down mode, a pulldown resistor is connected to the terminal and the device enters in shutdown mode, otherwise the device
works normally.
3.1.5 SWAP (J12)
The SN65LVDS822RGZEVM has a SWAP terminal that selects the CMOS output pinout and also controls
differential input termination. If the SWAP jumper is set on power-down position, a pull-down resistor is
connected to the terminal to set the CMOS outputs to the default pinout and to set the differential input
termination connected. If the SWAP jumper is left floating, the CMOS outputs are set to the default pinout
and the differential inputs termination are disconnected (requires external termination). If the SWAP
jumper is set on power-up position, a pull-up resistor is connected to the terminal to set an output
swapped pinout and to set the differential input termination connected.
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Hardware Set Up
7
Chapter 4
SLLU184A – September 2013 – Revised September 2013
EVM Installation
Install the EVM by following steps 1 – 7:
1. Configure the jumpers in the SN65LVDS822RGZEVM as follows:
CLKPOL
SLEW
MODE14
SHTDN
SWAP
pull-up
pull-up
pull-down
pull-up
pull-down
2. Connect the serial outputs of the LVDS transmitter (for example, the SN65LVDS83B) to the serial
inputs of the SN65LVDS822RGZEVM as shown in Table 4-1.
Table 4-1. LVDS Inputs
LVDS Transmitter
SN65LVDS822RGZEVM
A0P
J1
A0N
J2
A1P
J3
A1N
J4
A2P
J5
A2N
J6
A3P
J7
A3N
J8
CLKp
J9
CLKn
J10
3. Configure the power supply to 3.3 V. Turn off the power supply.
4. Connect all the ground jacks of both the LVDS transmitter and the SN65LVDS822RGZEVM and tie
them to the ground terminal at the power supply.
5. Connect all the VCC jacks of both the LVDS transmitter and SN65LVDS822RGZEVM and tie them to
the V+ terminal at the power supply.
6. Connect the oscilloscope’s probes to both pin 1 and pin 55 in the EVM J11 connector. The ground of
the probes can be connected to every even pin in the EVM J11 connector.
7. Turn on the power supply.
8
EVM Installation
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Appendix A
SLLU184A – September 2013 – Revised September 2013
SN65LVDS822RGZEVM Schematics
Figure A-1 through Figure A-3 contain the schematics for this EVM.
J1
A0p
J2
A0n
J3
A1p
Layout Notes:
J4
A1n
U1A
26
1. All LVDS input traces should match.
2. Place the capacitors and 50-Ω resistors on
the bottom layer, close to the DUT pins.
3. Route LVDS input traces on the bottom layer.
Drop via on the pin pad.
A0p
J5
25
A2p
28
27
J6
30
A2n
29
J7
34
A3p
33
32
31
J8
A3n
A0n
A1p
A1n
A2p
A2n
A3p
A3n
CLKp
CLKn
SN65LVDS822RGZ
J9
CLKp
J10
CLKn
Figure A-1. LVDS Inputs
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SN65LVDS822RGZEVM Schematics
9
Appendix A
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D0/D20
D14/D6
D1/D19
D15/D22
D2/D18
D16/D21
J11
U1B
D0/D20
D1/D19
D2/D18
D3/D26
D4/D25
D5/D17
D6/D14
D7/D13
D8/D12
D9/D24
D10/D23
D11/D11
D12/D8
D13/D7
SN65LVDS822RGZ
22
D3/D26
21
20
D4/D25
19
18
D5/D17
16
13
D6/D14
12
11
D0/D20
D1/D19
D2/D18
D3/D26
D4/D25
D5/D17
D21/D16
D22/D15
D6/D14
D7/D13
D8/D12
D9/D24
D10/D23
D11/D11
D23/D10
D24/D9
D12/D8
D13/D7
D14/D6
D15/D22
D16/D21
D17/D5
D25/D4
D26/D3
D18/D2
D19/D1
D20/D0
CLKOUT
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
U1C
D14/D6
D15/D22
D16/D21
D17/D5
D18/D2
D19/D1
D20/D0
D21/D16
D22/D15
D7/D13
10
9
CONN EDGE 28X2
D23/D10
D8/D12
D24/D9
8
D25/D4
4
D26/D3
D9/D24
3
CLKOUT
D10/D23
SN65LVDS822RGZ
2
D17/D5
1
48
D18/D2
47
40
D19/D1
39
38
D20/D0
15
14
D21/D16
7
5
D22/D15
46
42
D23/D10
41
D24/D9
D11/D11
D25/D4
D12/D8
D26/D3
D13/D7
CLKOUT
Figure A-2. CMOS Output Bus
10
SN65LVDS822RGZEVM Schematics
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Appendix A
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VDD3p3V
R85
4.75K
SWAP_PU SWAP_PU
1
2
3
J12
HEADER 3
SWAP
VDD3p3V
SWAP_PD
SWAP_PD
R86
4.75K
4.75K
R87
SHTDN#_PU
SHTDN#
SHTDN#_UP
3
2
1
J33
SHTDN#_PD
HEADER 3
VDD3p3V
4.75K
R88
U1D
MODE14_PU
J29
HEADER 3
1
2
3
45
4.75K
R81
MODE14_PU
36
MODE14
SWAP
MODE14
SHTDN#
SLEW
37
SHTDN#_DN
VDD3p3V
35
R89
4.75K
MODE14_PD
MODE14_PD
23
4.75K
R82
CLKPOL
SLEW_PU SLEW_PU
SN65LVDS822RGZ
SLEW
3
2
1
J13
HEADER 3
VDD3p3V
SLEW_PD
SLEW_PD
R83
4.75K
R90
4.75K
J14
CLKPOL_PU
1
2
3
CLKPOL
HEADER 3
CLKPOL_PD
CLKPOL_PU
R84
4.75K
CLKPOL_PD
Figure A-3. Configuration Jumpers
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SN65LVDS822RGZEVM Schematics
11
Appendix A
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VDD3p3V
P1
VDD3p3V_DUT
2
1
VDD_3p3V
VDD_3p3V
VDDIO
1
VDD3p3V_B
C35
47 uF
2
1
Layout Notes:
1. Place these caps near DUT on the bottom side
of the board.
2. Each group should share one via to the power pin,
but should not share via to GND.
3. Minimize the trace length between the power pin and caps.
4. Connect capacitors to GND through thermal pad.
C37
22 uF
C39
10 uF, 25 V
C41
1 uF, 25 V
U1E
VDDIO1
6
P2
1
VDDIO2
GND
GND
VDDIO3
VDD1
49
GND_PAD
VDD2
17
C58
0.01uF
43
C54
0.01uF
24
C48
0.01uF
VDD3p3V
C59
0.1uF
C56
0.1uF
C50
0.1uF
44
SN65LVDS822RGZ
VDDIO
C53
0.01uF
P3
VDDIO_DUT
C36
47 uF
2
2
C55
0.1uF
C49
0.1uF
1
VDDIO_B
1
1
VDDIO
VDDIO
C47
0.01uF
C38
22 uF
C40
10 uF, 25 V
C42
1 uF, 25 V
Layout Notes:
1. Place banana jacks in two rows, P1 and P3 in the first row
and P2 and P4 in the second row, 750 mils apart (center-to-center).
2. Place TI logo on top side metal.
3. Add mounting holes.
Figure A-4. Power
12
SN65LVDS822RGZEVM Schematics
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Appendix B
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SN65LVDS822RGZEVM Bill of Materials
Table B-1 contains the BOM for the EVM.
Table B-1. SN65LVDS822RGZEVM BOM
Item
Qty
Reference
Part
Manufacturer
Part Number
Digikey Part Number
Pkg
1
2
C35,C36
47 uF
Vishay
293D476X9016D2TE3
718-1090-2-ND
7343
2
2
C37,C38
22 uF
Vishay
293D226X9025D2TE3
718-1070-2-ND
7343
3
2
C39,C40
10 uF, 25 V
AVX
TAJB106K025RNJ
478-5257-2-ND
1210
4
2
C41,C42
1 uF, 25 V
Kemet
C1210C105K3NACTU
399-5737-2-ND
1210
5
5
C47,C48,C53,C54,C58
0.01uF
TDK
C0603X5R0J103M
445-4704-1-ND
201
6
5
C49,C50,C55,C56,C59
0.1uF
TDK
C0603X5R0J104M
445-4711-1-ND
201
7
10
J1,J2,J3,J4,J5,J6,J7,J8,J9,J10
32K141-40ML5
Rosenberger
32K141-40ML5
8
1
J11
2 x 28
Samtec
HTSW-150-07-G-S
HTSW-150-07-G-S-ND
0.1x0.1"
9
5
J12,J13,J14,J29,J33
1x3
Samtec
HTSW-150-07-G-S
HTSW-150-07-G-S-ND
0.1x0.1"
10
3
P1,P2,P3
Banana Jack-Metal
Emerson Network
108-0740-001
J147-ND
4mm
11
10
R81,R82,R83,R84,R85,R86,R87,R88,R89,R90
4.75K
Vishay
CRCW06034K75FKEA
541-4.75KHCT-ND
603
12
1
U1
SN65LVDS822RGZR
Texas Instruments
SN65LVDS822RGZR
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T/H_SMT SMA
48-QFN
SN65LVDS822RGZEVM Bill of Materials
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13
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