A MMIC Smart Power Amplifier with On-Chip P2

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P2.23
A MMIC Smart Power Amplifier with On-Chip
Dynamic Bias Controller for WCDMA Mobile Communication
Y.H. Choi, K.Y. Kim, J.H. Kim, Y.S. Noh and C.S. Park
School of Engineering, Information and Communications University (ICU)
103-6 Munji, Yuseong, Daejeon 305-714, Korea
82-42-866-6125 (tel), 82-42-866-6110 (fax), [email protected]
Abstract – This paper presents an InGaP/GaAs HBT smart
MMIC power amplifier provided with a new dynamic bias
controller and dual power stages in parallel. The proposed
dynamic bias circuit controls the quiescent current as a
function of input power with perfect freedom, and is
implemented to a WCDMA MMIC power amplifier together
with the parallel power stages for both linearity and
efficiency. Maximum output power, PAE, and gain are
simulated to have 31.3dBm, 40.8%, and 23.9dB, respectively,
at the WCDMA condition. The smart power amplifier
exhibits an improvement of average power usage efficiency
by 220 % while keeping the WCDMA linearity.
Index Terms – Hetero-junction bipolar transistor (HBT),
monolithic microwave integrated circuit (MMIC), power
amplifier, dynamic bias controller, dual power stage, wideband code-division multiple access (WCDMA)
Recently to resolve the problem we have proposed an
adaptive bias scheme[5] that supplies reduced current at
lower power level for efficiency while more current at
higher power level for linearity. In this work, we propose a
new dynamic bias circuit that controls the quiescent
current as a function of input power with perfect freedom,
and together with parallel power stages of different emitter
area we implement a WCDMA MMIC power amplifier
consuming quiescent current optimally for both linearity
and efficiency.
II. POWER AMPLIFIER CIRCIUT DESIGN
I. INTRODUCTION
RFC
Vref1
Both efficiency and linearity are the critically required
performance to power amplifiers for non-constant
envelope digital modulation mobile terminals. Even
though the efficiency of the power amplifier reveals
maximum value around 40 % at the linearity limit,
because the most frequently used power level ranges from
-20dBm to 15dBm [1], backed-off from linearity limit, the
average efficiency of the power amplifier significantly
decreases to a value around 5%. On a while, as the RF
power level increases, the efficiency increases but the
linearity of the power amplifier degrades because the gain
compression and phase distortion are occurred.
To solve this problem, many research works have been
tried employing Doherty structures [2], DC-DC converter
[3], and smart power amplifier using a digital modecontrol signal [4]. The Doherty amplifier using Ȝ/4
transmission lines is hard to be applied to portable
terminals due to the size limitation. The power amplifier
with DC-DC converter has drawback because of
additional components and current consumption. The
smart power amplifier has gain discontinuity because of
switching between two different amplifiers.
0-7803-8451-2/04/$20.00 ©2004 IEEE
Vcc
Vcc
MMIC
RFC
Vref2
Dynamic
Bias Circuit
RF
Input
LEHBT
Input
Matching
Circuit
Vref2
Bias
Circuit
SEHBT
Vref2
Bias
Circuit
Emitter
area
2560 um2
Output
Matching
Circuit
Emitter
area
960 um2
RF
Output
Vcc
RFC
G
Fig.1. Schematic diagram of the MMIC power amplifier
Fig.1 shows the schematic diagram of the two stage
MMIC power amplifier. The power stage is composed of
two separate amplifiers connected parallel to each other;
one with emitter area of 2560um2 and the other of 960um2.
The power stage of smaller emitter (SE-HBT) is designed
to act as a major amplifier with a proper input impedance
for a low input power level while the stage with larger
emitter (LE-HBT) is biased to a class B for a lower input
power level below -7 dBm, and thus the total current to
351
the power stage will be kept to a minimum value to a
linearity limit (total quiescent current less than 10 mA).
With the aid of the dynamic bias controller, the larger
emitter power stage is designed to be biased to class AB
from class B when the input power increases above -7
dBm, and to consume quiescent current of 95 mA for the
input signal above 0 dBm for the linearity improvement.
HBT1 determine the amount of the sensing power to the
transistor HBT1 of the bias circuit. Then, HBT1 has the
emitter size of 80um2 and is biased to the same as the
drive stage for the simple estimation. As the input power
increases, the rectified base-emitter dc current of the class
AB biased HBT1 increases, and thus the base voltage of
the HBT2 is decreased. Then the increased base voltage of
the HBT3 (VB3) increases the collector current to the
power stage. If the input power is increased above a
critical value, the HBT2 will be turned off and the supply
quiescent current to the power stage will be kept constant
at a value determined by the R2-HBT3-power stage circuit.
Also with an input power below another critical value the
quiescent current will be converged to value determined
by the two bias transistors and the resistors. The two
diodes connected to the base of HBT3 compensate the
possible temperature effect.
III. OPERATING PRINCIPLE OF DYNAMIC BIAS
CONTOLLER
Fig.2. shows the load line characteristics of transistors
corresponding to the HBT cells of power stage. For a
lower input power, the dynamic bias controller supplying
the low quiescent current for power stage results in the
load line movement to the dotted one in the figure, hence,
improving the efficiency at the expense of the linearity.
IC
A:High Power
B:Low Power
VCE
VCC
Fig.2. Load line characteristics for power stage using the
dynamic bias controllerG
G
Vref2
Vref1
R2
R1
(a)
HBT3
Input
HBT2
Rb
HBT1
Cby
R3
Power
Stage
Fig.3. Dynamic bias circuit for the larger emitter power stage
Fig.3 reveals the details of the dynamic bias controller
that senses the input power to the driver amplifier and
controls the quiescent collector current to the larger power
stage. We can design the collector supply current with a
perfect freedom as a function of input power by
controlling the values of the resistances in the control
circuit. The resistance of Rb and input impedance of
(b)
352
In order to prevent the possible gain variation along
with the input power change, the impedance to the each
parallel power stage has been optimized with the
capacitance in front of the power stages. And the capacitor
to separate dc current is used in order to prevent the low
frequency oscillation and match the phase difference
between the large emitter stage and the small emitter stage.
The output matching circuit consists of a low pass filter,
suppressing harmonic distortion. The MMIC power
amplifier has been implemented to a small size of 1.2x0.9
mm2 using a commercial InGaP/GaAs HBT technology.
IV. SIMULATION RESULTS
(c)
(a)
(d)
Fig.4. The quiescent current to the larger power stage as a
function of input power level
(The reference condition for this simulation is 10Ÿ of Rb, 500Ÿ
of R1, 250Ÿ of R2, and 230Ÿ of R3.)
(a) Effect of Rb
(b) Effect of R1
(c) Effect of R2
(d) Effect of R3
Fig.4 describes the quiescent current to the larger power
stage as a function of input power level for the different
values of resistances. The value of Rb determines the input
power level sensed, R1 and R3 decide the increasing slope
of the quiescent current, and R2 determines the final value
of the quiescent current for a high power level. For the
large power stage biased to class B, Rb, R1, and R3 are
determined as 0Ÿ, 600Ÿ, and 200Ÿ, respectively to have
control function for the input power between –7 dBm and
0 dBm (equivalent to output power between 14 dBm and
23 dBm), and R2 is decided as 250Ÿ to limit the quiescent
current below 95 mA.
(b)
Fig.5. (a) Simulated maximum output power, PAE, and gain
(b) Collector current and PDF as a function of output power
353
REFERENCES
Fig.5 (a) presents the simulation results of the
maximum output power, power-added efficiency, and gain
of the 2-stage MMIC power amplifier. A maximum output
power of 31.3dBm, PAE of 40.8% and gain of 23.9dB are
obtained at 1.95GHz. Fig.5 (b) shows the collector current
change together with the probability density function
(PDF) as a function of output power.
To evaluate the efficiency improvement, the definition
of the average power usage efficiency is used [6].
Kusage
Pout
Pin
[1] T. Fowler, K. Burger, Nai-Shuo Cheng, A. Samelis, E.
Enobakhare, and S. Rohlfing, “Efficiency Improvement
Techniques at Low Power Levels for Linear CDMA and
WCDMA Power Amplifiers”, IEEE RFIC Symposium., pp. 41-44,
June 2002.
[2] J.H. Cha, Y.G. Yang, B.J. Shin, and B.M. Kim, “An Adaptive
Bias Controlled Power Amplifier with a Load-Modulated
Combing Scheme for High Efficiency and Linearity”, IEEE
MTT-S International Microwave Symposium, VOL. 1, pp. 8-13,
June 2003
[3] Peter M. Asbeck, Lawrence E. Larson, and Ian G. Galton,
“Synergistic Design of DSP and Power Amplifiers for Wireless
Communications”, IEEE Trans. on Microwave Theory and
Techniques, VOL. 49, NO. 11, November 2001.
[4] Ji Hoon Kim, Joon Hyung Kim, Youn Sub Noh, Song Gang
Kim, and Chul Soon Park, “PAE Improvement of PCS MMIC
Power Amplifier with a Bias Control Circuit”, IEICE Trans.
Electron., VOL. E86-C, No. 4, pp. 672-675, April 2003.
[5] Y.S. Noh and C.S. Park “Intelligent Power Amplifier MMIC
Using Adaptive Bias Control Circuit for W-CDMA Applications”,
IEEE Journal of Solid State Circuit, VOL 39 , Issue: 6 , pp.967970, June 2004.
[6] G. Hanington, P.F. Chen, V. Radisic. T. Itoh, and P.M. Asbeck,
“Microwave Power Amplifier Efficiency Improvement with a 10
MHz HBT DC-DC- Converter”, IEEE MTT-S Int. Microwave
Symposium. Dig. pp. 589-592, June 1998.
[7] Joon Hyung Kim, Ji Hoon Kim, Youn Sub Noh, and Chul
Soon Park, “An InGaP-GaAs HBT MMIC Smart Power
Amplifier for W-CDMA Mobile Handsets”, IEEE Journal of
Solid State Circuit, VOL. 38, No. 6, pp. 905-910, June 2003.
[8] Hyun-Min Park, Sang-Hoon Cheon, Jae-Woo Park, and
Songcheol Hong, “Demonstration of on-chip Appended Power
Amplifier for Improved Efficiency at Low Power Region”, IEEE
MTT-S Digest. pp. 691-694, June 2003.
[9] Young-Woong Kim, Ki-Chhon Han, Seok-Yong Hong, and
Jin-Ho Shin, “A 45% PAE / 18mA Quiescent Current CDMA
PAM with a Dynamic Bias Control Circuit”, IEEE RFIC
Symposium. June 2004.
(1)
Where Pin and Pout are the average RF output power
and input DC power with power amplifier pdf,
respectively. Compared to a conventional fixed quiescent
current (64 mA), this work reveals a significant reduction
of collector current for the output power below 23 dBm
that improves the power usage efficiency by 220% (10.6%
compared to 4.8%). This result reveals that by optimizing
the quiescent current with the proposed dynamic bias
controller and parallel amplifiers we can obtain both
power efficiency and linearity competitively.
V. CONCLUSION
We have designed a MMIC smart power amplifier of
improved efficiency and linearity by devising a unique
dynamic bias control circuit and dual power stages in
parallel. The circuit controls the quiescent current with
perfect freedom as a function of input power, and which
improves average power usage efficiency by 2.2 times
while keeping the WCDMA requirements including the
linearity: maximum output power of 31.1dBm, PAE of
35.85%, and gain of 23.9dB.
354
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