STATE-OF-THE-ART X-BAND MMIC POWER AMPLIFIER USING InGaP/GaAs HBTs
FOR SPACE APPLICATIONS
I. Melczarsky (1), J.A. Lonac (2), R.P. Paganelli (3)
(1)
DEIS, University of Bologna - Viale Pepoli 3/2 40123 Bologna BO Italy, Email: ilan.melczarsky@unibo.it
(2)
MEC srl – Via San Nicolò di Villola 1 40127 Bologna BO Italy, Email: julio.lonac@mec-mmic.com
(3)
IEIIT CNR– Viale Risorgimento, 2 40136 Bologna BO Italy, Email: r.paganelli@bo.ieiit.cnr.it
ABSTRACT
The paper presents the design and characterization of an
X-band monolithic High Power Amplifier chip
developed using HB20PX InGaP/GaAs Heterojunction
Bipolar Transistor (HBT) process from UMS. Unlike
other circuits in the literature, this chip has been
especially designed to be compatible with space
component derating requirements as regards maximum
voltages and currents, as well as maximum junction
temperature for active devices. Nonetheless, the
designed chip achieved 39.5 dBm of output power and
more than 40% of Power Added Efficiency at 9.6 GHz
with a collector bias voltage of just 7.8 V and a collector
current density of 17 kA/cm2. These performances are to
the best of the author’s knowledge state-of-the-art for
such low bias voltage and very close to those of
commercial or general-purpose circuits, thus making
this circuit a good candidate for next-generation spaceborne applications.
1.
INTRODUCTION
InGaP/GaAs Heterojunction Bipolar Transistor (HBT)
is a mature technology which has demonstrated very
high power densities and efficiencies up to X-band [114]. Moreover it has been space evaluated by ESA [8],
and therefore it is a valid technology for High-Power
Amplifier (HPA) Microwave Monolithic Integrated
Circuit (MMIC) blocks in current- and next-generation
space-borne radars, communication links, etc.
Although there are several examples of X-band HPAs
based on HBTs both in scientific literature [1-12] as
well as in commercial product datasheets [13-14], these
circuits are not specifically intended for space
applications. Actually, their design has been focused on
maximizing electrical performances and minimizing
area occupation and therefore little or no derating
factors have been applied in order to comply with the
stringent reliability and life requirements of a space
mission. In fact, it is known that reliability, life, and
failure rates of a given active device technology are
strongly affected by the maximum junction (channel, for
FETs) temperature, the value of the collector (drain)
bias voltage, and the level of bias current density.
Accordingly, space component directives require these
magnitudes be derated by an appropriate factor with
respect to the maximum ratings defined by the
manufacturer. Moreover, thermal effects play a
fundamental role in HBT technologies and, if not
properly dealt with, can lead to thermal instabilities [1617]. Thus it is fundamental that all these aspects be
considered during all the design phases of an MMIC
intended for space applications.
The aim of this paper is therefore to study the
capabilities of the latest advances in HBT technology
and to discuss the measured performances of an HPA
circuit
designed
adopting
space
component
requirements from an early stage. It will be shown that
with careful design and the latest technology it is
possible to achieve 39.5 dBm of output power and 40%
of Power-Added Efficiency while biasing the active
devices with low collector voltages (~75% of the
maximum collector-emitter bias voltage), low current
densities (<70% of the maximum current density), and
keeping junction temperature 50 °C below the absolute
maximum rating, which ensures excellent MTTFs thus
making this circuit a good candidate for next-generation
space-borne applications.
The paper is organized as follows: Section 2 describes
the main features of HBT technology and Section 3
presents some device characterization results used to
validate the electro-thermal device models prior to the
circuit design phase; Section 4 presents the main
guidelines and criteria adopted for the design of the
HPA and Section 5 presents the measurements of the
HPA chips. Finally, some conclusions are outlined in
Section 6.
2.
HBT TECHNOLOGY
Technology process HB20PX from UMS Foundry was
used for the HPA design. This InGaP/GaAs HBT
process is an evolution of HB20P, space-evaluated by
ESA in 2000 [8] and allows to design MMIC Power
Amplifiers from C up to Ku bands. It features a highlydoped base layer and a thick collector layer which,
combined with careful optimization of the current gain,
allows to obtain very high collector-emitter breakdown
voltages with good gain values (14.5 dB @ 10 GHz for
an 8x40 μm device [12]). Thermal stability of the
devices has also been improved by optimizing the level
of ballasting, implemented at each emitter finger
through a resistive layer at the emitter epitaxy. This has
resulted in good thermal stability margin with moderate
gain reduction. Moreover, the finger to finger thermal
resistance as well as the thermal resistance to the
substrate have been reduced thanks to the use of a thick
gold layer as a thermal drain, and multiple gold via
holes that help dissipate the heat through the GaAs
substrate and also provide a low-inductance path to the
underlying ground plane. Apart from conventional HBT
power cells, the process features “BiCell” devices [11]
in which two emitter fingers are put together on the
same base stripe. This leads to a reduction in the output
parasitic collector capacitance and also of the basecollector capacitances which improves the RF
performances and also allows to double the emitter
active area with respect to conventional cells, with
nearly the same footprint. All of these features,
combined with the use of high-quality epitaxies allow to
achieve very high power densities (3.5 W/mm)
combined with remarkable reliability performances
(MTTF>106 hours at a junction temperature of 175°C
and collector current density of 33 kA/cm2 [11]). The
process also features integrated resistors, air-bridges, via
holes, spiral inductors and MIM capacitors. Thick-metal
microstrip lines are also available which can be used to
implement low-loss impedance matching and power
combining networks.
Also the thermal resistance of the devices was measured
[18] and compared to the values specified by the
foundry.
3.
4.
DEVICE CHARACTERIZATION
UMS Foundry provides the designer with a Design Kit
for Agilent ADS CAD which includes modelling and
layout-generation capabilities for passive components
and microstrip lines, as well as for active devices.
Nonlinear electro-thermal transistor models are based
on a modified version of the classical Gummel-Poon
model suitably modified for HBTs. Device junction
temperature dynamically affects both the resistive and
the displacement components of the transistor currents
and is modelled through a nonlinear thermal impedance
which allows to simulate the device behaviour for
pulsed as well as for continuous-wave (CW) operating
conditions. Statistical process variations are also
included both in the passive as well as in the active
device models and can be accounted for in Design For
Manufacturing simulations.
In order to verify the accuracy of the foundry models
before the proper HPA design activity, a broad
measurement campaign was launched on some device
samples made available by the foundry. Accordingly,
the transistors were characterized on-wafer both in
small-signal operating conditions at several bias points
and ambient temperatures, as well as in large-signal
load-pull type nonlinear measurements. Figure 1
presents some measured and simulated load-pull
characteristics for a transistor sample. Measured
characteristics were compared to circuit simulations
using the foundry device models for a number of device
sizes and bias conditions, allowing to determine the
validity range of the models and estimate their accuracy.
Figure 1. Measured (left) and simulated (right) load pull
characteristics of an HBT transistor sample.
Also passive components (MIM capacitors, spiral
inductors, microstrip structures) were characterized with
the vector network analyzer up to 50 GHz and the
measurements compared to both the foundry electrical
models and to planar 2.5D EM simulations. The latter
allowed to set-up and refine the EM simulator
parameters that would later be extensively used both at
the design and layout phases of the HPA.
HIGH-POWER AMPLIFIER DESIGN
The design goals for this HPA circuit were 39.5 dBm of
output power and 40% of Power Added Efficiency
specified at 3 dB of gain compression over a (40°C,+50°C) baseplate temperature range. Although
there exist in the literature circuits with these
performances [1-14], the aim of this work was to design
an MMIC following space component directives with
regards to maximum voltage, maximum current density
and maximum junction temperature. Thus a derating
factor of 25% was applied to the maximum rated bias
voltage and collector current density, and a safety
margin of 50°C was maintained with respect to the
maximum junction temperature specified by the
manufacturer. Accordingly, the maximum available
collector bias voltage, DC collector current density, and
junction temperature were, respectively: 7.5 V, 19.2
kA/cm2, and 125 °C. The specified bandwidth was 500
MHz around a central frequency of 9.6 GHz.
Figure 2 shows a photograph and a block diagram of the
HPA chip which measures 5.7 x 4.5 mm2. It consists of
two power stages, the first one having 4 conventional
HBT cells working in class-A, and the final or power
stage having 8 “BiCell” transistors in an inverse Class-F
operation. The circuit was designed at a schematic level
using Agilent ADS linear (i.e. S-parameters simulation)
and nonlinear simulation capabilities (i.e. HarmonicBalance analysis). The quiescent bias point, as well as
the optimum load impedance for each stage were chosen
based on measured and simulated load-pull contours so
as to obtain the best power and efficiency performances.
Moreover, we made sure dynamic load curves remained
within the space-derated Safe Operating Area for the
devices under all operating conditions (e.g. variations in
operating temperature, bandwidth, process parameters,
load mismatch).
Vbb1
Vcc1
Vcc2
Vbb2
(3)
RF
IN
(1)
Vbb1
(2)
Vcc1
RF
OUT
(3)
(4)
(5)
Vcc2
Vbb2
Figure 2. HPA chip photograph and block diagram: (1)
input matching-network, (2) driver stage, (3) inter-stage
matching networks, (4) power stage, (5) output
matching network.
Figure 3 shows typical load curves for one output
device at different frequencies from 9 GHz to 10.2 GHz.
1.0
9.0 GHz
9.1 GHz
9.2 GHz
9.3 GHz
9.4 GHz
9.5 GHz
9.6 GHz
9.7 GHz
9.8 GHz
9.9 GHz
10.0 GHz
10.1 GHz
10.2 GHz
Ic [A]
0.8
0.6
0.4
0.2
0.0
0
2
4
6
8
10
12
14
16
18
Vce [V]
Figure 3. Simulated dynamic load curves of a single
power cell of the 2nd stage of the HPA for frequencies
between 9 GHz and 10.2 GHz (3 dB gain compression
point, Tc: 50°C)
The output network consists of a bus-bar structure [19]
to which the 8 output power cells are connected,
followed by a 4:1 impedance matching and power
combining structure made of thick metal microstrip
lines and MIM capacitors. Its main function is to
transform the 50-ohm load impedance at the output of
the HPA into suitable load impedances shown to the
collector of each power cell at the fundamental
frequency and its harmonics. Special attention needs to
be taken in order to minimize its losses since they
directly impact on the output power and power
efficiency of the amplifier. Moreover, it is fundamental
to minimize the differences among the loads shown to
each output cell and also to minimize their sensitivity to
process variations.
The inter-stage network consists of two identical
structures that combine the power of 2 driver transistors
and then split it in order to symmetrically feed 4 power
cells of the output stage. It is the most difficult section
of the circuit to synthesize since it needs to transform
the very low input impedance of 4 power cells into a
relatively high impedance shown to each of the 2 driver
cells, which is difficult to accomplish for moderate
bandwidths with acceptable losses. Moreover the
impedance transformation turns out to be very sensitive
to process variations. Finally, the input impedancematching and 1:4 power-splitting network (IMN) was
implemented in the circuit using both lumped-elements
(MIM capacitors) and microstrip transmission lines. It
was designed by optimizing the trade-off between
losses, bandwidth, area occupation and sensitivity to
process parameter variations and did not present any
particular design difficulties.
The former impedance matching and power combining
networks were initially synthesized using foundry
models for microstrip structures and lumped elements
and were then refined making extensive use of planar
EM simulations using Agilent Momentum and Sonnet.
In fact, at this frequency of operation and for relatively
compact layouts such as the one of the present design,
effective electrical lengths and spurious couplings
obtained with accurate EM simulations can differ
significantly with respect to those obtained using
compact equivalent-circuit or analytical models. This
approach was later validated experimentally using
measurements performed with a new technique [19] on
a 9-port output matching network included in the tile as
a cut-out.
Another important design consideration for this circuit
regards thermal and electrical stability, which have to be
studied and optimized carefully. In fact, common-mode
or differential (i.e. odd-mode) instabilities can arise both
for linear operating conditions with no RF applied (i.e.
small-signal instabilities) as well as for large-signal
operation (i.e. parametric instabilities). Accordingly, the
circuit has to be analyzed for all possible modes of
oscillation using linear and nonlinear techniques such as
[20] and suitable stabilization networks be inserted
where needed. Typically resistance-capacitance
networks are used at the base of each device to prevent
common-mode oscillations and resistors are put
between the bases to prevent odd-mode oscillations.
However, normal operation of the amplifier is usually
degraded by the common-mode stabilization networks,
which therefore have to be carefully optimized in order
to guarantee stability over all temperature range and
parameter space with minimum performance
degradation.
Biasing is applied symmetrically to the chip through 4
20
0
15
-5
10
-10
5
-15
0
-20
○○○ S21
□□□ S11
▲▲▲ S22
-5
-10
7
8
9
|S11|, |S22| [dB]
This Section presents the measured electrical
performances of the HPA circuit. The chips were
mounted onto a metal test-jig designed in-house, using
thermally and electrically conductive epoxy. Lowfrequency biasing networks were included on the test jig
which provide filtering and high-frequency decoupling
of the DC power sources. The test jig included RF input
and output SMA connectors attached to 50-ohm
microstrip access lines on a TMM® 10 substrate. The
DC and RF pads of the chip were connected to the
external biasing network and RF microstrip accesses
using gold bonding wires having a diameter of 25 μm. A
TRL-type procedure was used to de-embed the test-jig
from the measurements and therefore all the
measurements in the following have reference planes at
the input and output RF pads of the chip.
In order to verify the performances of the chip, the
worst-case condition was tested, i.e. with the backside
of the chip at the maximum specified temperature
(50°C) and in continuous-wave operation. In fact, for
space-borne radar applications these circuits most
typically operate during short pulses (e.g. tens of μs)
and normally the backside-to-junction temperature
increase in pulsed operation is about 5 to 20°C smaller
than the corresponding value for CW operation. Thus,
all the circuit performances that are negatively affected
by temperature (e.g. transducer gain, output power,
PAE, reliability and life) will, in most practical
applications, be better with respect to the test conditions
reported in this paper. Collector bias voltage was 7.5 V
for the 1st stage and 7.8 V for the 2nd stage transistors.
Figure 4 shows typical small-signal S parameters
measurements for this circuit. Measurements were
performed using an Agilent E8364C Vector Network
Analyzer from 7 GHz to 12 GHz. As can be seen from
the figure, the small-signal transducer gain of the HPA
(|S21|) varies from 14.9 dB to 16.4 dB from 8.3 GHz to
10 GHz, with input (|S11|) and output (|S22|) return losses
greater than 10 dB.
The following Figures display the measured large-signal
performances of the HPA. An Anritsu MG3693B RF
source followed by an Agilent 83020A amplifier were
used to feed the HPA input, whereas an Agilent
N6705A DC source was used to bias the circuit and
measure the DC currents. Input and output RF power
were sampled using an Agilent N1912A power meter
whose 2 channels were connected to directional
couplers at the input and output of the HPA and
properly calibrated. Figures 5-8 were obtained by
sweeping the input power at three fixed frequencies in a
500 MHz band centred around 9.6 GHz.
Figure 5 shows that the gain for small input power is
|S21| [dB]
CIRCUIT MEASUREMENTS
-25
-30
10
11
12
Freq [GHz]
Figure 4. Measured S parameters of the HPA (Tc=50°C,
CW operation)
17
16
Gain [dB]
5.
~16 dB with a small gain expansion observed especially
at 9.65 GHz and 9.85 GHz; the 3 dB gain compression
point occurs for an available input power of ~26 dBm.
Figure 6 shows that the output power initially grows
linearly with the input power and then saturates
smoothly to a level of ~39.8 dBm. At the 3 dB
compression point the output power is nearly 39.5 dBm.
15
f=9.35 GHz
14
f=9.65 GHz
13
f=9.85 GHz
12
11
10
5
10
15
20
25
30
Pavs [dBm]
Figure 5. Measured HPA gain vs. source available
power (Tc=50°C, CW operation)
Pout[dBm]
biasing pads located on the top and bottom edges
whereas the RF input and output of the chip are located
on the left and right borders, respectively.
40
38
36
34
32
30
28
26
24
22
20
f=9.35 GHz
f=9.65 GHz
f=9.85 GHz
5
10
15
20
25
30
Pavs [dBm]
Figure 6. Measured output power vs. source available
power (Tc=50°C, CW operation)
Figure 7 shows the Power Added Efficiency versus the
available input power, which varies somewhat with the
frequency, nonetheless exceeding the 40% goal at the 3
dB compression point.
40
35
f=9.35 GHz
30
25
f=9.85 GHz
f=9.65 GHz
10
5
0
5
10
15
20
25
30
Pavs [dBm]
Figure 7. Measured Power-Added Efficiency vs. source
available power (Tc=50°C, CW operation)
Ic [A]
2.8
2.6
2.4
f=9.35 GHz
f=9.65 GHz
2.2
2
1.8
1.6
f=9.85 GHz
2.80
2.70
2.60
Gain[dB]
Ic [A]
9.00
9.20
9.40
2.50
9.60
9.80
2.40
10.00
freq [GHz]
Figure 9. Measured gain and total DC current vs.
frequency @ ~3 dB gain compression point (Tc=50°C,
CW operation)
42.00
Pout [dBm], PAE [%]
Moreover, Figure 8 shows the total DC current absorbed
by the HPA, which corresponds to a worst-case current
density for the transistors of the 2nd stage smaller than
17 kA/cm2 (4 dB compression point), which is roughly
70% of the maximum rating for this technology.
13.70
13.60
13.50
13.40
13.30
13.20
13.10
13.00
12.90
12.80
12.70
8.80
Total Ic [A]
20
15
Gain [dB]
PAE [%]
45
more frequency selective, exhibiting a minimum value
of about 36% at the lower edge of the band and reaching
a maximum of over 41.5 % at the centre of the band.
This frequency selectivity is mainly due to the
narrowband nature of the harmonic tuning performed by
the output network.
41.00
Pout[dBm]
PAE [%]
40.00
39.00
38.00
37.00
1.4
1.2
1
36.00
8.80
9.00
9.20
9.40
9.60
9.80
10.00
freq [GHz]
5
10
15
20
25
30
Pavs [dBm]
Figure 8. Measured HPA total DC current vs. source
available power (Tc=50°C, CW operation)
Figures 9-11 display swept-frequency measurements
with constant available source power of 26 dBm which
corresponds to ~3 dB gain compression point. As in the
previous case, worst-case test conditions were
considered (i.e. backside temperature of 50°C and
continuous wave operation). It can be observed that the
compressed gain of the HPA in Figure 9 is ~13dB with
little variation over the measured band. The same can be
said with regards to the total DC absorbed current which
stays below 2.7 A or 17 kA/cm2 for the power cells of
the HPA.
The measured output power, reported in Figure 10
exceeds 39 dBm in a frequency band of 8.85 GHz to
9.95 GHz, with a maximum of ~39.6 dBm in the centre
of the band. Power added efficiency proved to be a bit
Figure 10. Measured output power and PAE vs.
frequency @ ~3 dB gain compression point (Tc=50°C,
CW operation)
Finally, Figure 11 shows the junction temperature of the
devices of the 1st and 2nd stages of the HPA. Junction
temperature was derived from the measured dissipated
power, backside temperature and thermal resistance. It
can be observed that the maximum junction temperature
of about 127 °C is reached by the transistors of the 1st
stage of the HPA. This junction temperature should
guarantee excellent reliability and life performances
fully compliant with space-mission requirements.
However, it must be taken into account that this is a
worst case since it corresponds to CW operation and
that in a typical pulsed-mode application the maximum
junction temperature would be 5°C to 20 °C smaller,
according to the duration and period of the pulses.
Finally, Table 1 summarizes the measured performances
of this circuit.
Junction Temperature [°C]
130.00
125.00
120.00
115.00
110.00
105.00
100.00
95.00
90.00
85.00
80.00
8.80
8.
1. Liu, W.; Khatibzadeh, A.; Tae Kim; Sweder, J.; “First
demonstration of high-power GaInP/GaAs HBT
MMIC power amplifier with 9.9 W output power
at X-band”, Microwave Guided Wave Lett., IEEE,
Vol. 4, Iss. 9, Sept. 1994 Page(s):293 – 295
Power s ta ge
Driver Stage
9.00
9.20
9.40
9.60
9.80
10.00
freq [GHz]
Figure 11. Junction temperature (estimated from power
measurements) vs. frequency @ ~3 dB gain
compression point (Tc=50°C, CW operation)
Magnitude
Frequency band
Output power
PAE
Operating gain
Small-signal gain
Input return loss
Total DC current
Bias voltage
Max.
junction
temperature
Value
8.85 – 9.95
39.3±0.3
38.5±2.5
13.2±0.4
14.9±0.9
> 10.6
2.7
7.5 (1st stage)
7.8 (2nd stage)
<127
Units
GHz
dBm
%
dB
dB
dB
A
V
°C
Table 1. Measured HPA performances HPA at 3 dB of
gain compression in “worst-case” conditions (CW
operation and 50°C of backside temperature)
6.
CONCLUSIONS
We presented the design and characterization activity of
an X-band HPA MMIC based on the latest evolution of
InGaP/GaAs HBT technology. The circuit was designed
following space directives regarding electronic
components and thus suitable derating factors were
applied to the maximum bias voltage, current density
and junction temperature of the active devices.
Nonetheless very good electrical performances were
measured for this chips which are close to those of
commercial or non space-oriented products.
7.
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