28V High Efficiency High Linearity InGaP/GaAs Power HBT 28V

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28V High Efficiency High Linearity
InGaP/GaAs Power HBT
N.L. Wang, W. Ma, C. Dunnrowicz, X.Chen, H.F.
Chau, X.Sun, Y.Chen, B.Lin,
EiC Corporation
I.L.Lo*, C.H. Huang*, M.H.T.Yang*,
Visual Photonics Epitaxy Co. Ltd.
C.P. Lee,
National Chiao Tung Univ., Hsinchu, Taiwan
EiC Corp.
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2003 PA Workshop 6-2
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Agenda
ƒ
ƒ
ƒ
ƒ
ƒ
Introduction
28V Operation InGaP/GaAs HBT Design
Circuit Design and Assembly
Experiment Results
Conclusion
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Introduction
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28V InGaP/GaAs HBT Power
Transistor
Background
ƒ The best InGaP/GaAs HBT designed for 3-8V operation
achieved excellent linearity and 1010 hours @ Tj=150oC
ƒ 28V HBT was demonstrated as a discrete device for
higher power operation
ƒ Flip chip was attempted to reduce thermal resistance
EiC’s Present Effort
ƒ Build MMIC compatible with existing assembly
approach
ƒ Design SOA (safe operation area) and ruggedness
ƒ Provide high linearity
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28V Operation InGaP/GaAs
HBT Design
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Design of 28V InGaP/GaAs HBT
ƒ BVcbo~70V, BVceo~35V
ƒ Conventional 100µm thick substrate MMIC
approach is adopted
ƒ Thermal resistance design of HBT layout was
done with proprietary program
ƒ SOA (Safe Operation Area) through proper
ballasting was designed with another proprietary
program
ƒ Initial “wafer level reliability” study result is very
similar to the low voltage InGaP/GaAs HBT
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Icc(mA)
(mA)
Icc
Measured I-V Curve vs.
Designed SOA for Aee=1500µm22
450
450
400
400
350
350
300
300
250
250
200
200
150
150
100
100
50
50
00
I-V
I-VCurve
Curve
SOA
boundary
Ib=1mA
Ib=1mA
Ib=2mA
Ib=2mA
Ib=3mA
Ib=3mA
Ib=4mA
Ib=4mA
Ib=5mA
Ib=5mA
00 55 10
1015
1520
2025
2530
3035
3540
4045
4550
50
Vce
Vce Class A Quiescent Bias Point
Total Emitter Area 1500um2. This is the building block for larger
size HBT
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Power HBT Design
ƒ Multi-finger building block is paralleled
in large size HBT
ƒ Patented feed structure to provide
minimum phase lag from the input feed
to the HBT fingers and minimum
variation of phase of RF signal at each
finger
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Circuit Design and Assembly
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On-chip Circuit Design
ƒ Bias circuit (based on current mirror), RF
choke and input pre-match circuit are
designed on the same chip with the power
HBT
ƒ Temperature compensation is achieved
through the current mirror
ƒ Output matching is done off-chip
ƒ Input matching is completed by off-chip
matching
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Basic Circuit Design
RFOUT
Partial
Input
Matching
RFIN
Vref
Vbias
Choke
Temperature compensated
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Assembly
ƒ Standard MMIC assembly procedure is
followed:
– The IC die is 4 mil thick
– AuSn eutectic attachment is used
– 1mil gold wire bond connects the die to the hybrid
circuit
¾ No reliability concern about the assembly
approach
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Experiment Results
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Highlights
ƒ Thermal resistance of 30-35oC/W was measured for
the building block of Ae=1500 µm2 HBT
ƒ Output power scales with HBT size to 25W at 900MHz,
while maintaining the efficiency over 60%.
ƒ Two tone test IMD3 maintains below –40dBc until
reaching saturation power.
ƒ At 900MHz under CDMA2000 9 fwr ch condition, 4.5W
with ηc=42% was measured with ACLR1=-45dBc /
ACLR2=-58dBc, and 35% at ACLR1=-50dBc
ƒ At 2GHz under CDMA2000 9fwr ch condition, 0.5W
with ηc=32% is achieved at ACLR1=-50dBc
ƒ At 2GHz under WCDMA, 23dBm with ηc=18% at
ACLR1=-45dBc
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Temperature Compensated
Bias Circuit
™ <9% change of Icq over –45 to +85oC range
Icq vs. Temperature
50
mA
40
30
20
10
0
-50
-25
0
25
50
75
100
Temperature, degC
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Gain / Efficiency of HBT with
Aee=1500 µm22
18
90
16
80
14
70
12
60
10
50
8
40
6
30
4
20
2
10
0
0
10
15
20
25
P out(dBm )
30
Gain
35
40
Efficiency
Pout=36dBm, G=14dB, ηc=71%
Gain, Efficiency vs Pout, 2GHz HBT Ae=1500um^2
100
90
80
70
60
50
40
30
20
10
0
20
16
Gain (dB)
100
Efficie ncy
Ga in(dB)
H VH B T Gain, E fficiency, 900MH z
20
12
8
4
0
10
20
30
40
Pout(dBm)
Pout=35dBm, G=13.5dB, ηc=67%
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Thermal Resistance
ƒ 30 to 35oC/W thermal resistance is
measured from the HBT of Ae=1500um^2
ƒ Measurement relies on the Vbe
vs.Temperature relationship
ƒ At full power operation, temperature rise
is 50oC
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Output Power vs. HBT Size
@900MHz
Emitter
size
Pout(dBm)
1500
3000
6000
12000
35
38
41
44
Gain(dB)
16.8
15.34
13.18
9.92
70
71
68
61
ηc %
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Two Tone Test Result @ 2GHz
Tw o Tone Test @ 2GHz HBT Ae=1500
Two Tone Test @ 2GHz HBT Ae=1500
100
0
90
-10
80
70
IMD3 20mA
-30
IMD5 20mA
-40
IMD5 40mA
IMD3 40mA
-50
mA or %
dBc
-20
60
Icc 20mA
Icc 40mA
50
Eff 20mA
40
Eff 40mA
30
-60
20
-70
10
-80
0
10
15
20
25
30
35
10
Pout (dBm) average power
15
20
25
30
35
Pout (dBm) average power
Single tone CW P1dB is 32.5dBm; Gss=13.2dB
Output power is average. Each tone power is 3dB lower; PEP is 3dB higher
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CDMA2000 Test Result
CDMA2000 ACPR vs Pout, 2GHz, HBT Ae=1500
-30
100
-35
90
-40
80
-45
70
-50
60
-55
50
-60
40
-65
30
-70
20
-75
10
-80
0
20
25
Pout(dBm)
ƒ
ƒ
ƒ
30
ACLR1
35
ACLR2
40
Eff
ACPR(dBc)
ACLR (dBc)
HVHBT ACLR vs. Pout, Ae =6000, 900MHz
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
100
90
80
70
60
50
40
30
20
10
0
10
15
Pout(dBm)
20
ACPR1
25
ACPR2
30
Efficiency
Efficiency is 32 to 35% at ACLR1=-50dBc
At 900MHz, 36.5dBm is achieved at ACLR1=-45dBc with 42% efficiency. 35dBm is
achieved at ACLR1=-50dBc. HBT size is 4 building blocks.
At 2000MHz, 27dBm is achieved with ACLR1=-50dBc from 1 building block.
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WCDMA Test Method 1
ACLR (dBc)
WCDMA ACLR vs. Pout, 2GHz, HBT Ae~1500um^2
-30
35
-35
30
-40
25
-45
20
-50
15
-55
10
-60
5
-65
0
10
18
Pout (dBm)
ƒ
ƒ
ƒ
20
ACLR1
22
ACLR2
24
26
Efficiency
Peak to average ratio is 9.8dB
P1dB is 32.5dBm
At ACLR1=-45dBc, Pout is 23dBm with 18% efficiency
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Conclusion
Key Advantages
ƒ InGaP/GaAs HBT achieves high efficiency: over 60%
at 2GHz
ƒ Excellent linearity under modulated signals
ƒ Long lifetime and stable gain is expected from the
standard InGaP/GaAs HBT result
Major Achievement
ƒ 25W is achieved in the standard MMIC approach
¾ InGaP/GaAs HBT can be further developed to
serve the high power / high reliability
applications
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Acknowledgment
ƒ The authors like to thank Mr. Jerry
Curtis for his encouragement
ƒ Many colleagues’ invaluable support on
this project is also acknowledged here
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