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USOO5581506A
United States Patent [19]
[11]
Patent Number:
Yamauchi
[45]
Date of Patent:
[54] LEVEL-SHIFTER, SEMICONDUCTOR
INTEGRATED CIRCUIT, AND CONTROL
METHODS THEREOF
[75] Inventor: Hiroyuki Yamauchi, Osaka, Japan
[73] Assignee: Matsushita Electric Industrial Co.,
Ltd., Osaka, Japan
[30]
Feb. 2, 1995
Foreign Application Priority Data
Jun. 3, 1994
[JP]
Japan .................................. .. 6422620
[51]
Int. Cl.6 ..................................................... .. G11C 7/00
[52]
[58]
US. Cl.
. .
365/189.11; 365/203; 326/62
Field of Search ............................. .. 365/l89.ll, 203,
365/l89.07, 233; 326/62, 63, 80, 93
[56]
References Cited
U.S. PATENT DOCUMENTS
4,878,201
5,317,206
10/1992
Dec. 3, 1996
Japan .
Primary Examiner—Joseph A. Popek
Attorney, Agent, or Firm—McDermott, Will & Emery
[57]
ABSTRACT
During a period corresponding to the former half of one
cycle of a clock signal, a capacitor is charged to an inter
mediate potential between the respective precharged poten
tials of two level-shifters. Subsequently, during a period
corresponding to the latter half of one cycle of the clock
signal, the capacitor is connected to that one of the output
[21] Appl. No.: 382,530
[22] Filed:
4-302463
5,581,506
10/1989 Nakaizurni ................... .. 365/18911 X
5/1994 Hanibuchi et a1. ..................... .. 326/62
nodes which shifts to a lower potential in the level-shifter on
the upper stage, while a power source line is connected to the
other output node which shifts to a higher potential. On the
other hand, the capacitor is also connected to that one of the
output nodes which shifts to the higher potential in the
level-shifter on the lower stage, while the ground line is
connected to the other output node which shifts to the lower
potential. Consequently, there can be provided a semicon
ductor integrated circuit free from power dissipation that
might have been caused by an internal power~source circuit.
The semiconductor integrated circuit enables data transfer
with a small amplitude and consumes an extremely small
amount of current even when multi-bit data lines operate in
parallel.
FOREIGN PATENT DOCUMENTS
4-211515
8/1992
our
49 Claims, 55 Drawing Sheets
Japan .
XCLK/Z
VM 1 l2"- Wee-V33’)
VIN
XCLK
CLK\3
US. Patent
Dec. 3, 1996
Sheet 1 0f 55
5,581,506
US. Patent
Dec. 3, 1996
Sheet 3 0f 55
5,581,506
U.S. Patent
Dec. 3, 1996
Fig.9
Sheet 7 of 55
5,581,506
US. Patent
Dec. 3, 1996
Fig.1O
VIN1_‘
XVIN1_"‘
l___.._____
VIN2
XVIN2"'“"
Sheet 8 of 55
5,581,506
US. Patent
Dec. 3, 1996
H“ N
Sheet 9 of 55
-_~———
g
5,581,506
-->
WCLK
A
A
XWCLK
v
w
L
I
isww : ON
:SW15OFF
{SW1 ION
: SW3: ON
: SW3 OFF
{ SW3 : ON
I SW2 : oFF
1 SW2
ON
: SW2 : OFF
?SW4= OFF 1:sw4:o~
Esvva: OFF
I
i
U.S. Patent
Dec. 3, 1996
Sheet 10 0f 55
Fig.12
XCLK
WCLK
XWCLK
VIN1
XVIN1
VIN2
.
XVIN2
VouT 1
lX
/
5,581,506
US. Patent
Dec. 3, 1996
Fig.1'5
Sheet 12 of 55
5,581,506
US. Patent
Dec. 3, 1996
Sheet 14 0f 55
5,581,506
US. Patent
Dec. 3, 1996
Sheet 15 of 55
5,581,506
Fig.18
CLK
XCLK
>I
\I
,
VIN]
XVIN1
‘
\/IN2
XVIN2
VIN3
XVIN3
VouT1
XVOUT‘I
VouT2
XVOuT2
Vows
XVouT3
REUSE OF CHARGE
/
US. Patent
Dec. 3, 1996
Sheet 16 0f 55
F i g .19
Vcc
F XC L K
IFXCLK
l__.________
P 501
ll
1
|
R4;
I-XCLK
Vss
CLKéSW]
5,581,506
US. Patent
Dec. 3, 1996
Sheet 17 of 55
5,581,506
FIgZO
6II-I"Vcc'
z
nXIH*VCC
O
ECL SIHWcc
-
(FIRST
CONVENTIONAL)
EMBODIMENT
g 4IHWcc‘
Ln
5
U
L
C:m 3IH"V¢C
2
O
ZXIHXVCC (SECOND
CONVENTIONAL)
EMBODIMENT
ZII-I‘VOC“
4
9'
A
A
‘F
4’
a
O
O.
HHXWC“
J
IH‘VCUPRESENT INVENTION)
1
Z
3
A
5
6
7
8
NUMBER OF CIRCUITS IN
PARALLEL
n
US. Patent
Dec. 3, 1996
Sheet 18 of 55
5,581,506
F i g. 21
V00
R]
VCC
IDCZ
/22
.
Vu
R2
¢5
I003
29
fSWZ
:Vcc
‘##32
100} % SW3
i4
5R3
Q
V1.
M005
SW1
Vc
US. Patent
Dec. 3, 1996
Sheet 19 of 55
5,581,506
Fig.2
m
m
m
vVA
W
VV
Vwmn
i
jWWE
M».0
ME
.IIW
11%
W19db,‘ ABAI1rv mkwat”WIW
w
v0
mw
221
_
_
__
:
V0
XV
VA
XCLK
réq/