Spring 2004 – Test 1
1.
(6 pts) Assume a signal called ‘clk’. Write a VHDL process that will print the time of the
previous low pulse width when the clock signal transitions from ‘0’ to ‘1’.
process (clk)
variable ll: line;
begin
if (clk = '1') then
write(ll, string'("PW low is: "));
write(ll,clk'delayed'last_event);
write(ll, string'(" @ "));
write(ll,now);
writeline(output,ll);
end if;
end process;
2.
(6 pts) Write a VHDL process that will only pass every 4th clock cycle:
clk
clkout
process (clk)
variable cnt: integer := 0;
variable init: boolean;
begin
if (init = FALSE) then
-- ignore initial event
clkout <= clk;
init := TRUE;
else
if (cnt = 0) then
clkout <= clk;
end if;
if (clk = '0') then
cnt := cnt + 1;
if (cnt = 4) then
cnt := 0;
end if;
end if;
end if;
end process;
3.
(6 pts) Draw the waveforms for k, j or if there is some unusual event that occurs, describe it.
signal k: integer := 0;
signal j : integer := 0;
signal a: boolean;
Predicable behavior, k,j updates scheduled at +1 delta, so they
both get the value of ‘1’ at +1 delta, then both get the value of
3 of at 2ns + 1 delta.
a <= transport TRUE after 2 ns;
process (a)
k <= k + j + 1;
end process;
process (a)
j <= j + k + 1;
end process;
4.
(6 pts) Draw the waveforms for k, j or if there is some usual event that occurs, describe it.
signal k: integer := 0;
signal j : integer := 0;
signal a: boolean;
a <= transport TRUE after 2 ns;
process (a, j)
k <= k + j + 1;
end process;
process (a, k)
j <= j + k + 1;
end process;
Delta time loop – if delta interation set high enough,
then i,j reach maximum value and overflow.
5.
(5 pts) Give an example of an access type in VHDL.
A line type is an access type to string.
6.
(6 pts) For the code below draw the waveform for ‘a’ :
0 1 2 3
4
5
6 7
1
8 9 0
signal a : std_logic;
a <= ‘H’;
process
begin
a <= transport ‘L’ after 2 ns;
wait;
end ;
process
begin
a <= transport ‘1’ after 4 ns;
wait;
process
begin
a<= transport ‘0’ after 6 ns;
wait;
end;
7.
H
A_1
A_2
A_3
A_4
A final
U
L
U
1
U
0
U
X
(5 pts) What is the difference between the std_ulogic and std_logic types?
std_ulogic is the unresolved version of std_logic, so std_ulogic types cannot have multiple drivers.
8.
(6 pts) Assume I declare a subtype of NATURAL called mvlogic that has values 0-127 that
defines 128 different drive strengths (0 the weakest, 127 the strongest). Write a resolution function
for this type.
package prob10pkg is
type natvec is array (natural range <>) of natural;
function resolve_mvlogic (x:natvec) return natural;
subtype mvlogic IS resolve_mvlogic natural;
end prob10pkg;
package body prob10pkg is
function resolve_mvlogic (x:natvec) return natural is
variable rval: natural := 0;
begin
for i in x'range loop
if ( x(i) > rval ) then
rval := x(i);
end if;
end loop;
return rval;
end resolve_mvlogic;
9.
(10 pts) Assuming the type ‘mvlogic’ above, write a process that models a ‘storage node’. The
storage node only has one terminal called ‘y’ of type ‘inout’. It accepts a generic parameter
called DTIME that is the decay time for each output strength reduction of the node. The idea is
that if DTIME amount of time passes with no active driver, then the driving strength value of the
output of the capacitor is reduced by ‘1’. (HINT: An event on this node signals a possible
change in driver...). The weakest output will be ‘0’.
use work.prob10pkg.all;
entity prob10 is
entity storage is
generic (DTIME:time);
end prob10;
port (y : inout mvlogic);
end storage;
architecture a of prob10 is
architecture a of storage is
signal wakeup:boolean;
begin
process
begin
wakeup <= not(wakeup); wait for DTIME;
end process;
process (y, wakeup)
begin
if (y'event) then
y <= y;
else
if (y /= 0) then
y <= y - 1;
end if;
end if;
end process;
end;
component storage is
generic (DTIME:time);
port (y : inout mvlogic);
end component;
signal j: mvlogic;
begin
u1: storage
generic map (DTIME => 2 ns)
port map (y=>j);
process
begin
j <= 10;
wait for 30 ns;
j <= 0;
wait;
end process;
end a;
10. (5 pts) What is the difference between a VHDL function and a VHDL procedure?
A function must return a value, all parameters must be of type ‘in’ and cannot be a pointer type.
11. (4 pts) VHDL functions and procedures are ‘overloaded’. What does this mean? Give an example.
variable a_int: integer;
variable a_real: real;
variable ll: line
write(ll,a_int);
write(ll,a_real);
An overloaded procecure uses the types of it
inputs parameters to determine what to it does.
write procedure has same form for these two
calls, but the types of the second parameter differ.
12. (5 pts) What is the difference between a VHDL library and a VHDL package? What can be
placed in a library that cannot be placed in a package?
A package can contain functions, procedures, constants, type declarations, variable declarations, constant
declarations, component declarations.
A library can contain packages, entities, architectures, configurations.
13. (4 pts) For the PLD model we studied in class, the JEDEC programming file was read at
COMPILATION, ELABORATION, or SIMULATION time?
Read at elaboration time.
14. (4 pts) What is a delta time unit? Give an example of a signal assignment with 1 delta delay.
It is an arbitrarily small delay that gives an ordering to other simultaneous events within the same
time step.
15. (4 pts) Give an example of RECORD type declaration.
record myrecord is
a_int: integer;
a_real: real;
end myrecord;
16. ( 6 pts) Describe what happens in the process below. How many times is the process executed?
What is the final value of ‘i’?
signal i: integer:= 0;
My mistake, this is an infinite loop so delta time never advances.
However, an acceptable answer is also:
process
begin
i <= i + 1;
if (i = 1) then
wait;
end if;
i <= i + 1;
end;
Process is execute once at startup, i =0. I is assigned the new
value of ‘1’ at 1 delta.
At one delta, process executed again. ‘i’ is assigned the value
value of ‘2’ at 2 delta. Process suspends, final value of ‘i’ is 2.
17. (6 pts) Describe what happens in the process below. How many times is the process executed?
What is the final value of ‘i’?
process
variable i:integer := 0;
begin
i := i + 1;
if (i = 1) then
wait;
end if;
i := i + 1;
end;
Process is execute once at startup, variable i is at
incremented, process halts with i = 1.
18. (6 pts) In the process below, draw the waveform for j
signal j:integer := 0;
signal init: boolean;
process
begin
if (init = FALSE) then
j <= transport 3 after 4 ns;
init <= TRUE;
else
j <= transport 6 after 2 ns;
wait;
end if;
end process
My mistake, infinite loop again because init is a
signal.
However, if init was a variable, then the second j
assignment would replace the first, so j value would
be a ‘6’.