EE 101 Homework 7
Redekopp
Name: _________________________________________
Due: See Blackboard
Score: ________
Blackboard ONLY Submission with companion Xilinx Project to verify your design.
While the Blackboard submission may not require you to go through all the design steps (such as drawing
out state diagrams or circuits, you should make sure to go through all the steps on your own.
HW 7a Blackboard Form
1.
[BB] (20 pts.) Analyze the sequential circuit below that implements a 4-bit
sequence checker. Find the state diagram and identify what sequence this circuit
is checking for (i.e. the shortest sequence of X that will make F=1), then complete
the waveform (Notice the state machine is in reset at the first clock edge and will
not respond to X). Enter you transition equations, state/transition table,
sequence being checked, and waveforms in the Blackboard submission.
Q1,Q0
State Name
00
SInit
01
SA
10
SC
11
SB
X
X
/PRE
S
CLK
X
Q1
Q
Q0
X
/CLR
/PRE
S
Q
R
X
Q
Q1
CLK
CLK
CLK
R
F
1
1
/CLR
Q
/RESET
/RESET
The circuit is checking for the sequence: ________
0
1
2
3
4
CLK
/RESET
X
STATE
SInit
F
1
5
6
7
8
9
2.
[BB] (15 pts.) Analyze the following sequential circuit below and find the state
diagram. Enter you transition equations and state/transition table in the
Blackboard submission. Use the following state assignement. Enter you
transition equations and state/transition table in the Blackboard submission.
Q1,Q0
00
01
11
1
A
B
/PRE
J
CLK
0
/CLR
Q
/PRE
J
Q
B
No other states exist so
unused combinations can
be ignored.
1
A
CLK
K
State Name
EQ
LT
GT
CLK
0
EQ
Q
Q1
LT
CLK
K
/CLR
Q
GT
/RESET
3.
/RESET
[BB] (5 pts.) Study the following sequential circuit and answer the questions
below.
1
A
B
D
C
/PRE
Q
Q1
F
CLK
CLK
/CLR
Q
/RESET
a.) How many states will there be in the state diagram for this circuit?
b.) Is this a Mealy or Moore Machine.
c.) When we found the state diagram, what would be the maximum number of
transition arrows originating from a state?
d.) If A is held constant at ‘1’ for more than one clock, can the output, F, be 1?
2
HW 7b Blackboard Form
Note: For problems 4-6, we have provided a Xilinx project with designs and
testbenches for these state machine designs. You are encouraged to complete them
to verify your design works via simulation before submitting the Blackboard
answers. However, you are not required to turn in any Xilinx projects or
schematics.
Important: In Xilinx the components use active high preset and clear signals and so
we provide an active-high reset signal.
[BB] (15 pts.) Below is a state diagram for a simple, home alarm system. To turn
the alarm system on or off, the user has to enter a code correctly and then hit the
enter key. If the alarm system is on (in the monitor state), the user can deactivate
it by entering the code correctly. If, however, they enter it incorrectly two times
in a row, then the user may actually be an intruder, so the system should enter the
alarm state and stay there forever (until reset). Design a state machine to
implement this diagram. Use D flip-flops and for state assignment OFF = 00,
MONITOR = 01, 1WRONG = 10, and ALARM = 11. Be sure to implement the
initial state using the /RESET signal.
a.) Enter your excitation equations on Blackboard
b.) Enter your output equations on Blackboard
c.) Show the initial state (/RESET) configuration on Blackboard.
ENTER
ENTER • CORRECT
4.
ENTER • CORRECT
1WRONG
ALARM
Alarm=0
Alarm=1
ENTER • CORRECT
ENTER • CORRECT
~RESET
Monitor
OFF
Alarm=0
Alarm=0
ENTER • CORRECT
ENTER
3
ENTER + CORRECT
5.
[BB] (15 pts.) The circuit you analyzed in question 2 was a comparator that
looked at two numbers, A and B, one bit at a time (a.k.a serially) starting with the
MSB and working down to the LSB. Go back and look at the state diagram you
found and understand its operation. Now, design a state machine that again
compares two numbers, A and B, one-bit at a time but starts with the LSB and
works up to more significant bits. You need not worry about how many bits the
numbers are, just keeping checking the A and B inputs. You should have three
states: EQ, LT, and GT with three corresponding outputs: EQ, LT, GT which
should be asserted when in the corresponding state.
Hint: As an example, think about the numbers: A=1010 and B=1100. If you
started at the LSB’s (0 and 0) you would say they are equal. Once you looked at
the second bit 1 and 0 you would say A>B, but when you looked at the next bit (0
and 1), what would you say is the relationship?
Design the system using positive-edge triggered D Flip-flops (w/ preset and clear
inputs). Use two state variables, Q1 and Q0, with the state assignment GT=00,
EQ=01, LT=11, (10 = Don’t-care). Show all steps of your design and draw out
the implementation.
Enter your excitation equations and output equations on Blackboard. Use the
preset and clear inputs along with the signal /RESET to initialize the state
machine to the initial state EQ and enter your configuration on Blackboard.
d.)
e.)
f.)
g.)
Enter your excitation equations on Blackboard
Enter your output equations on Blackboard
Show the initial state (/RESET) configuration on Blackboard.
Show the waveform of the operation of Q[2:0] on Blackboard.
Waveform for problem 5 (Note: Q1 is LOW and Q0 is HIGH initially)
0
1
2
3
CLK
A
B
Q1
Q0
State
EQ
4
4
5
6
6.
[BB] (15 pts.) Design a 3-bit Down Counter (i.e. counting down:
111,110,101,100,011,010,001,000,111…). This counter has one input DOWN.
The circuit should not count (it should stay at it’s current value) if DOWN=0.
The circuit should count down if DOWN=1. In this case, the outputs are just the
state values: Q2, Q1, Q0 which form the 3-bit count value.
Draw a state diagram of this machine. On power on (reset) the counter should
start at Q2,Q1,Q0 = 111
Using positive-edge triggered D-Flip-Flops implement the circuit (show all steps.)
You do NOT need to draw out the circuit, just come up with equations for the
flip-flop inputs (excitation variables). Use the state variables Q2, Q1 and Q0.
h.) Enter your excitation equations on Blackboard
i.) Show the initial state (/RESET) configuration on Blackboard.
j.) Show the waveform of the operation of Q[2:0] on Blackboard.
Waveform for problem 6. (Note: Q2, Q1, and Q0 are HIGH initially)
0
1
2
3
4
5
CLK
DOWN
Q2
Q1
Q0
5
6
7
8
9
10
HW 7c Blackboard Form
7.
[BB] (10 pts.) Complete the waveform for a 74LS163A synchronous 4-bit
counter (positive edge-triggered) Q[3:0] and TC outputs.
0
1
2
3
4
5
6
7
8
Clock
/SR
CEP
CET
PE
P3-P0
Q3-Q0
0101
1110
TC
8.
[BB] (5 pts.) Complete the waveform for a positive-edge triggered, 4-bit
D-Register with active-hi data (load) enable and active-low asynchronous reset.
Enter unk if the value of Q is unknown during a clock cycle.
0
1
0010
1001
2
3
4
5
6
7
0101
1010
0110
8
CLK
/AR
EN
D[3:0]
0011
1101
Q[3:0]
6
1111
0001