# Solution ```Homework 2
By Yuan Zhou
EECT 7329 Advanced Analog IC Design
Homework 2
Yuan Zhou
Step 1.
Design a folded-cascode differential amplifier
First, let’s design a simple five-transistor fully differential amplifier. Fig. 1 shows a example
design. The transistor sizes are presented in Tab. 1. The overdrive voltages of transistors
are designed to be 100∼200 mV, as shown in Tab. 2. The cascode biasing circuit is shown
as Fig. 2, where Vicm is the input common mode voltage. The CMFB circuit is shown as
Fig. 3.
Figure 1: A folded cascode fully differential amplifier
M1
Vbin
5pF
M2 M3
Vin
Vb1
M5
M6
Vb2
M7
Von
Vop
M8
Vb3
M9
M10
Vcmc
M11
5pF
Vip
M4
Table 1: Transistor sizes of the FD amplifier
M1
M2/M3/M4/M5/M6/M7
20 &times; 45 &micro;m/0.25 &micro;m
10 &times; 45 &micro;m/0.25 &micro;m
M8/M9
M10/M11
10 &times; 45 &micro;m/0.25 &micro;m 20 &times; 45 &micro;m/0.25 &micro;m
Table 2: Overdrive voltages of transistors
M1
M2/M3
M4/M5
M6/M7
M8/M9
-132 mV -117 mV -147 mV -122 mV 103 mV
Step 2.
M10/M11
135 mV
Simulation results
The only requirement of the amplifier design in this homework is the output swing. The
output voltage swing is the maximum peak voltage that the output can produce before it
1
Homework 2
By Yuan Zhou
Figure 2: Cascode biasing circuit
bin
b1
b2
M12
b2
b4
b1
icm
b3
Figure 3: CMFB circuit
Vb1
Vb2
M13
Von
Vcmc
M14
Vb3
M15
Vocm
M16
Vop
Vb3
The size of M13/M14/M15/M16
is 50um/0.25um
The size of all other PMOS
transistors is 45um/0.25um
The size of NMOS transistors
is 15um/0.25um
starts clipping. We define it as the output range in which the small signal gain does not
decrease more than 3 dB. The open-loop gain vs. the output differential voltage is simulated
with a open-loop configuration. The largest small-signal gain is 41.5. The peak-to-peak
output swing is larger than 2.9V as shown in Fig. 4.
For the frequency response of the amplifier, the Bode plot is shown as Fig. 5. The poles
are extracted from PZ analysis. After pole zero cancellation, we can find the dominant pole
is located at 2.09 MHz and the non-dominant pole is located at 1.90 GHz. The unity gain
bandwidth of the amplifier is 247 MHz. The phase margin is 82.2 degree.
2
Homework 2
By Yuan Zhou
Figure 4: The open-loop gain vs. the output differential voltage
50
40
Output Swing = 2.95 V
Gain (dB)
30
20
10
0
−10
−3
−2
−1
0
Vout (V)
1
2
3
Amplitude (dB)
Figure 5: The Bode plots of the gain of amplifier
50
0
−50
4
10
6
8
10
10
10
10
Frequency (Hz)
Phase
200
100
0
−100
4
10
6
8
10
10
Frequency (Hz)
3
10
10
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