Semicustom Products
UT90nSDTC-EVB, 3.125 Gbps Quad-lane SerDes Macro
Evaluation Board Data Sheet
February 2014
www.aeroflex.com/RadHardASIC
FEATURES
 Aeroflex UT90nHBD 3.125 Gbps SerDes Macro transceiver, CMOS9SF RadHard-by-Design
 SMA interfaced Quad Full-Duplex High-Speed Serial
CML TX/RX Lanes for easy access to test equipment
 Header connector interfaced Quad Full-Duplex LVDS
TX/RX parallel data lanes for easy access to protocol
data generators
 Dual power supply domains for 1.8V I/O and 1.0V Core
power efficient operation and user evaluation
 Additional CMOS I/O header connector access for functional verification and diagnostics
 Operating range of -55ºC to +125ºC
 Out-of-the-box NI LabVIEW developed user control
GUI for ease of setup and operation
 Supported Protocols:
- 10GBASE-CX4 (IEEE 802.3)
- 10GBASE-KX4
- Rapid IO - Level I (1.25Gbps/2.5Gpbs/3.125Gbps)
- General Purpose 8b10b Protocol with either
156.25MHz or 312.5MHz system clocks
INTRODUCTION
The UT90nSDTC-EVB is a quad-port serial/parallel interface high-speed evaluation board, designed to allow the
ASIC and the system designers an easy access to all the
features of the Aeroflex's UT90nHBD 3.125Gbps quadlane full-duplex SerDes macro. The serial interface consists
of four separate transmit (TX) and receive (RX) CML serial
lanes, fitted with edge-launch SMA connectors, for connecting to an external test instrumentation or another serial
full-duplex device. The parallel interface consists of four
TX/RX 10-bit wide LVDS data lanes, fitted with 20-pin
right-angle header connectors for connecting to external
parallel BERT test equipment or another parallel interface
device, such as an FPGA-based protocol emulator.
The UT90nHBD SerDes macro is XAUI compatible, so
synchronous full-duplex quad-lane operation is fully supported. The SerDes macro implementation on the
evaluation board can also be configured to operate each
serial/parallel lane independently, but at a single data rate
for all four lanes and synchronized to a single PLL reference
input clock.
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GENERAL FEATURES AND OPERATION
The Aeroflex UT90nSDTC-EVB evaluation board is designed to provide the user flexible means to configure, control and channel data thru
the UT90nSDTC quad-lane full-duplex SerDes transceiver, running at data speeds of up to 3.125 Gbps per lane.
The UT90STD-EVB evaluation system has the following main features:
 Two main power domains - I/O 1.8V and Core 1.0V, separated into functional block power sub-domains (TX, RX, PLL) for optimal
SerDes performance and user evaluation flexibility.
 External SPI-enabled microcontroller programming - working in conjunction with a custom-designed software interface, under the
National Instruments LabVIEW development or run-time environments. The user control of the evaluation board is done exclusively
through the use of the software interface and the SPI-enabled microcontroller, eliminating the need for PCB hardware manipulation.
 Parallel LVDS TX/RX interface - enabling flexible user-configurable connection of an external parallel data pattern generator (such as
FPGA prototype board or parallel BERT instrument) for the purposes of running the "user protocol" data through the SerDes transceiver.
 Header connectors for flexible user access to the SerDes transceiver output error-detect indicator signals for the purposes of verifying
the correct operation in various programming modes and configurations.
N4903B J-BERT
Data Out Clock Out
-
+
-
+
Data In
-
ext_clk
+
Clock In
PC w/LabView
USB Cable
+
TXn[0:3]
UT90nSDTC
Characterization PCB
-
4-wire Ribbon
Cable
+
Power Supply
+
RXn[0:3]
+
SPI Port
-
Arduino UNO
Microcontroller
LVDS RXn[4:0]
LVDS TXn[4:0]
PLL REFin
UT90nSDTC
LVDS TXn[9:5]
LVDS RXn[9:5]
+
Reserved
Digital I/O
-
-
+
-
+
TLA 704
Logic
Analyzer
LVDS RXCLKn[0:3]
+
LVDS TXCLKn[0:3]
Power Supply
-
Logic Analyzer
Error Detect I/O
P6417 16-Channel Probe
Figure 1: UT90nSDTC-EVB Evaluation User Test Setup
An example of an evaluation test setup scenario shows a high-performance serial BERT Agilent N4903B, connecting to one of the four
serial TX/RX interfaces of the UT90nSDTC SerDes transceiver (Figure 1). The BERT is used to generate the test serial data pattern, perform
error detection on the received pattern and provide the PLL reference input clock for the SerDes transceiver. The BERT serial data pattern
is sent to the RX serial inputs and is then looped back to the TX serial outputs, through one of the user-configurable modes of operation.
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UT90nSTDC-EVB MODES OF OPERATION
The UT90nSDTC SerDes transceiver is capable of several different user-configurable modes of operation, including built-in self-test
(BIST) and internal/external loopback on both the high-speed serial and the parallel data interfaces. Given here is a brief overview of
each mode of operation.
Figure 2: UT90nSDTC-EVB BIST Loopback Modes
Internal BIST Loopback - the BIST engine of each lane is used to generate the parallel data pattern that is serialized and sent back
internally onto the deserializer block, (light-blue trace in Figure 2).
External BIST Loopback - equivalent to the Internal BIST mode, with the BIST generated parallel data pattern transmitted out of the
TX CML serial outputs and looped back to the RX CML inputs externally, through the use of SMA cables (light-green trace in Figure
2).
Internal RF Loopback - the received serial data pattern is looped back directly onto the internal TX output MUX and the TX CML
outputs, without being processed by the Clock and Data Recovery (CDR)/Deserializer sub-system (bright-red trace in Figure 3).
Internal Serial-Parallel-Serial Loopback - the received serial data pattern on the RX CML inputs, is fully processed by the CDR/
Deserializer sub-system and looped back directly onto the internal TX parallel data bus, to be reserialized and re-transmitted out of the
TX CML outputs (dark-red trace in Figure 3).
LVDS Serial-Parallel-Serial Loopback - equivalent to the Internal Serial-Parallel-Serial loopback, with the external LVDS TX/RX
interface is used to loop the data back from the RX to the TX parallel data bus (bright-purple trace in Figure 3).
LVDS Internal/External Serial Loopback - equivalent to the Internal/External BIST loopbacks, with the BIST engine of a given lane
replaced by an external user parallel data pattern generator (such as a parallel BERT or a "user protocol" FPGA).
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Figure 3: UT90nSDTC-EVB Internal/External Loopback Modes
The following jBERT instrument screen image shows a typical eye-diagram obtained using the UT90nSDTV-EVB evaluation board,
operating in Internal Serial-Parallel-Serial loopback mode.
Figure 4: UT90nSDTC-EVB Eye-Diagram
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UT90nSTDC-EVB PROGRAMMING INTERFACE
The UT90nSDTC SerDes transceiver is equipped with a CMOS 1.8V serial programming interface controlling a serial shift register,
for setting the individual programming values of the control bits on each serial/parallel SerDes lane..
In addition to the internal serial register of the UT90nSDTC, the evaluation board hardware contains two additional IC shift registers
that provide full user functional control capability over the LVDS parallel data I/O buffers, enabling the users to evaluate the performance of the SerDes transceiver independently from the LVDS parallel data interface.
Figure 5: The UT90nSDTC-EVB Ni LabVIEW-based GPUI
The NI LabVIEW-based GUI provides the user with maximum flexibility in setting up and controlling the various control features of
the SerDes transceiver such as reset and power-down, pre-emphasis control, BIST control, Receiver Variable Gain adjustment, Receiver Phase-rotator Delay adjustment, loopback control and etc. for each individual TX/RX data lane independently (Figure 5).
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info-ams@aeroflex.com
Aeroflex Colorado Springs (Aeroflex) reserves the right to
make changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
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