Nuclear Instruments and Methods in Physics Research A 699 (2013) 120–123
Contents lists available at SciVerse ScienceDirect
Nuclear Instruments and Methods in
Physics Research A
journal homepage: www.elsevier.com/locate/nima
ASIC developments for high speed serial data transmission in particle
physics experiments
Datao Gong a, Tiankuan Liu a, Suen Hou b, Da-shung Su b, Ping-Kun Teng b, Annie C. Xiang a, Jingbo Ye a,n
a
b
Department of Physics, Southern Methodist University, Dallas, TX 75275, USA
Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan
a r t i c l e i n f o
a b s t r a c t
Available online 25 June 2012
We report R&D results on two integrated circuit designs: a 5 Gbps 16:1 serializer and a 5 GHz LC phaselocked-loop (PLL). The prototypes were fabricated with a commercial thin-film silicon-on-sapphire
0.25 mm CMOS technology. Both the serializer and the PLL have been evaluated to meet design goals
and tested against operation conditions in the environment of a particle physics detector front-end for
the proposed HL-LHC upgrade.
& 2012 Elsevier B.V. All rights reserved.
Keywords:
ASIC
Data Transmission
Serializer
PLL
1. Introduction
Serial data transmission over optical fibers is used in particle
physics experiments. The transmitting data rate over a single fiber
channel increased from a few megabits per second (Mbps) to
1.6 gigabits per second (Gbps. Example: the optical link that reads
out the Liquid Argon Calorimeter [1], or LAr, in the ATLAS
experiment at CERN). The operation environments require high
system reliability due to lack of frequent access for maintenance
or repair. In some cases the radiation in a particle physics detector
front-end also puts special requirements on the electronics and
optics that operate inside the detector volume [2]. In the upgrade
program for the High Luminosity Large Hadron Collider (HL-LHC)
at CERN, R&D projects are carried out to meet the challenges of
higher radiation tolerance and system reliability, and much
higher data bandwidth with low power dissipation, compared
with the optical link systems now operating in experiments on
the LHC. This is because with the increase of radiation in the
detector front-end, it is advantageous to simplify the front-end
readout electronics by moving all level-1 triggering circuits to the
back-end data acquisition (DAQ) system where frequent access is
possible and there is no or very little radiation in the operation
environment. The price to pay in the data-streaming mode frontend electronics is on the data transmission bandwidth. Taking the
ATLAS LAr optical link as an example, the data throughput will
increase from 1.6 Gbps per front-end board (FEB) to over
100 Gbps per FEB. To meet this challenge, and to address the
needs in many new detectors’ readout R&D, especially those
designs to operate in radiation environment, we have been
n
Corresponding author. Tel.: þ1 214 768 2114.
E-mail address: yejb@smu.edu (J. Ye).
0168-9002/$ - see front matter & 2012 Elsevier B.V. All rights reserved.
http://dx.doi.org/10.1016/j.nima.2012.05.095
working on designs of Application Specific Integrated Circuits
(ASICs) for the transmitting side of an optical link. The final goal
of data throughput in our R&D program is 10 Gbps per fiber. As a
step towards that goal, we prototyped a 16:1 serializer designed
to operate at 5 Gbps, and an LC based phase-locked-loop (PLL)
that runs up to 5 GHz. Both designs are based on a commercial
thin-film silicon-on-sapphire (SOS) 0.25 mm CMOS technology.
The design and measurement results of the serializer are reported
in Section 2, while those for the LC-PLL in Section 3. In the
conclusion we point out our roadmap to the final goal of ASICs
and the link system of 10 Gbps per fiber, or an aggregated
bandwidth of 120 Gbps per FEB.
2. Design and measurement results of the 5 Gbps serializer
ASIC
A functional block diagram of serial data transmission over
fiber optics is shown in Fig. 1. The interface block prepares the
upstream parallel data for serial transmission hence works at a
clock rate that is close to the parallel data clock which is much
lower (by about 8 in this case) than the serial data rate. The
serializer and the optical interface blocks have circuits that work
at the highest clock frequency of the system. For example, for a
5 Gbps serial data rate and circuits using both edges of the clock,
one needs a 2.5 GHz PLL. The optical interface consists of a
(current) laser driver (LD) circuit and a laser. The LD is the same
as a CML line driver with matching modulation current and
impedance of the laser in use. Because of these, we decided to
first prototype a 16:1 serializer with a CML output to gain
experience with this SOS technology. To increase the chances of
success, this design is also based on a ring oscillator PLL as its
clock unit, learned from a successful previous ASIC serializer, the
D. Gong et al. / Nuclear Instruments and Methods in Physics Research A 699 (2013) 120–123
GOL chip, developed for particle physics [3]. This PLL limits the
serial speed to be 5 Gbps. To probe the speed of the technology,
we also implemented a standalone LC based PLL. The design and
testing of this serializer are described in the following subsections
while the LC-PLL is described in Section 3.
2.1. The design of the ASIC
The design of the serializer follows an inverted tree structure
with a cascade of many 2:1 multiplexing units, as shown in Fig. 2.
The advantage of this serializing structure are twofold: one, the
multiplexers operate at lower speeds except the last stage which
runs at the final serial data rate, offering the possibility of ‘‘trading
power for speed’’ only in the last multiplexer which is specially
designed; two, the power-of-2 structure simplifies the design of
the clock unit, which in this particular design is shared with the
PLL divider chain. A divide-by-two divider immediately after the
VCO (voltage controlled oscillator) in the PLL also helps to
maximize the clock speed. The disadvantage of this structure is
a serializing ratio of the power of 2, requiring a possible data
reformatting at the interface stage in front of the serializer. Since
in most applications such an interface ASIC will be needed to
perform many functions such as data framing, scrambling,
redundancy switch, and communication for control and monitoring, adding data bus reformatting to the interface to cope with a
particular application is manageable. The high-speed clock is
synthesized based a ring-oscillator-PLL, also illustrated in Fig. 2.
The PLL can be selected to latch to either the rising or the falling
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edge of the reference clock (the parallel input data clock),
ensuring correctly clocking in the input data. A selection of PLL
low pass filter bandwidth is implemented to cope with different
input clock quality. A static D-Flip–Flop is used to improve the
serializer’s immunity to single event upset caused by ionizing
particles. To achieve the needed speed with these static DFF, its
internal clock and clock-bar are carefully adjusted to ensure the
shortest D-to-Q time.
2.2. The evaluation of the prototype
Testing of the prototype chip was carried out by wire-bonding
it to a PCB. Special caution was exercised for a few very fast
signals both in the PCB design with impedance-matched traces
and in placing the chip for wire-bonding with the shortest
connecting wires. In general electric signal reflection is minimized
by implementing impedance match for all differential signal
traces. For CMOS signal traces, resistors are placed in series to
reduce sharp rising (falling) edge. Shown in Fig. 3(a) is the eye
diagram measurement with an eye mask. A bathtub curve is also
traced with a Bit-Error-Rate-Tester (Anritsu MP1763C/1764C) and
is shown in Fig. 3(b). From both measurements one can extract an
eye opening of 0.69 UI (Unit Interval). Signal rise/fall time,
amplitude of a 100 O differential load, timing jitter in the serial
bit stream, together with different jitter components are listed in
Table 1. The measured power consumption of this ASIC is
463 mW, corresponding to 93 mW/Gbps. This measured power
consumption in room temperature agrees with simulation
within 5%.
2.3. The next step in serializer design
Fig. 1. Block diagram of a fiber optics based serial link system.
Making use of the fact that in most particle physics detector
front-end electronics, all readout channels are based on one
system clock, we decided to design an array serializer, with two
serializing units sharing one LC-PLL. The choice of this architecture is a balance of power saving and high-speed clock distribution. A block diagram of this design is shown in Fig. 4. The
designed serial data rate is 8 Gbps, as shown in the post-layout
simulation of the output eye diagram. The simulated power
consumption of this ASIC is 1200 mW, or 75 mW/Gbps. This
design reaches the highest achievable serial data rate with the
particular process we choose in this SOS technology, with all the
constraints we have, in particular the radiation tolerance
requirement.
Fig. 2. Block diagram design of the 16:1 5 Gbps serializer.
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D. Gong et al. / Nuclear Instruments and Methods in Physics Research A 699 (2013) 120–123
Fig. 3. (a) Eye diagram. (b) Bathtub scan of a 5 Gbps signal with 27 1 PRBS input.
Table 1
Measurement results of the 5 Gbps serializer ASIC.
Errors listed in the table are statistic only.
Parameters (unit)
Value
Amplitude (V)
Rise time (ps)
Fall time (ps)
Total jitter @ BER 10–12 (ps)
Random jitter (ps)
Total deterministic jitter (DJ) (ps)
DJ: Periodic (ps)
DJ: Inter-symbol interference
(ps)
DJ: Duty cycle (ps)
1.16 70.03
52.0 70.9
51.9 71.0
61.6 76.9
2.6 70.6
33.4 76.7
3.0 72.3
3.0 72.3
15.2 73.8
3. Design and measurement results of the 5 GHz LC-PLL
The chosen SOS technology offers high Q inductors. To take
advantage of this, we designed an LC based PLL in the same
prototype submission of the serializer, so one finds reusing many
of the functional blocks from that serializer design. The challenge
in the design is the varactor, the voltage controlled capacitor,
of which the manufacturer does not provide a model for
simulation. Due to schedule and budget constraints, we put a
test bank of varactors together with the LC-PLL design in the same
submission. Reported below are the results of the varactors and
the LC-PLL.
3.1. The varactor results
Several varactors based on the RN and IN transistors are
implemented in the prototype chip and are tested using LCR
meters from Agilent (Model 4263B) and from Stanford Research
System (SR720). The tests were carried out with frequencies from
100 Hz to 100 kHz, provided by the LCR meters. The tests were
also carried out at room temperature and at liquid nitrogen
temperature. Shown in Fig. 5 are the capacitance changes as a
function of the bias voltage with the RN and IN transistor based
varactors. Also shown are the simulation results. We use the
RN transistors in our design. There is a systematic shift between
simulated value and measured capacitance. Since the manufacturer does not provide a reliable simulation model for the
varactors, we decide to take the measured value in our future
designs.
Fig. 4. Block diagram of a 2-lane array serializer design.
3.2. The design of the ASIC and the measurement results
Block diagram of the LC-PLL is shown in Fig. 6. We reuse the
phase-frequency-detector circuit (PFD), the charge-pump circuit
(CP) and the low-pass-filter (LPF) from the ring-oscillator PLL
inside the serializer. The first stage divider is a new design and
works at 5 GHz. In order to test the design, and for lack of a 5 GHz
output driver (we now know this is not possible with the chosen
technology), we reuse the 2.5 GHz CML Driver for the signal
output. We split the signal after the first divider stage, connecting
one branch to the CML Driver. This is illustrated in Fig. 6. Based on
D. Gong et al. / Nuclear Instruments and Methods in Physics Research A 699 (2013) 120–123
123
Fig. 5. Simulated and measured capacitance of RN (left) and IN (right) type of varactors.
Built on these experiences, we are now designing LOCs2, and
LOCld for the optical interface. Simulation results indicate that
both LOCs2 and LOCld should work at 8 Gbps and this is really
what this technology can offer. We will need either change the
system design to work with the speed of 8 Gbps per fiber, or move
to a newer SOS technology to reach higher speeds. The low speed
(below 1 GHz) and mostly digital circuits interface function block
to complete the link transmitting side will be investigated at a
later stage.
Fig. 6. Block diagram of the LC-PLL with the CML output for testing purpose.
Table 2
Measurement results of the 5 GHz LC-PLL ASIC. Errors listed in the table are
statistic only.
Parameters (unit)
Value
Tuning frequency range (GHz)
Power consumption (mW)
Output amplitude, pk–pk (V)
Rise time (ps)
Fall time (ps)
Random jitter (ps)
Deterministic jitter (ps)
4.63 7 0.12 to 4.98 7 0.02
111 7 8
1.23 7 0.09
44.9 7 2.4
44.4 7 2.2
1.3 7 0.3
7.5 7 1.1
simulated varactor tuning range, we thought that we should have
a tuning range from 3.8 GHz to 5.0 GHz of the PLL. A mistake in
the first divider design limited this range to be from 4.6 GHz to
5.0 GHz. This problem has been traced to a design mistake in the
first stage divider and will be corrected in future designs. Listed in
Table 2 are the results of this LC-PLL. The power consumption
does not include those from the CML Driver and the LVDS
receiver.
4. Conclusion
With one MPW run, we have 5 designs. Reported here are the
results of a serializer, a LC-PLL and a testing block of varactors.
Acknowledgments
This work is supported by the US-ATLAS R&D program for the
upgrade of the LHC and the US Department of Energy Grant DEFG02-04ER41299. The authors would like to thank Peter Clarke,
Jay Clementson, Yi Kang, Francis M. Rotella, John Sung, and Gary
Wu from Peregrine Semiconductor Corporation for technical
assistance; Justin Ross at Southern Methodist University for
setting up and maintaining the software environment; Jasoslav
Ban, Mauro Citterio, Christine Hu, Sachin Junnarkar, Valentino
Liberali, Paulo Rodrigues Simoes Moreira, Mitch Newcomer, Quan
Sun, Fukun Tang, and Carla Vacchi for technical assistance and
reviewing of ASIC designs; Hucheng Chen, Francesco Lanni, and
Sergio Rescia at Brookhaven National Laboratory for help on
varactor measurements.
References
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