Sreedhar et al., International Journal of Advanced Engineering Technology
E-ISSN 0976-3945
Research Paper
SUPPLY VOLTAGE FLUCTUATION IMMUNE SHEPWM FOR
MULTILEVEL INVERTERS WORKING WITH FLUCTUATING
DC SOURCES
T.Sreedhar1 and K.Udhayakumar2
Address for Correspondence
1
Research scholar, 2 Assistant Professor (SG), Department of Electrical and Electronics Engineering, CEG
Campus, Anna University, Guindy, Chennai, Tamil Nadu, India
ABSTRACT –
Selective Harmonics Elimination (SHE) technique adds values to multilevel inverter (MLI) based systems. Previously
developed SHE pulse width modulation (SHE-PWM) strategies mainly focused on specific harmonics elimination with equal
and unequal DC sources. DC input voltage of MLI fluctuates dramatically when small DC-link capacitor is used or in
distributed generation systems such as in a photovoltaic systems. The severity of this fluctuation is well received by the
research community when the inverter system utilizes the single phase AC source. An effort is made to compute the
optimized switching angles to eliminate a set of preferred lower order harmonic components of the MLI output voltage even
when DC inputs fluctuate. The proposed supply voltage fluctuation immune SHEPWM (SVFI-SHEPWM) is an ingenious
solution to SHE problem of MLI with fluctuating DC input. The complete algorithmic development of the strategy along with
the MATLAB simulation study is presented. The experimental investigation is carried out with the proto type seven level
MLI using the field programmable gate array (FPGA).
KEYWORDS: Multilevel Inverter, Selective Harmonics Elimination, Fluctuating DC Input, Supply Voltage Fluctuation
Immune SHEPWM.
1. INTRODUCTION
The main function of a multilevel inverter (MLI) is to
synthesize a desired ac voltage waveform from
several DC voltage sources [1]. The MLI produces a
fair approximation to a sinusoidal waveform and if
the number of involved DC sources increases, this
approximation will get better and better. Ideally, as
the number of DC sources approaches infinity, the
staircase waveform will approach the desired
sinusoid [2]-[3]. The multilevel fundamental
switching scheme inherently provides the opportunity
to eliminate certain higher order harmonics by
varying the times at which certain switches are turned
“on” and turned “off”. The MLI offers the merits
such as reduced switch stresses, lower switch ratings,
absence of transformers, increased reliability (if a
component fails, the inverter will still be usable albeit
at a reduced power level) and it has switching
redundancies (more than one way to produce the
desired voltage), low dv/dt, etc. [4]-[5]. Basically,
there are three MLI topologies, viz. diode-clamped,
flying-capacitor
(also referred to as capacitorclamped), and cascaded H-bridges [4]. Several newer
structural options have been evolved recently [5]-[10].
MLIs are widely used in many industrial applications
such as ac power supplies, static VAR compensators,
drive systems, electric vehicle, renewable energy
systems, etc. [11]-[14].
The switching strategies of the MLI are evolved from
the three-level modulation strategies as an extension.
For instance, the multi carrier pulse width modulation
(MCPWM) strategies are simply an extension of
three-level modulation commonly used in voltage
source inverters (VSIs). For an ‘m’ level inverter, (m1) triangular carriers and a reference signal of
fundamental frequency are required for generation
gating signals in an analog platform [15]. A host of
alternatives has been proposed by the researchers for
the past decades to improve the output voltage
harmonic profile [16-18]. One of the significant
advantages of multi-level structure is the harmonic
reduction in the output waveform without increasing
switching frequency or decreasing the inverter output
power. The PWM methods of MLI are high
frequency schemes and contradictory to its prime
motivation. Obviously the fundamental switching
Int J Adv Engg Tech/Vol. VII/Issue I/Jan.-March.,2016/622-631
results in lower order harmonics. Quite simply,
harmonics are a source of electromagnetic
interference (EMI) which can create voltage and
current surges. Without harmonic elimination,
designed circuits would need more protection in the
form of snubbers and EMI filters. The earlier
research found out that the solution to these issues is
selectively eliminating the objectionable harmonic
without increasing the switching frequency. The
cluster of PWM strategies in this domain is named as
selective harmonic elimination PWM (SHEPWM)
are extensively practiced for both three level and
MLIs [19]-[20].
There are some unusual problems prevailing in the
MLI based systems. The first one is unequal voltages
in DC sources either due to sources or due to the
optimal requirements of the application. It is worth
noting that the angles optimized for equal voltage
class will not work well for unequal class [21]. The
problem of eliminating selected lower order
harmonics in a multi-level inverter with equal and
unequal DC sources has been done by solving the
Fourier non-linear transcendental equations of output
voltage [22]. There have been many attempts to
perform SHE in MLI working with unequal voltages.
Genetic Algorithm (GA) based SHE techniques are
used to obtain the optimized switching pattern for
various modulation index when the MLI is working
with both equal and unequal DC sources been
proposed in [23]. The second issue in the MLI is
fluctuation in the DC-Link voltage [24]. In many
applications, the lifetime of the electrolytic capacitor
is the crucial factor to limit the lifetime of the
converter. Large DC-Link capacitor causes high line
current peaks during DC-Link capacitor load. Power
factor correction circuits are traditionally used to
correct line current quality in single phase supplied
inverter systems. Thus, ripple free DC-Link may not
be recommended in few applications due to its
demerits, viz. bulky, heavy, and costly DC-Link
components, slow response, poor input power factor
and huge inrush current. To overcome the problem of
the line current quality and big electrolytic capacitor,
a relatively small film capacitor (MPPF, metalized
polypropylene film capacitor) is embroiled. While
overcoming the problem of the line current waveform
Sreedhar et al., International Journal of Advanced Engineering Technology
and the life time of the electrolytic capacitor, the new
problem is arisen in the form of the heavily
fluctuating DC-Link voltage due to the low value of
the filter/splitting capacitors [25]. This leads to
heavily fluctuating torque. Many dynamically
industrial low performance applications such as
pumps and fans are high inertia loads. Thus, even
heavily fluctuating torque can be tolerated. The
existing SHEPWM strategies and their switch angel
computations perform truthfully when the practical
conditions in system are ideal. In circumference
where DC sources have ripple, the implementation of
SHEPWM strategy experiences a noticeable
deviation from the theoretical values. This mismatch
is due to spectral errors which appear in practical
cases and they are unavoidable. Such condition
which prevails in the drive fed from the single-phase
ac source where the front end converter is a singlephase diode rectifier followed by DC-Link capacitor.
The spectral errors and failure of SHE optimized
switching edges are reasoned by the input amplitude
distortion or fluctuation [26]. The fluctuation in the
input DC voltage has the significant impact on SHE
problem of MLI which has not been focused by the
authors. An ingenious low frequency switching
SHEPWM for input amplitude distortion is needed to
solve this issue.
A fluctuating motor power control has been proposed
to reduce the DC-Link capacitance [27]. The
converter power matching has been the prime idea
where the current oscillation is enforced along the
constant torque line which only affects the reactive
power of the motor. An analysis on electrolytic
capacitor-less inverter, and a strategy for resonance
suppression control for a DC-Link voltage and input
current in electrolytic capacitor-less inverter have
been developed [28]. The aim has been operating the
electrolytic capacitor-less inverter both in the
motoring mode and regenerating mode owing to its
inherent bidirectional power flow capability of the
active front-end rectifier whose switching frequency
is equal to the input line frequency. The dynamic
behavior of an inverter with small DC-Link capacitor
has been studied by simulations and laboratory tests.
The developed modulating principle and differential
space vector pulse width modulation (DSVPWM)
could deal with heavily fluctuating DC-Link voltage
and produce correct voltage vector with high
accuracy [29]. A general DC-Link voltage balancing
control method for MLIs based on a generalized
space vector PWM (SVPWM) scheme has been
advocated. The discussion includes an optimal
switching sequence and the optimal duty cycles for
DC-Link voltage balancing control [30]. An idea of
modified flux weakening strategy incorporated
induction drive for an electrolytic capacitor-less
inverter has been evolved. The requirements like the
decoupling of the fluctuation and maximum
utilization of the DC-Link voltage are well dealt with
the developed scheme without affecting its stability
[31]. To handle the DC-Link fluctuation, the concept
of “average voltage constraint” has been proposed
[32].
From the detailed literature survey, it is understood
that DC-Link fluctuation has been identified as
problem in VSI based systems. Hitherto, the attempts
are not ready for the existing PWM methods to work
Int J Adv Engg Tech/Vol. VII/Issue I/Jan.-March.,2016/622-631
E-ISSN 0976-3945
with such rippled dosed conditions. Many studies did
not include this fluctuation due to obscure
characteristics. No effort is noticed in the literature to
solve the SHE problems in amplitude distorted
atmosphere. This paper proposes an effectual
technique named as Supply Voltage Fluctuation
Immune (SVFI) SHEPWM technique, for eliminating
selected lower order harmonics in the MLI when the
input source is fluctuating DC voltage. The
simulation and experimental studies have been
carried out for a single-phase seven level inverter.
The detailed discussion and solutions are provided
for two cases, viz. without DC-Link capacitor and
with 33μF DC-Link capacitor. The proposed SVFISHEPWM method is simulated in the MATLAB tool
and later test in the proto type single phase seven
level MLI using Field Programmable Gate Array
(FPGA) processor.
2. PROBLEM DEFINITION
Earlier contributions on SHE technique applied to
MLIs assumed the DC sources either as equal values
or unequal values, but do not vary with time. In these
cases, the switching angles must be updated
constantly in order to perform SHE effectively
because it is worthwhile to know that the switching
angles calculated for performing SHE with equal DC
sources does not work for unequal DC sources. As
per the literature survey, research work on SHE for
multilevel inverter with different DC sources is
carried out only for the past one decade. Recent
researchers have attempted to solve the SHE problem
for unequal DC sources. But SHE for MLI with
fluctuating DC sources is still unattainable. Also for
accurate representation of every solution for
fluctuating DC source requires more tedious and
complex calculations. Even though it is obvious that
MLI circuit may possess both of the above said
problems concurrently, it is mind boggling that the
issue with fluctuated DC input sources have not been
attempted yet.
To understand the above said problem, an example
system of single-phase seven level cascaded MLI is
taken as indicated in Fig.1. The typical seven level
output voltage, individual H-bridges' outputs, and
switching instants are marked in Fig.2.
The MATLAB simulated harmonic spectra of the
output voltages results for constant and equal DC
sources, constant and unequal DC sources, and equal
and fluctuating DC input sources are pictured
respectively in Fig.3, Fig.4, and Fig.5. The switching
angles for all the three spectrum are considered as
θ1=15degree, θ2=45degree and θ3=75degree. From
the figures, it is inferable that for the same switching
instant the fundamental and the THD of the spectrum
vary and thus imply that the switching angles will not
be the same for attaining the required fundamental
voltage. In addition, it is observable that the total
harmonic distortion (THD) is minimized when
optimized DC sources are employed. When the
input is fluctuating, the lower order harmonics are
further induced by directly increasing the THD.
The effects on the fundamental components (peak
value) can also be noticed.
The single phase seven level cascaded MLI which is
fed by three separate constant DC sources and three
diode-bridge rectifier with DC-Link are shown in
Fig.6.
Sreedhar et al., International Journal of Advanced Engineering Technology
E-ISSN 0976-3945
Fig.1. Seven-level cascaded multilevel inverter
Fig.2. Output voltage of seven-level cascaded multilevel inverter
Fig.3. Harmonic spectrum – Equal and constant DC input voltages
Fig.4. Harmonic spectrum – Unequal, constant and optimized DC input voltages
Fig.5. Harmonic spectrum – Equal and fluctuating DC input voltages
Fig.6. Seven level cascaded MLI with constant and fluctuating DC input sources
Int J Adv Engg Tech/Vol. VII/Issue I/Jan.-March.,2016/622-631
Sreedhar et al., International Journal of Advanced Engineering Technology
E-ISSN 0976-3945
The three phase MLI essentially triplicates the above structure. The typical output voltage waveforms are
obtained when DC sources are steady and fluctuating. And they are shown in Fig.3.
Fig.7. Output voltage waveform of MLI with constant and fluctuating DC sources
The output voltage equation of the inverter with constant DC input sources is given by
4V
(1)
Vn  dc [cos(n1 )  cos(n 2 )  cos(n3 )]
n
Where Vdc is time invariant. But in case when the rectified DC input the voltage is fluctuating, relation (1) is not
valid and Vdc is time variant. Hence an effective SHEPWM scheme should form the output voltage equation of
the MLI when the input DC sources are fluctuating.
2. Principle of the Proposed SVFI Technique
Fig.8. Flowchart for SVFI-SHEPWM Technique
Fig.8 represents the comprehensive steps involved in the proposed SVFI-SHEPWM technique. For the available
DC-Link capacitor, the DC-Link voltage-time plot is drawn and the equation of the same is obtained from curve
fitting techniques. Application of the Fourier analysis paves the harmonic voltage equation. At this stage, the
switching instant to selectively eliminate the specified harmonics can be computed through either NewtonRaphson method or through Genetic Algorithm (GA). The obtained switching angles can be validated. Similarly
for any different DC-link capacitor values, these steps may be followed.
4. Formulation of SVFI-SHEPWM Technique
As mentioned before, to find the output voltage equation of the MLI with fluctuating DC input sources, it is
essential to know the DC-Link voltage equation. Some of the standard DC-Link capacitor values such as 22
μF/450V, 33μF/450V, 330μF/450V, 2200μF/200V, etc. while results are discussed for 33μF/450V and capacitorless DC-link.
4.1 SVFI-SHEPWM without DC-Link capacitor
Int J Adv Engg Tech/Vol. VII/Issue I/Jan.-March.,2016/622-631
Sreedhar et al., International Journal of Advanced Engineering Technology
E-ISSN 0976-3945
Fig.9. Performing curve fitting for DC-Link voltage – without DC-Link capacitor
For performing curve fitting the DC-Link voltage, datum should be retrieved from the workspace and plotted
again in the curve fitting tool in MATLAB. Then for the curve data, fitting is performed as evidenced in Fig.9.
There are different fitting techniques but for DC-Link curve, Fourier fitting is employed for high precision and
accuracy.
The equation of the DC-Link voltage without DC-Link capacitor is given as
f ( i )  a 0  a 1 cos(  i w )  b1 sin(  i w )  a 2 cos( 2 i w )  b2 sin( 2 i w )  a 3 cos( 3 i w )
 b3 sin( 3 i w )  a 4 cos( 4 i w )  b 4 sin( 4 i w )
(2)
a 0  30 .25 ; a 1   21 .17 ; b1  0 .0685 ; a 2   4 .194 ; b 2  0 .0179 ;
a 3   1 . 769 ; b3   0 .002523 ; a 4   0 . 9574 ; b 4   0 .02985 ; w  2;
This DC-Link voltage equation as the input function of Fourier analysis is performed by formulating the output
voltage equation of the MLI with fluctuating DC input sources. The Fourier expansion is given as
f (t ) 
a0

2


(3)
( a n cos n  t  b n sin n  t )
n 1
Since the output waveform of the MLI is odd-quarter wave symmetry, the Fourier coefficients a0=an=0. As it
is an odd function, bn = 0 for all even values of 'n'

bn 
4

[

2

f ( 1 ) sin( n  t ) dt 
1

2

f ( 2 ) sin( n  t ) dt 
2
2

f ( 3 ) sin( n  t ) dt ]
(4)
3
Consider


2

f ( 1 ) sin( n  t ) dt  A ( 1 );
1

2
Therefore,
bn 
4


2
2
f ( 2 ) sin( n  t ) dt  A ( 2 );  f ( 3 ) sin( n  t ) dt  A ( 3 )
(5)
3
[ A( 1 )  A( 2 )  A( 3 )]
(6)
By solving (5), it is obtained as
  0.014925 sin[( n  8) *  i ]    0.0012615 sin[( n  6) *  i ]   0.00895 sin[(n  4) *  i ] 
A( i )  
  
  

n8
n6
n4

 0.03425 sin[(n  2) *  i ]    0.03425 sin[( n  2) *  i ]    0.00895 sin[( n  4) *  i ] 

  
  
 
n2
n2
n4

 0.0012615 sin[( n  6) *  i ]   0.014925 sin[( n  8) *  i ]   0.4787 cos[(n  8) *  i ] 




n6
n8
n 8

 
 

 0.8845 cos[(n  6) *  i ]   2.097 cos[(n  4) *  i ]  10.585 cos[(n  2) *  i ]   30.25 cos[(n) *  i ] 

  
  
  

n6
n4
n2
n
10.585 cos[(n  2) *  i ]   2.097 cos[(n  4) *  i ]   0.8845 cos[(n  6) *  i ]   0.4787 cos[(n  8) *  i ] 

  
  
  

n2
n4
n6
n8

(7)
It is noticeable that in (7) all the 'sin' terms are nearer to zero. Therefore, by neglecting all the 'sin' terms, the
equation is approximated and thus reducing the size of the equation. The approximated equation is given as
Int J Adv Engg Tech/Vol. VII/Issue I/Jan.-March.,2016/622-631
Sreedhar et al., International Journal of Advanced Engineering Technology
E-ISSN 0976-3945
 0.4787 cos[(n  8) *  i ]   0.8845 cos[(n  6) *  i ]   2.097 cos[(n  4) *  i ] 
A( i )  
  
  

n 8
n6
n4

10.585 cos[(n  2) *  i ]   30.25 cos[(n ) *  i ]  10.585 cos[(n  2) *  i ] 

  
  

n2
n
n2

(8)
 2.097 cos[(n  4) *  i ]   0.8845 cos[(n  6) *  i ]   0.4787 cos[(n  8) *  i ] 

  
  

n4
n6
n 8

V n  bn 
4

(9)
[ A( 1 )  A( 2 )  A( 3 )]
   0 . 4787 cos[( n  8 ) *  1 ]   0 . 8845 cos[( n  6 ) *  1 ]   2 . 097 cos[( n  4 ) *  1 ]  









n8
n6
n4
 
 



   10 . 585 cos[( n  2 ) *  1 ]   30 . 25 cos[( n ) *  1 ]   10 . 585 cos[( n  2 ) *  1 ]  




 




n2
n
n2
 
 
 
 

   2 . 097 cos[( n  4 ) *  ]   0 . 8845 cos[( n  6 ) *  ]   0 . 4787 cos[( n  8 ) *  ]  

1
1
1








n4
n6
n8
 
 







0
.
4787
cos[(
n

8
)
*

]
0
.
8845
cos[(
n

6
)
*

]
2
.
097
cos[(
n

4
)
*

]






2
2
2







 
 



n

8
n

6
n

4







 
  10 . 585 cos[( n  2 ) *  2 ]   30 . 25 cos[( n ) *  2 ]   10 . 585 cos[( n  2 ) *  2 ] 

Vn  (4 /  ) *   

  
  

  
n2
n
n2

 

2
.
097
cos[(
n

4
)
*

]
0
.
8845
cos[(
n

6
)
*

]
0
.
4787
cos[(
n

8
)
*

]






 
2
2
2







  
n4
n6
n8
 
 
 


   0 . 4787 cos[( n  8 ) *  3 ]   0 . 8845 cos[( n  6 ) *  3 ]   2 . 097 cos[( n  4 ) *  3 ]   
 


 
n8
n6
n4
 
 
 
 
   10 . 585 cos[( n  2 ) *  3 ]   30 . 25 cos[( n ) *  3 ]   10 . 585 cos[( n  2 ) *  3 ] 




  



n2
n
n2
 
 


  
   2 . 097 cos[( n  4 ) *  3 ]   0 . 8845 cos[( n  6 ) *  3 ]   0 . 4787 cos[( n  8 ) *  3 ]   
  


 
n4
n6
n8
 
 
  
  
(10)
Equation (10) is the output voltage equation of the MLI without DC-Link capacitor. This is a non-transcendental
equation. To solve this equation, NR algorithm is used and the switching angles eliminating selected lower order
harmonics are calculated [22].
4.2 SVFI-SHEPWM with 33μF DC-Link Capacitor
The same procedure as mentioned above is done for another case with DC-Link capacitor (33μF).
Fig.10. Perform in curve fitting for DC-Link voltage – with 33μF DC-Link capacitor
The DC-Link voltage equation with DC-Link capacitor - 33μF is given as
f ( i )  a 0  a 1 cos(  i w )  b1 sin(  i w )  a 2 cos( 2  i w )  b 2 sin( 2  i w )
 a 3 cos( 3 i w )  b 3 sin( 3 i w )
a 0  30 . 63 ; a 1   20 . 43 ; b1   0 . 04044 ; a 2   3 . 491 ; b 2   0 . 1315 ;
(11)
a 3   1 . 118 ; b 3   0 . 1967 ; w  2 ;
With (11), the Fourier analysis is done to find the output voltage equation of the MLI with DC-Link capacitor 33μF.
Int J Adv Engg Tech/Vol. VII/Issue I/Jan.-March.,2016/622-631
Sreedhar et al., International Journal of Advanced Engineering Technology

bn 
4
[


2


f (  1 ) sin( n  t ) dt 
1

2


f (  2 ) sin( n  t ) dt 
2
E-ISSN 0976-3945
2
f (  3 ) sin( n  t ) dt ]


3
(12)
Consider



2
f (  1 ) sin( n  t ) dt  A (  1 );
1



2
f (
2
) sin( n  t ) dt  A ( 
2
);
2


2
f (  3 ) sin( n  t ) dt  A (  3 )
3
(13)
Therefore,
bn 
4

[ A ( 1 )  A ( 2 )  A ( 3 )]
(14)
By solving (13) and substituting in (14), the output voltage equation is given as
   0.559 cos[( n  6) *  1 ]  1.745 cos[( n  4) *  1 ]  10.215 cos[( n  2) *  1 ]   



  
n6
n4
n2
 
 
  

    30.63 cos[( n ) *  ]  10.215 cos[( n  2) *  ]  1.7455 cos[( n  4) *  ]   
1
1
1
  


 
n
n

2
n

4





 

   0.559 cos[( n  6) *  ] 
 
1
  
 

n6
  

 


   0.559 cos[( n  6) *  2 ]   1.745 cos[( n  4) *  2 ]   10.215 cos[( n  2) *  2 ]  
 
 
 
  
n6
n4
n2
 
 
 
 

    30.63 cos[( n ) *  2 ]  10.215 cos[( n  2) *  2 ]  1.7455 cos[( n  4) *  2 ]  
V n  ( 4 /  ) *   


 
n
n2
n4
 
 
 
  



 0.559 cos[( n  6) *  2 ] 

  

n6


  
   0.559 cos[( n  6) *  ]  1.745 cos[( n  4) *  ]  10.215 cos[( n  2) *  ]   
3
3
3
 


 
n6
n4
n2
 
 
 
 
   30.63 cos[( n ) *  ]

10.215 cos[( n  2) *  3 ]  1.7455 cos[( n  4) *  3 ]   
3 
   



 
 
 
  
n
n2
n4
 
 

 

   0.559 cos[( n  6) *  3 ] 
  (15)

  
n6

 
Equation (15) is the output voltage equation of the MLI with 33μF DC-Link capacitor. This is a nontranscendental equation so to solve this equation NR algorithm is used and the switching angles eliminating
selected lower order harmonics are calculated.
4.3 Validation of Arrived Equations
Equations (10) and (15) form the output voltage equation of the MLI operating with fluctuating DC sources
respectively without DC-Link capacitor and with 33μF DC-Link capacitor. Thus for validating the newly
formed output equations the simulated and theoretical results are compared in Tables 1 and 2 for V1
(fundamental), V3, V5, V7, V9, V11, V13, V15, V17, V19, V21, and V23 with different level of fluctuations
respectively. The close association of the simulated harmonic values and the values obtained through the
equations is found.
Table 1. Validation – without capacitor
Harmonics Voltage Vn
V1 (Fundamental)
V3
V5
V7
V9
V11
V13
V15
V17
V19
V21
V23
Theoretical (V)
102.9136
31.3105
5.1187
5.0863
5.5477
5.6929
4.1282
4.5807
1.6824
1.7722
2.8723
2.6467
Int J Adv Engg Tech/Vol. VII/Issue I/Jan.-March.,2016/622-631
Simulated (V)
101.6
32.13
4.98
5.1
6.51
5.9
4.15
4.59
1.66
1.7
2.97
2.67
Sreedhar et al., International Journal of Advanced Engineering Technology
E-ISSN 0976-3945
Table 2. Validation – with 33μF capacitor
Harmonics Voltage Vn
V1 (Fundamental)
V3
V5
V7
V9
V11
V13
V15
V17
V19
V21
V23
Theoretical (V)
102.86
31.3914
4.859
5.6342
6.6716
5.9345
4.1479
4.4773
1.6508
1.6219
2.8885
2.696
Simulated (V)
102.03
31.04
6.03
4.68
6.37
6.4
4.72
4.13
1.96
1.65
2.8
2.99
5. SIMULATION RESULTS
The simulation of seven level MLI with fluctuating DC input sources is carried out for various modulation
indices in MATLAB 7.12 software package. The switching angles are calculated for various modulation indices
using Newton-Raphson algorithm for eliminating seventh and ninth harmonics. The average value of fluctuating
DC source voltages are taken equal as V1=V2=V3= 50V without DC-Link capacitor while the load is resistive 100Ω/phase. The output fundamental voltages, THD, and individual (V5 and V7 in percentage) of seven-level
inverter with various modulation indices are obtained in NR based SVFI-SHEPWM method with and without
DC-Link capacitor respectively in Table 3 and Table 4. Similarly, the complete solutions for both the cases
through GA optimization are listed in Table 5 and Table 6. Comparing the results of GA toolbox based firing
angles with NR based firing angles, it is inferable that the switching angles are similar in both the cases with
negligible variations.
Table 3. Switching angles by NR based SVFI SHE-PWM – without DC-Link capacitor
Modulation
index
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
Firing angle (degrees)
α1
29.9999
25.5205
15.7142
42.1549
34.3765
23.3268
6.8753
17.3392
13.7227
0.01506
α2
89.9015
54.8794
48.402
43.7654
46.1515
43.5754
34.5196
17.3392
13.7226
0.05189
Fundamental voltage (V)
α3
59.9223
87.4036
85.4515
74.1014
68.3994
64.6522
61.6747
57.1332
51.8376
0.77229
Theoretical
75
82.5
90
97.5
105
112.5
120
127.5
135
142.5
Simulated
73.55
81
88.58
96.81
104.1
111.3
118.9
125.7
130
143.3
THD
%
40.41
38.11
32.61
49.02
43.81
36.29
27.87
21.89
18.94
1.97
V5
V7
(% of V1)
0.88
0.5
0.24
0.36
0.17
0.09
0.47
0.52
0.34
0.05
0.06
0.11
0.23
0.17
0.28
0.59
2.44
3.2
0.85
0.6
Table 4. Switching angles by NR based SVFI SHE-PWM – with 33μF DC-Link capacitor
Modulation
index
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
Firing angle (degrees)
α1
α2
α3
29.9983
89.5813
60.3499
33.988
55.5768
84.942
17.0222
49.5523
84.709
38.9181
47.0611
74.0734
31.9107
47.5095
68.5599
19.5283
42.7739
65.6673
0.05517
32.4127
62.5138
16.5898
16.5898
58.3691
13.7623
15.2837
54.1309
0.07710
0.34164
0.35504
Fundamental voltage (V)
Theoretical
Simulated
75
73.57
82.5
81.23
90
88.96
97.5
96.41
105
104
112.5
111.7
120
118.9
127.5
124.9
135
128
142.5
143.3
THD
%
40.94
46.29
33.51
48.04
43.06
34.16
26.94
21.87
19.93
1.97
V5
V7
(% of V1)
1.83
0.6
1.74
0.72
2.18
0.76
1.51
0.9
1.54
0.73
1.86
0.73
0.53
1.58
1.05
0.34
1.23
2.61
0.85
0.6
Table 5. Switching angles by GA based SVFI SHE-PWM – without DC-Link capacitor
Modulation
index
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
Firing angle (degrees)
α1
α2
α3
30.3327
59.9228
89.8260
25.2644
54.8612
87.4401
15.6368
48.3854
85.4552
42.1598
43.7039
74.1604
34.4003
46.1733
68.3935
23.3369
43.586
64.6452
6.59394
34.4897
61.6777
17.1247
17.5608
57.1431
13.4420
14.0202
51.881
0.01506
0.05189
0.77229
Int J Adv Engg Tech/Vol. VII/Issue I/Jan.-March.,2016/622-631
Fundamental voltage (V)
Theoretical
Simulated
75
73.46
82.5
81.05
90
88.59
97.5
96.77
105
104.1
112.5
111.3
120
118.9
127.5
125.7
135
130
142.5
143.3
THD
%
40.67
37.98
32.59
48.97
43.93
36.29
27.87
21.9
18.99
1.97
V5
V7
(% of V1)
0.76
0.62
0.35
0.36
0.15
0.12
0.41
0.61
0.39
0.04
0.06
0.11
0.22
0.16
0.31
0.57
2.42
3.16
0.85
0.6
Sreedhar et al., International Journal of Advanced Engineering Technology
E-ISSN 0976-3945
Table 6. Switching angles by GA based SVFI SHE-PWM – with 33μF DC-Link capacitor
Modulation
index
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
α1
28.3195
25.1781
17.0537
38.7220
31.9672
19.5402
0.32426
16.0074
13.6595
0.07710
Firing angle (degrees)
α2
α3
60.3674
89.9580
55.4931
87.0628
49.5329
84.7121
47.2020
74.0551
47.4987
68.5664
42.7887
65.6628
32.4365
62.5271
17.2349
58.3894
15.1612
54.1062
0.34164
0.35504
Fundamental voltage (V)
Theoretical
Simulated
75
73.6
82.5
81.19
90
88.96
97.5
96.47
105
103.9
112.5
111.7
120
119.4
127.5
124.9
135
128
142.5
143.5
The experimental system suggested to implement the
proposed SVFI-SHEPWM, diode rectifiers, DC-link
capacitors, seven level cascaded MLI, a personal
computer, SPARTAN-6 FPGA (XC6SLX45) device
and a load. The proposed SVFI-SHEPWM
architecture is designed using the VHDL language.
The functional simulation of the architecture has
been carried out using the tool ModelSim 6.3. The
Register Transfer Level (RTL) level verification and
implementation are done using the synthesize tool
Xilinx ISE 13.2. Then the designed architecture is
configured to the SPARTAN-6 FPGA (XC6SLX45)
device. The functionality of each block in the
architecture is simulated thoroughly using the
ModelSim software. The RTL view of the developed
architecture is shown in Fig.11 while representative
harmonic spectrum of the output voltage is presented
in Fig.12.
THD
%
39.11
38.4
33.51
47.99
43.11
34.19
26.02
21.82
19.76
2.61
V5
V7
(% of V1)
1.96
0.56
1.79
0.66
2.18
0.76
1.62
0.92
1.53
0.7
1.83
0.75
2.17
0.14
1.03
0.32
0.96
2.84
0.78
0.56
current and limit the voltage distortion that the
harmonic current can produce. Replacing the large
electrolytic capacitor by a small film capacitor the
input current quality is improved but the output
currents are distorted by low order harmonics. This
results in the DC-link voltage fluctuation problem
which is more serious for an inverter system which
utilizes a single phase ac source.
It is implausible that SHE technique has not been
attended for MLI’s working with fluctuating DC
sources till date. In this paper, it is validated that the
optimized switching angles calculated for eliminating
the lower order specific harmonics with constant DC
sources do not match when there is fluctuation in the
source. Thus a new algorithm SVFI SHE-PWM
technique is proposed and the output voltage
equation of the MLI is formulated through the
proposed technique and validated. The obtained nontranscendental equation is solved using either NR
algorithm or GA MATLAB toolbox for eliminating
selected lower order harmonics (5th and 7th
harmonics). Two typical cases, viz. without DC-Link
capacitor and with 33μF DC-Link capacitor are
demonstrated.
REFERENCES
1.
Fig.11. RTL view of the developed architecture
2.
3.
4.
Fig.12. Representative harmonic spectrum Experimental
5.
6. CONCLUSION
In voltage source inverters (VSI), relatively large delink capacitors are used to provide stable DC-Link
voltage and energy storage. However electrolytic
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MPPF-type capacitor the line current harmonic
content is improved and the unreliable electrolytic
capacitor can be omitted. Several power quality
standards like IEEE519 and EN50160 provide
guideline limits on the amount of the harmonic
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